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AN1836
Freescale Semiconductor, Inc.
FLASH Programming Motorola MC68HC912 Microcontrollers
Matt Ruff Body Electronics Occupant Safety Systems Engineering Austin, Texas
Introduction
This document outlines basic routines that demonstrate program erase FLASH EEPROM MC68HC912 Family microcontrollers (MCU) through background debug mode (BDM) interface using Motorola serial debug interface (SDIL) SDBUG12 software (version 2.15) from Microcomputer Systems, Inc. SDBUG12 software interface tool SDIL hardware, which allows background monitoring M68HC12 Family MCUs. Information pertaining proper conditioning handling external voltage supply used program FLASH EEPROM (electrically erasable programmable read-only memory) also included. Care must taken ensure proper programming prevent damage device data corruption memory array. This application note provides updated information engineering bulletin titled Erasing Programming FLASH EEPROM MC68HC912B32, Motorola document order number EB183/D, addition much greater detailed description programming voltage supply considerations needed design application.
Motorola, Inc., 2000
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Freescale Semiconductor, Inc. Application Note
Kbytes embedded FLASH EEPROM primary reason MC68HC912B32 device useful. This module serves electrically programmable erasable, non-volatile ROM-like memory, allowing storage program code which: Must executed frequently Must executed high speeds Might need upgraded field later
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programming routines registers referred this document pertain MC68HC912B32 device. However, concepts covered here hold entire MC68HC912 FLASH Family other Motorola microcontrollers which share this same FLASH technology (also called 1.5T FLASH EEPROM FLASH technology). Included this list M68HC16 683xx Families. Some newest M68HC12 Family devices moving FLASH technology contain part number differentiate FLASH technology used (for instance, MC68HC912D60A).
FLASH EEPROM Control Block
FLASH EEPROM controlled 4-byte register block, which located address $00F4 upon reset. Within this block four singlebyte registers: Lock control register, FEELCK Module configuration register, FEEMCR Module test register, FEETST Module control register, FEECTL
more detail these control registers, refer Section FLASH EEPROM Registers MC68HC912B32 MC68HC912BE32 Advance Information, Motorola document order number MC68HC912B32/D. This section found appropriate documents M68HC12 Family MCUs. sequence these registers covered later this document.
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Application Note FLASH EEPROM Control Block
FLASH EEPROM Lock Control Register
FEELCK register (located $00F4) contains only LOCK (bit which allows prevents writing FEEMCR register. This must cleared change FEEMCR. Note that cleared reset.
Address: $00F4 Read: Write:
LOCK
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Reset:
Figure FLASH EEPROM Lock Control Register (FEELCK)
FLASH EEPROM Module Configuration Register
FEEMCR register (located $00F5) contains only BOOTP (bit which protects 2-Kbyte boot block Kbyte early mask sets G86W G75R) located $7800-$7FFF. This must cleared, after FEELCK (LOCK bit) cleared, write erase boot block.
Address: $00F5 Read: Write: Reset:
BOOTP
Figure FLASH EEPROM Module Configuration Register (FEEMCR)
FLASH EEPROM Module Test Register
FEETST register (located $00F6) effect always reads normal modes operation.
Address: $00F6 Read: Write: Reset:
Figure FLASH EEPROM Module Test Register (FEETST)
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Freescale Semiconductor, Inc. Application Note
FLASH EEPROM Control Register FEECTL register (located $00F7) controls actual programming erasing FLASH EEPROM. this register, five bits used control FLASH. bits upon reset.
Address: $00F7 Read: Write: Reset:
FEESWAI
SVFP
ERAS
ENPE
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Figure FLASH EEPROM Control Register (FEECTL) FEESWAI FEESWAI (bit controls behavior FLASH EEPROM clock while wait mode. SVFP SVFP (bit status bit, when near normal programming voltage levels; clear otherwise (read only). This guarantee that within specified tolerances should used only secondary check. ERAS ERAS (bit when set, configures array erasure. (bit when set, enables programming latches. ENPE ENPE (bit when set, applies programming/erase voltage array.
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Application Note Hardware Configuration
Hardware Configuration
Setting Debugging Hardware
Since programming FLASH EEPROM takes finite amount time dependent reliable programming voltage from exterior source, difficult tell procedure worked immediately. Also, should verified some sort external signal. simplify debugging process, using hardware techniques that listed this application note. debugging hardware, simply light-emitting diodes (LED), connected port pins MC68HC912B32 device error sequence successfully complete indicators. with code listed here, connect PA0, with current limiting resistor indicate errors. like manner, connect green indicate that process completed successfully. Refer Figure connections.
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MC68HC912B32
GREEN (OK)
(ERROR)
Figure Debugging Hardware Connections Setting M68HC12B32EVB sure connect programming voltage (VFP) source M68HC12B32EVB with proper polarity. allows connected board, jumper actually transfers (pin microcontroller. default location applies pin, jumper should always located here maintain voltage when programming erasing occurring. Figure locations Refer Evaluation Board User's Manual, which comes with M68HC12 evaluation board, Motorola part order number M68EVB912B32, detailed connection information.
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JUMPER APPLY PIN.
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Figure M68EVB912B32 Evaluation Board Connections M68HC12B32EVB designed used evaluation purposes only does have sufficient protection against improper voltage levels production level system. Refer Example Protection Circuitry this document more detailed circuit information proper circuit design protection FLASH EEPROM MCU.
NOTE:
should 11.4-11.8 volts mask sets 1H91F 3H91F. other masks, 11.4-12.6 volts volts ±5%).
Software Considerations
Using SDBUG12 manipulate FLASH EEPROM requires some special considerations. First, bugs some versions software cause confusion when manipulating FLASH memory array. memory display windows sometimes refresh properly, sometimes showing addresses value even addresses another value. this problem, issue RESET command from SDBUG12 command prompt force SDBUG12 refresh display windows from once part comes reset.
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Application Note Software Considerations
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routines that follow were tested with version 2.15 SDBUG12 running Windows workstation window. problem described preceding paragraph appear when executing these routines. SDBUG12 displayed proper values FLASH array when routines were allowed completion. Both code segments included here loaded into part same time since they overlap. LOAD command SDBUG12 load each segment into RAM. Notice that entry point program routine $80A entry point erase routine $90A. Once loaded into RAM, command will begin programming process will begin erase process. detailed description software commands SDBUG12, refer documentation from Microcomputer Systems, Inc.
NOTE:
Once FLASH array been erased programmed, reloading DBUG12 monitor code into FLASH array necessary that monitor used, manipulation array will have destroyed this code. This accomplished with bootloader boot block part using software programming tool, such Prog12s, which product Microcomputer Systems, Inc. using M68EVB912B32 evaluation board, refer Evaluation Board User's Manual, which comes with evaluation board, further information reload monitor program into device using on-board bootloader.
General Notes Coding FLASH Programming Erasing
routines used this application note designed reference purposes. Programming erase routines always should downloaded device time programming through through CAN, J1850, other communication link. code these algorithms should resident device during normal operations. reason including these routines FLASH EEPROM prevent possible activation code runaway situation. code gets
Windows registered trademark Microsoft U.S. other countries.
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Freescale Semiconductor, Inc. Application Note
"lost," possible that programming voltage could applied array time much longer than specifications allow, resulting corruption data. Obviously, implementing FLASH-modifying code, such bootloaders stored FLASH, could result such case microcontroller were lost start executing code random point.
NOTE:
cases such this, great care must taken test code make certain that FLASH modification routines cannot activated accidentally. these routines must located non-volatile memory (NVM), other ways safeguard against code runaway possible. instance, assembly opcodes interlaced with software interrupt (SWI) instructions, splitting instruction which modifies FEECTL register apply programming voltage array prevents accidental modification that register. actually code, that section code would need reconstructed copying bytes from their interlaced location using message from CAN, J1850, SCI, etc., which contains decryption locations scrambled opcodes. instructions essential, would ensure that device would execute code were lost this region, alerting engineer possible dangerous condition. This concept complicated beyond scope this application note. mentioned here only offer possible alternative avoid accidental activation program erase routines. other major reason simply leave program erase routines interest software reuse. newer devices developed newer FLASH technologies emerge, algorithms programming erasing these routines also being refined. algorithms themselves downloaded dynamically target devices time programming, newest algorithms utilized with little impact target system. This allows target system software remain FLASH technology independent, minimizing engineering time required code development testing.
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Application Note Programming FLASH Array
Programming FLASH Array
Programming FLASH EEPROM accomplished this step-bystep procedure. voltage must proper level prior executing step first time. Apply program/erase voltage pin. Clear ERAS FEECTL register establish program mode enable programming address data latches. Write data valid address. address data latched. BOOTP asserted, attempt program address boot block will ignored. Apply programming voltage setting ENPE. Delay programming pulse, tPPULSE. Remove programming voltage clearing ENPE. Delay while high voltage turning off, tVPROG. Read address location verify that been programmed. location programmed, repeat steps through until location programmed until specified maximum number program pulses, nPP, been reached. location programmed, repeat same number pulses required program location. This provides percent program margin. Read address location verify that remains programmed. Clear LAT. there more locations program, repeat steps through Turn VFP. Reduce voltage VDD. flowchart Figure demonstrates recommended programming sequence.
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START PROG TURN CLEAR MARGIN FLAG CLEAR PROGRAM PULSE COUNTER (nPP) CLEAR ERAS WRITE DATA ADDRESS
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ENPE DELAY DURATION PROGRAM PULSE (tPPULSE) CLEAR ENPE DELAY BEFORE VERIFY (tVPROG) MARGIN FLAG SET? DECREMENT COUNTER DATA CORRECT? DATA CORRECT? CLEAR LOCATION FAILED PROGRAM INCREMENT COUNTER READ LOCATION MARGIN FLAG
NEXT ADDRESS/DATA
DONE? TURN
DONE PROG
Figure Programming Sequence Flowchart
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Application Note Programming FLASH Array
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following code segment adheres recommended procedure programming FLASH array. flowchart Figure outlines this same procedure. general idea programming latches, write desired byte/word location array, apply programming voltage FLASH module within chip setting ENPE bit), then make sure location programmed properly. data correct, then number times programming voltage applied this byte programmed will have been preserved variable. programming voltage then pulsed that many times again ensure that byte/word remains programmed. This percent programming margin. This whole process repeated each byte/word programmed. next code segment simply copies string characters from stores beginning FLASH array. source code this application note available Motorola's site http://www.motorola.com/sps.
NOTE:
following code, STEP comments refer steps shown beginning this section. Some steps code correspond directly programming algorithm, included simply provide output indicator LEDs show user status program.
;-;-Application Note Source Code AN1836 -;-Erasing Programming FLASH -;-EEPROM MC68HC912B32 -;-;- FLASH EEPROM program routine MC68HC912B32 1.5T FLASH Module -;-;- Rev. February 2000 -;-Created Name Labels easier reading-;-Streamlined Code efficiency Rev. April 23,1998 -;-Fixed Tppulse 25us Tvprog 10us Written November 1997 -;-;-ASSEMBLER: IASM12 3.06 -;-P Microcomputer Systems-;-;- Matt Ruff, BE/OS Systems Engineering -;-;- This code intended instructional only. Motorola assumes liability modification this code. responsibility user verify parameters, variables, timings, etc.
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Freescale Semiconductor, Inc. Application Note
;-$BASE ;Set assembler default base base -;FLASH Start address ;FLASH address ;Num words number bytes divided pulses maximum ;FLASH Lock Control Register ;FLASH Module Configuration Register ;FLASH Control Register ;Lock register FEELCK ;Boot Protect FEEMCR ;Status Voltage FEECTL ;Erase Control FEECTL ;Programming Latch Control FEECTL ;Enable Program/Erase Voltage FEECTL ;Port data register ;Port data direction register
;-Equates FEEStart: $8000 FEEEnd: $FFFF FEESize: $8000 FEEWords: {FEESize/2} MaxNpp: FEELCK: FEEMCR: FEECTL: LOCK: BOOTP: SVFP: ERAS: LAT: ENPE: PORTA: DDRA: PA0on: PA1on: Mult: EClock: mS1LoopTime: mS1Delay: $0000 $0002 1000 {Mult*8000}
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;Multiplier EClock, assembler won't values over 2^16 ;E-clock frequency
;Num clock cycles loop. surround expression w/{()} P&E. ;Factor 1000 used base time ;-Equates -ORG Start: BRCLR Loop: Step MOVB LDAB Step STAB Step STEP4: FEEStart,X ;Write data address #LAT,FEECTL DATA,X ;Set FEECTL MarginFlag ;Clear number pulses ;Clear MarginFlag #$B00 ;(Turn your power supply board) FEECTL,$08,Error;If present, output error #$0000 $0800 ;Number programming pulses applied ;Programming margin flag $80A
Npp: MarginFlag:
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Application Note Programming FLASH Array
BSET Step Step BCLR Step YesFlag: Step
FEECTL,ENPE dly_22us FEECTL,ENPE dly_10us MarginFlag NoFlag STEP4 FEEStart,X DATA,X Error FEECTL,LAT #$00 Loop Done FEEStart,X DATA,X SetMarginFlag #MAXNpp STEP4 Error MarginFlag STEP4 PORTA #$FF,DDRA #PA1on,PORTA
;Apply programming voltage (Set ENPE) ;Delay time prog pulse (Tppulse) ;Remove programming voltage (Clear ENPE) ;Delay high voltage turn (Tvprog) MarginFlag set?? not, bump counter check data ;Decrement Npp=0? not, Step ;Read FEEPROM location verify programming same byte programmed? ;Programming failed, output error ;Clear FEECTL ;Check delimiter character not, back start! quit. ;Increment number prog pulses applied ;Read FEEPROM location verify programming same byte programmed? margin flag ;Have applied number pulses? not, continue programming have problem ;Set MarginFlag
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LDAA CMPA Step BCLR CMPA NoFlag: LDAA CMPA LDAB CMPB SetMarginFlag: Done: MOVB MOVB
;Clear Port ;Set DDRA outputs ;Turn indicate complete ;(Turn supply programming complete)
;-;-Error Subroutine -;-Error: PORTA ;Clear Port MOVB #$FF,DDRA ;Set DDRA outputs Blink: MOVB #PA0on,PORTA ;Turn error output dly_500ms ;Delay blinking visible (1/2 second between flashes) MOVB #$00,PORTA ;Turn dly_500ms Blink ;Repeat nauseam.
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;-;-Delay Subroutines -;-dly_500ms: #500 ;Delay DelaymS ;-;-Millisecond Delay Routine -;-;-Call with number delay accumulator. -;-The delay exact, close enough when delaying -;-DelaymS: DlyLoop1mS: #mS1Delay ;Load delay count into DlyLoop: ;Decrement count DBNE X,DlyLoop ;Loop until done. DBNE D,DlyLoop1mS ;-;-Microsecond Delay Routines (8MHz clock) -;-;- reduce loop overhead, following routines have been optimized counting cycle time calculating delay based 8MHz system clock. -;-dly_22us: Delay about 22-23us cycles Total delay {4+2+(loopcount*3)+5}*125ns loopcount yields 20.875us cycles-
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d_22u: DBNE dly_10us:
D,d_22u
cycles; cycles; Delay about 10us cycles Total delay {4+2+(loopcount*3)+5}*125ns loopcount yields 10.375us cycles-
d_10u: DBNE DATA
D,d_10u
cycles; cycles-
"Motorola Microcontrollers"
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Application Note Erasing FLASH Array
Erasing FLASH Array
This sequence demonstrates recommended procedure erasing FLASH EEPROM. voltage must proper level prior executing step first time. Turn VFP. Apply program/erase voltage pin. ERAS configure FLASH EEPROM erasing.
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Write valid address FLASH array. This allows erase voltage turned data written address written important. boot block will erased only control BOOTP negated. Apply erase voltage setting ENPE. Delay single erase pulse, tEPULSE. Remove erase voltage clearing ENPE. Delay while high voltage turning off, tVERASE. Read entire array ensure that FLASH EEPROM erased. FLASH EEPROM locations erased, repeat steps through until either remaining locations erased until maximum erase pulses have been applied, nEP. FLASH EEPROM locations erased, repeat same number pulses required erase array. This provides percent erase margin. Read entire array ensure that FLASH EEPROM erased. Clear LAT. Turn VFP. Reduce voltage VDD. flowchart Figure demonstrates recommended erase sequence.
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START ERASE TURN CLEAR MARGIN FLAG CLEAR ERASE PULSE COUNTER (nEP)
ERAS
WRITE ARRAY
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ENPE DELAY DURATION ERASE PULSE (tEPULSE) CLEAR ENPE DELAY BEFORE VERIFY (tVERASE) MARGIN FLAG SET? DECREMENT COUNTER ARRAY ERASED? ARRAY ERASED? CLEAR INCREMENT COUNTER READ ARRAY MARGIN FLAG
TURN
ARRAY ERASED
ARRAY FAILED ERASE
Figure Erasing Sequence Flowchart
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Application Note Erasing FLASH Array
This code segment follows recommended procedure erasing FLASH array. flowchart Figure outlines this same procedure. general idea erase flag, write location array, apply erase voltage FLASH module within chip setting ENPE bit), then make sure entire array erased. whole array erased, then number times erase voltage applied this erasure will have been preserved variable. erase voltage then pulsed that many times again ensure that array remains erased. This percent erase margin.
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source code this application note available Motorola's site http://www.motorola.com/sps.
NOTE:
following code, STEP comments refer steps shown beginning this section. Some steps code correspond directly erasing algorithm included simply provide output indicator LEDs show user status program.
;-;-Application Note Source Code AN1836 -;-Erasing Programming FLASH -;-EEPROM MC68HC912B32 -;-;- FLASH EEPROM erase routine MC68HC912B32 1.5T FLASH Module -;-;- Rev. February 2000 -;-Fixed ReadArray routine -;-Created Name Labels easier reading -;-Streamlined Code efficiency Rev. January 2000 -;-Changed 10ms delay tepulse -;-to match specification change Rev. April 1998 -;-Changed 100ms delay tepulse Written November 1997 -;-;-ASSEMBLER: IASM12 3.06 -;-P Microcomputer Systems -;-;- Matt Ruff, BE/OS Systems Engineering -;-;- This code intended instructional only. Motorola assumes liability modification this code. responsibility user verify parameters, variables, timings, etc. -;-;-
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$BASE
;Set assembler default base base -;FLASH Start address ;FLASH address
;-Equates FEEStart: $8000 FEEEnd: $FFFF FEESize: $8000 FEEWords: {FEESize/2} BootBlkSize: BCFEEWords: MaxNep: FEELCK: FEEMCR: FEECTL: LOCK: BOOTP: SVFP: ERAS: LAT: ENPE: PORTA: DDRA: Mult: EClock: mS1LoopTime: mS1Delay:
;Num words number bytes divided 2048 ;Size boot block {(FEESize-BootBlkSize)/2};Num words blank check {()}for P&E. pulses maximum ;FLASH Lock Control Register ;FLASH Module Configuration Register ;FLASH Control Register ;Lock register FEELCK ;Boot Protect FEEMCR ;Status Voltage FEECTL ;Erase Control FEECTL ;Programming Latch Control FEECTL ;Enable Program/Erase Voltage FEECTL ;Port data register ;Port data direction register ;Multiplier EClock, assembler won't values over 2^16 ;E-clock frequency
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$0000 $0002 1000 {Mult*8000}
;Num clock cycles loop. surround expression w/{()} P&E. ;Factor 1000 used base time ;-Equates -ORG Start: BRCLR Step MOVB Step Step STEP4: BSET FEECTL,ENPE ;Apply erase voltage (Set ENPE) FEEStart,X ;Write some data valid FLASH address #ERAS|LAT,FEECTL ;Set ERAS FEECTL bitwise #$B00 ;(Turn supply board now) #$0000 ;Clear number pulses MarginFlag ;Clear margin flag ErasedFlag ;Clear erased flag FEECTL,SVFP,Error present, output error $0900 ;Number programming pulses applied ;Programming margin flag ;Array Erased Flag $90A
Nep: MarginFlag: ErasedFlag:
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Application Note Erasing FLASH Array
Step Step BCLR Step YesFlag: Step BCLR NoFlag: LDAB CMPB SetMarginFlag: Done: MOVB MOVB PORTA #$FF,DDRA #$02,PORTA ;Clear Port ;Set DDRA outputs ;Turn indicate complete ;(Turn board now) MarginFlag STEP4 ;Set Margin Flag ReadArray ErasedFlag SetMarginFlag #MaxNep STEP4 Error ;Increment number erase pulses applied ;Verify entire array erased erased? (TST sets ErasedFlag margin flag (BNE branches ErasedFlag ;Have applied number pulses? not, continue erasing have problem FEECTL,ERAS|LAT Done ;Clear ERAS FEECTL quit. STEP4 ReadArray ErasedFlag Error ;Decrement mod. coming branch Step ;Verify entire array erased array erased? (TST sets ErasedFlag not, Erase failed, output error (BEQ branches ErasedFlag dly_10ms MarginFlag NoFlag ;Delay high voltage turn (Tverase) margin flag set?? (TST sets MarginFlag not, bump counter check data (BEQ branches MarginFlag FEECTL,ENPE ;Remove erase voltage (Clear ENPE) dly_10ms ;Delay time erase pulse (Tepulse)
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;-;-Read Verify Erase subroutine -;-ReadArray: ErasedFlag Always start with clear flag. #BCFEEWords words check FLASH. boot block check) #FEEStart Index start FLASH. #$FFFF Erased word value comparison. CheckLoop: 2,X+ word erased? VerifyBad not, return without setting ErasedFlag. (failure)
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DBNE VerifyBad: ;-;-Error Subroutine -;-Error: PORTA ;Clear Port MOVB #$FF,DDRA ;Set DDRA outputs Blink: MOVB #$01,PORTA ;Turn error output dly_500ms ;Delay blinking visible (1/2 second between flashes) MOVB #$00,PORTA ;Turn dly_500ms Blink ;Repeat nauseam. ;-;-Delay Subroutines -;-dly_500ms: #500 ;Delay 500ms DelaymS dly_10ms: ;Delay 10ms DelaymS ;-;-Millisecond Delay Routine -;-;-Call with number delay accumulator. -;-The delay exact, close enough when delaying -;-DelaymS: DlyLoop1mS: #mS1Delay ;Load delay count into DlyLoop: ;Decrement count DBNE X,DlyLoop ;Loop until done. DBNE D,DlyLoop1mS Y,CheckLoop ErasedFlag Yes, word count, done check next word. words checked erased. ErasedFlag.
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Application Note Programming Voltage Supply Considerations
Programming Voltage Supply Considerations
Programming Voltage Supply Envelope
preventing damage FLASH array corruption data contained memory programming voltage envelope shown Figure Many problems that customers experience with FLASH devices failure ensure that their voltage sources always meet these requirements. most important single thing remember from this diagram that should always same level, except during actual program erase cycle. Corruption FLASH data often encountered when allowed exceed during power-up power-down phases. Conversely, allowed fall below volts lower than time, damage FLASH array occur.
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13.5 12.6 11.4
MAXIMUM ENVELOPE ENVELOPE COMBINED
4.15
-0.30 POWER NORMAL READ PROGRAM ERASE POWER DOWN
Figure Programming Voltage Envelope
NOTE:
Although Figure shows lower boundary 4.15 volts during normal read phase, always must more than volts below VDD. example, operating voltage system volts, lower than 4.85 volts.
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Example Protection Circuitry Figure shows example circuit which, properly implemented, maintain appropriate voltage levels pin. This section outlines design this circuit, what each component intended some design considerations when designing protection.
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Figure Supply Circuit general idea this circuit implementation supply from dc-dc converter. This dc-dc converter, like most, provides shutdown feature which allows converter's output shut off. When SHDN converter pulled high, 10-k pullup resistor (R1) does, output VOut shorted supply. This requires that programming erasing routines assert port turn converter supply 12-volt programming voltage during programming erasing cycle. Simple programming erasing routines, such those shown earlier this application note, will longer suffice. implementing this solution, tied power-up power-down, ensuring that they rise fall together. Capacitors normal decoupling capacitors supply lines. used reduce electromagnetic interference (EMI) circuit. large, will allowed fall with VDD, potentially causing data
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Application Note Programming Voltage Supply Considerations
corruption FLASH array. (Refer Figure 11.) where dc-dc converter stores charge supply VOut target device. supply must able source approximately current least (based programming cycle requirements) current least (based erase cycle requirements). certain degree experimentation might required when selecting When trying different capacitor values, always monitor effects decay during power-down current supplied pin.
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must larger than make certain that SHDN dc-dc converter never allowed fall below unless output microcontroller driven low. external pullup ensures this behavior, matter what port used microcontroller what internal structure that looks like. Without strong enough pullup resistor voltage SHDN might drop during reset event, causing dc-dc converter activate begin driving voltage VOut begin rise volts. This would result data corruption FLASH.
NOTE:
Figure different from recommended circuit shown information about ST662A from Microelectronics, correct. change location capacitor which placed between VFP. This change implemented with cooperation Microelectronics tracking rapidly falling voltage level, such Figure Figure This circuit also been verified with Maxim Integrated Products device (MAX662).
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Freescale Semiconductor, Inc. Application Note
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Figure Exceeding during Power-Down certain that decays with VDD, shown Figure capacitance values tested. rate decay supply powering down will help define large capacitance made.
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Application Note Programming Voltage Supply Considerations
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Figure Tracking during Power-Down When checking ensure that reservoir capacitance value low, voltage level monitored during initial erase write pulse. Remember that largest current draw erasing when bits FLASH programmed Conversely, highest programming current seen when programming bits from erased state user should look this oscilloscope, brevity pulses. Using port SHDN signal useful trigger scope when pulses fired. voltage dips below 11.4 volts, capacitance used increased, sure verify that decay rates still same. declining with each successive pulse, inserting some delays between each pulse allow charge pump recharge.
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Freescale Semiconductor, Inc. Application Note
solution shown this application note uses ST662A dc-dc converter, similar device will work. Some other options LTC1262C from Linear Technology Corporation MAX662 from Maxim Integrated Products, Inc.
Alternative Circuitry
Another option placing dc-dc converter application board in-circuit reprogramming supply from outside target system. This achieved using something similar circuit shown Figure This solution requires that (background debug mode) connections made target board allow connection BDM-compliant debug tool, well supply. Again, long envelope rules adhered this circuit will work well. Also, bear mind that voltage regulator must able accept current which will flow upward through during program erase cycle, preventing from being injected back into microcontroller.
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Application Note Other FLASH Hardware Device Considerations
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Figure Supplied from External Source through Interface
NOTE:
diode shown Figure must have forward bias drop greater than volts maintain proper voltage relationship times. Diodes such 1N5818 1N5819 will work typically have even lower voltage drops current.
Other FLASH Hardware Device Considerations
Some hardware facts details worth mentioning here. instance, M68HC12 Family uses 1.5T FLASH technology. more detailed description this other technologies, refer application note Non-Volatile Memory Technology Overview, Motorola document order number AN1837/D. Without getting into level detail provided that document, practical side some hardware considerations included here. Topics
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Freescale Semiconductor, Inc. Application Note
covered lifetime FLASH memory itself effects usage FLASH array. Also important discuss failure mechanisms involved when acceptable ranges testing marginally programmed memories.
FLASH Lifetime
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main purpose long-term storage programs data. result, prime concern application designer know long that information will stored correctly. Motorola guarantees FLASH data retention lifetime years properly programmed data, based average operating temperature 70oC. Since FLASH EEPROM also electrically erasable, ideally suited in-circuit updating rapid code modifications. memory does, however, have finite number program erase cycles through before fails. Motorola guarantees program/erase cycles MC68HC912B32 device, which based 125°C.
Effects FLASH Array
FLASH memory's bitcells written erased over many cycles, they tend "age." primary effect that over time, gradually, more more erase programming pulses required erase program bitcell. This been taken into account algorithms programming erasing. algorithms ensure that only fewest number pulses required applied device. device ages, number pulses required will continue rise until exceeds specified limit electrical characteristics part. Once this happened, part longer able modified within specifications. Eventually, memory continually written erased, some bitcells will become completely saturated unable modified regardless number pulses applied them.
Possible Failure Mechanisms
already been discussed, preventing data disturbance damage FLASH array ultimate concern. improperly managed, either corruption data damage likely occur. brief mention should made some consequences improperly controlled voltage sources. instance, allowed
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Application Note Other FLASH Hardware Device Considerations
fall more than volts below time, lead pad-driven latchup conditions even damage input pad. This could result improper programming, reduced current capability pin, other types damage pin. Also important remember that during power-up power-down, when below volts, logic could potentially unknown state, might cause voltage applied array inadvertently, causing data disturbance FLASH array.
Freescale Semiconductor, Inc.
Testing Marginally Programmed FLASH
Some customers return devices claiming defective memory cells, since .s19 files won't verify because bits that don't seem programmed that seem change state after good deal time passed after programming. Generally, these returns caused inadequately programmed FLASH cells. This improper programming routines which meet requirements Motorola's programming algorithm inadequate programming voltage power supplies. However, programming algorithms power supply requirements outlined this application note adhered marginal programming should concern. Marginally programmed devices would, their very nature, tend allow bitcells change state over time, since only enough charge transferred allow cell read properly immediately after programming. these flipping symptoms experienced, there methods help determine devices being adequately programmed. there reason believe that some devices might marginally programmed, simple test determine whether FLASH strongly marginally programmed. method exact, effective detecting marginally programmed parts, relative strongly programmed ones. Most importantly, this test should used help identify insufficient programming voltage supply designs. Contact salesperson field applications engineering representative determine these testing methods appropriate your situation.
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Freescale Semiconductor, Inc. Application Note
vital success these tests that devices question properly handled before testing performed. devices should serialized this data linked with each device: supply which used with that device Schematics supply design, on-board supply used Source code used program erase that device
Freescale Semiconductor, Inc.
Also, several control devices should supplied comparison purposes, testing relative testing measure. supply question, might case charge pump were used design might incapable supplying adequate current, control devices will need identical programming erasing code bench power supply with large current sourcing capacity. FLASH modifying code question, necessary customer verify that code follows Motorola's recommended programming erasing algorithms which were covered this document. Once these things have been done, contact salesperson field applications engineering representative determine proceed with this type analysis. information gathered bullet list here needed analyze results testing marginal programming.
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Application Note Conclusion
Conclusion
This application note gives overview basics erasing programming FLASH array MC68HC912B32 microcontroller. Knowing these basics, easy progress writing bootloader, designing field programming unit, other application which needs manipulate FLASH memory. addition programming erasing algorithms, this document covers many hardware concerns relating programming voltage supply preventing data corruption damage FLASH memory. Several examples supply management have been given reference properly control programming power supplies while programming M68HC12 Family related devices. example serial bootloader this microcontroller, refer Serial Bootloader Reprogramming MC68HC912B32 FLASH EEPROM, Motorola document order number AN1718/D.
Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc. Application Note
Freescale Semiconductor, Inc.
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
reach USA/EUROPE/Locations Listed: Motorola Literature Distribution, P.O. 5405, Denver, Colorado 80217, 1-303-675-2140 1-800-441-2447. Customer Focus Center, 1-800-521-6274 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku, Tokyo, 106-8573 Japan. 81-3-3440-8573 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, King Street, Industrial Estate, N.T., Hong Kong. 852-26668334 MfaxTM, Motorola Back System: RMFAX0@email.sps.mot.com; http://sps.motorola.com/mfax/; TOUCHTONE, 1-602-244-6609; Canada ONLY, 1-800-774-1848 HOME PAGE: http://motorola.com/sps/ Mfax trademark Motorola, Inc.
Motorola, Inc., 2000
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