AN1831 Using MC68HC908 On-Chip FLASH Programming Routines Fr

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AN1831
Using MC68HC908 On-Chip FLASH Programming Routines
Freescale Semiconductor, Inc.
ROM-Resident Routines MC68HC908GR8, MC68HC908KX8, MC68HC908JL3, MC68HC908JK3, MC68HC908JB8
Grant Whitacre Applications Engineering Austin, Texas
Introduction
This application note describes routines that stored (read-only memory) MC68HC908GR8, MC68HC908KX8, MC68HC908JL3/JK3, MC68HC908JB8 microcontrollers (MCU). These routines used program, erase, verify FLASH memory accessed either user mode monitor mode(1). There additional routines MC68HC908KX8 trim internal clock generator, which also described herein. This document describes method calling each routines collection specifies what performed returned confirmation routine execution. illustrate these routines used practice, program included, which configured these devices program FLASH either user mode monitor mode.
These routines accessible both user mode monitor mode listed devices except MC68HC908GR8. This device allows access these routines monitor mode only.
Motorola, Inc., 2001
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Application Note
addition, host program, downloadable from Motorola site, been developed provide interface download this program device program FLASH.
FLASH Overview
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routines described here have been incorporated into these particular devices, which have enough allow this functionality routine. type FLASH which these routines applicable called "split gate" FLASH because type technology used, TSMC FLASH after fabrication plant, FLASH after company originally designed Split gate FLASH significant advantages. Some these advantages are: Faster programming time. takes program each byte, which translates little more than quarter second programming time program entire 8-Kbyte array. Better endurance. This type FLASH specified withstand least 10,000 program/erase cycles. Older technologies provided only about program/erase cycles. Simpler programming algorithm. programming algorithm split gate FLASH simple process turning high voltage, applying programmed, writing values each byte programmed turn. This differs from past technology which required iterative process turning high voltage applying page, writing values each byte page, checking bytes valid values "margin" read condition, then repeating program/verify process until bytes verified correctly.
Split gate FLASH programmed generally basis erased page basis. Also, entire array mass erased. page always contains rows, size page vary from device another. typical page size bytes. Before reprogramming byte that currently programmed with
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Application Note Routines
different value, entire page must erased reprogrammed. Refer applicable data manual proper program erase procedure this FLASH.
Routines
collection consists five callable(2) routines each described Table These routines explained briefly here, parameters passing method addressed later sections.
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GETBYTE
GETBYTE routine that receives byte monitor mode communication port defined that particular device, this received value passed back calling routine accumulator. these devices, communication port either port port Check Table constant definition COMMPORT port used each device. This routine expects same non-return-to-zero (NRZ) communication protocol baud rate that used monitor mode(3). difference between this routine's method receiving byte when monitor receives byte that monitor echoes back whatever received. more efficient program this routine when receiving data from host, eliminate time overhead sending every byte that received. This especially true host program routine already have built-in error detection scheme, such message checksum, there might need echo check each byte sent.
These routines accessible both user mode monitor mode listed devices except MC68HC908GR8. This device allows access these routines monitor mode only. baud rate will fOP/256 MC68HC908JB8. this device, rate this routine well monitor mode send/receive routines have been changed accommodate "standard" this device considering part. rate MC68HC908JB8 fOP/208.
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Application Note
RDVRRNG RDVRRNG routine serves purposes: used read range FLASH locations. used verify range FLASH locations with data contained data array RAM.
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Actually, both functions performed each time routine called, data specified FLASH range returned. degree flexibility with this routine that specify where data returned. accumulator when entering RDVRRNG, then data read will sent monitor mode communication port. accumulator non-zero, then data placed data array, replacing existing contents. beginning range read and/or verified specified parameters this routine. carry condition code register data specified range verified successfully against data data array. more added function this routine that does checksum data returned. This checksum, which bytes entire data collection, stored accumulator upon return from function.
PRGRNGE
PRGRNGE used program range FLASH locations with data loaded into data array. with RDVRRNG, start location range addresses programmed passed parameter. check that bytes specified range erased performed this routine prior programming. does this routine verification after programming, there return confirmation that programming successful. should noted that PRGRNGE returns with first-address variable, FADDR, address next byte after range just programmed. last-address variable LADDR changed. Also, since this routine calls delay routine DELNUS, parameter passing requirements that routine must when calling PRGRNGE. Another point worth noting that this routine allows range passed That range does have coincident with boundaries. range specified beginning row, middle row, row, range overlapping
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Application Note Routines
boundaries. only things that user must assure that range specified first erased that whatever specified range, data range must data array RAM.
NOTE:
This routine used conjunction with RDVRRNG perform complete program verification cycle specified range.
ERARNGE
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ERARNGE called erase range locations FLASH. This routine does last address (LADDR) variable. first address (FADDR) placed previous routines actually address range erased. There only sizes erase ranges: page entire array. Therefore, this routine needs told what type erase desired. This done setting called mass control variable called CTRLBYT. This explained more detail later Variables. Using ERARNGE erase page MC68HC908GR8, MC68HC908KX8, MC68HC908KX2 causes erase vector page when called erase another page FLASH. This behavior side effect servicing computer operating properly (COP) during this routine's necessary delay millisecond. workarounds this behavior are: block protection that least vector page protected from erase inadvertent reprogramming. Then page erases, other than attempt erase vector page, will result intended page being erased, vector page will remain intact. Accept erase vector page first buffering data this page then, after intended page erased along with vector page, reprogram vector page with buffered data. this erase routine ROM. Write your erase routine keep FLASH. Whenever page erase desired, copy routine execute erase from there. sure omit instructions that service COP.
CAUTION:
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Application Note
DELNUS last routine delay routine used support PRGRNGE ERARNGE routines. can, however, called independently. DELNUS takes parameters signifying operating frequency passed accumulator other, single byte value passed register, specifying length delay. Neither these parameters passed absolute value. operating frequency variable value four times that actually used, this value allowable lower limit four representing 1-MHz operation. delay value passed represents number microsecond increments delay. Therefore, resolution delay microseconds. minimum delay course, microseconds maximum delay this routine little more than milliseconds (255 µs). precision delay very high considering that normalized frequency operation which specified within 0.25 MHz. worst precision occurs short delays relatively slow operating frequencies, where both values passed midway between possible values(4). When delay routine called PRGRNGE ERARNGE (the only routines this collection which call delay routine), calling routine loads register with value delay needed. frequency parameter loaded into accumulator reading variable CPUSPD. This variable, therefore, must pre-loaded routine calling PRGRNGE ERARNGE.
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example this worst-case error would 1.125 desired delay these conditions, value frequency parameter could either signifying 1.00 1.25 MHz, respectively. delay value passed could either signifying delay, respectively. case like this, choose lower value parameter upper value other parameter minimize error delay.
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Application Note Routines
Table FLASH Routines
Routine Name Routine Description GETBYTE Gets byte data from comm port Comm port configured input RDVRRNG Reads and/or verifies range locations contains first address range; LADDR contains last address read; tested read data goes comm port (Acc $00) DATA;DATA contains data against which compare read data good compare; contains checksum; DATA contain read FLASH data PRGRNGE Programs range* locations contains first address range; LADDR contains last address programmed; DATA contains data used during programming; CPUSPD contains ERARNGE Erases** page entire range contains address range erased; range size specified control byte; CPUSPD contains DELNUS Delays contains time delay µs); contains times
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Entry Conditions
Exit Conditions
loaded with byte received
contains next address after range just programmed
Preserves contents (address passed)
Subroutines Called Variables Read Variables Modified Stack Used
Get_Bit LADDR, DATA ARRAY
DELNUS CONTROL BYTE, LADDR, DATA ARRAY, CPUSPD
DELNUS Control Byte, CPUSPD
DATA ARRAY bytes bytes bytes bytes bytes
*Allows programming range addresses, which does have boundary, either beginning end. example, programming $F001 $F008 valid. Does check blank range before erase necessary) after successful erase)
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Application Note Defined Constants
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Table lists various constants defined these routines. FLCR address relate delays used during programming erasing. constants ending values passed delay routine. mentioned previously, delay routine takes parameter which represents number microsecond increments delay time. Therefore, program time, TPROG, which specified time between microseconds, duration here times TPROGQ, microseconds. Page erase mass erase delays done same way, except that routines called ECALLS MECALLS times, respectively. Therefore, mass erase delay, which specified 4000 microseconds, actually delays each with duration microseconds, which results total mass erase delay 4080 microseconds (MECALLS TMERASEQ microseconds). Table Constants Used Routines
Constant Name FLCR TPROGQ TERASEQ TMERASEQ TNVSQ TPGSQ TNVHQ TNVHLQ TRCVQ ECALLS MECALLS Description FLASH control register address Program time Erase time Mass erase time HVEN setup time Program hold time hold time hold time (mass erase) Return read time Calls delay page erase Calls delay mass erase Value $FE08
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Application Note Variables
Because differences some constants used each device, following constants need specific particular device. Table shows constant values each device. Since these values device-specific, they have been included source code Routines Source Code. Table Device-Specific Values Constants
Constant Name Description Start address Size programming Communication port monitor mode FLASH block protect register address Address routine then output byte comm port (monitor code) Address routine output byte communication port (monitor code) Address routine communication port (monitor code) MC68HC 908GR8 PTA0 $FF7E MC68HC 908KX8 PTA0 $FF7E MC68HC 908JL3/JK3 PTB0 $FE09 MC68HC 908JB8 PTA0 $FE09
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ROWSIZ COMMPORT FLBPR
Get_Put
$FE99
$FE97
$FEBD
$FEC0
Put_Byte
$FEAE
$FEAA
$FED0
$FED5
Get_Bit
$FED2
$FECE
$FF00
$FF00
Variables
Table shows variables used routines. These variables either passed register static variables predefined location RAM. FADDR 2-byte value that represents first address range which operated. passed registers when call made routines. first address range
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Application Note
valid FLASH address does have page boundary. LADDR last address range passed first byte data structure RAM. This data structure very simple, consisting last address, speed variable, control byte, data array. discussed detail Data Structure. last address, like first address, valid FLASH address restricted being last byte page row.
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internal operating frequency device which FLASH operation performed passed variable called CPUSPD. 1-byte value which passed data structure should given rounded product four times actual internal operating frequency, such that 2.4576 MHz, then value passed should decimal $0A. This variable used normalize length delays with respect operating frequency, passing value four times actual frequency provides better resolution. remaining operating parameter used these routines single value control byte. This called mass when calling ERARNGE perform mass erase. ERARNGE called with intention performing page erase, then mass must cleared. other bits CTRLBYT used user's discretion other flags. Table Variables Used Routines
Variable Name FADDR LADDR CPUSPD CTRLBYT DATA Description First address range locations Last address range locations Mass (bit Data array Size bytes bytes byte byte Variable Location/Passing Method Data structure Data structure Data structure Data structure
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Application Note Data Structure
Data Structure
data structure collection static variables used execution three main routines PRGRNGE, ERARNGE, RDVRRNGE. data structure same relative location content same data order devices containing these routines. structure always starts ninth byte order variables shown Table
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Table Data Structure Location Content
Location Variable Name CTRLBYT CPUSPD LADDR Size (Bytes) Description Includes mass flag speed passed Last address read range program range Variable number bytes passed data programming verifying block
DATA
Variable
Note that data array DATA variable length. This done support variable number locations which perform programming, reading, verifying actions. Most time, these actions will performed data time, although that need case. Some these devices have rather small array, size data array must limited size minus stack needed size routine being executed. routine kept reasonable size, then there should problem defining data array size devices this collection.
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Application Note Addresses Routines
address call each five routines varies among devices. Table gives absolute address that should used when calling routines. Table Addresses Routines
Routine
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MC6868HC 908GR8 $1C99 $1CAD $1DA0 $1CEC $1D96
MC68HC 908KX8 $1000 $1003 $1006 $1009 $100C
MC68HC 908JL3/JK3 $FC00 $FC03 $FC06 $FC09 $FC0C
MC68HC 908JB8 $FC00 $FC03 $FC06 $FC09 $FC0C
GETBYTE RDVRRNG ERARNGE PRGRNGE DELNUS
MC68HC908KX8 Trim Routine
MC68HC908KX8 contains additional routines ROM, which have been included support trimming internal clock generator (ICG) module. ICGTRIM located $1330 MC68HC908KX8 called trim measuring pulse width break signal received port port baud rate used break signal must equal internal frequency device divided 256. Communication must conformance with normal monitor mode communication, that non-return-to-zero (NRZ) format. break signal defined consecutive bits, pulse width this signal nominally 1.04 milliseconds 9600 baud. This signal must within percent nominal value routine will attempt trim ICG. Table specifies relationship between internal frequency, baud rate, pulse width break signal.
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Application Note MC68HC908KX8 Trim Routine
Table Frequency, Baud Rate, Break Pulse Width
(MHz) 1.2288 2.4576 3.6864 4.9152 Baud Rate (bps) 4800 9600 14400 19200 28800 Break Pulse Width (ms) Minimum 1.5623 0.781 0.365 0.195 0.098 Nominal 2.083 1.042 0.521 0.260 0.130 Maximum 2.604 1.302 0.651 0.325 0.163
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7.3728
This routine checks many cycles measured during break signal bits) sent fOP/256 baud host adjusts trim register. break signal more than percent variation from what expected (0.78-1.30 9600), then trimming will performed. This accuracy limit consistent with extent ICG's ability fine tune trim register. main timing loop this routine begins leading edge break signal lasts until sees trailing edge. break signal lasts times. Since communicating bps, then duration times 2560 cycles. Each time through loop cycles, expected execute loop times MC68HC908KX8 sync serially with host. loop executed more than loop cycles, then MC68HC908KX8 must running faster than expected needs slowed down. loop executed less than loop cycles, then MC68HC908KX8 must running slower than expected needs speeded amount that speed changed equal number loop cycles over under 256. loop traversed times, then running (256 240) 6.25 percent fast. Each incremental change that made trim register (ICGTR) will result 0.195 percent change internal clock. That incrementing register over default value stored there will decrease internal clock 0.195 percent. Each execution loop over under what expected (256 times) represents error 1/256 0.391 percent error. number loop cycles
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Application Note
doubled this number used correct trim register. precision trimming therefore 0.391 percent. Another routine that unique MC68HC908KX8 called ICGTEST. This routine simply toggles port pin, port rate that 1/16th operating frequency. This allows verification that trimmed accurately. ICGTEST located $1369.
Typical Routine Calls
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This section provides examples these routines called. following code makes call delay routine (DELNUS). Assume 7.37 MHz, value passed accumulator round (fOP ($1D). delay value loaded into passed through register. example, let's value, TMERASEQ, which desired delay time divided
DELAYCALL:
#$1D #TMERASEQ DELNUS
;fOP*4 ;delay time/12
next block code makes call routine RDVRRNG read verify range FLASH from $F000 $F010. accumulator cleared before calling routine, which signals routine that specified range sent communication port instead being copied into RAM. verify stage will performed automatically each byte FLASH range will compared corresponding byte data array RAM. That first byte range, $F000, will compared with first byte data array which located 13th byte definition. This process repeated bytes range comparisons equal, then carry condition code register will cleared upon return from RDVRRNG. Otherwise, will set. This code does show loading compare data into RAM.
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Application Note Typical Routine Calls
Before calling routine, high byte byte last address range placed 11th 12th locations RAM, respectively, register loaded with first address range.
RDCALL: CLRA LDHX STHX LDHX
#$F010 LADDR #$F000 RDVRRNG
;COMMPORT DEST. ;LAST ADDRESS STORED LADDR ;FIRST ADDRESS STORED
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next lines code perform erase FLASH. variable CPUSPD located 10th location value which reflects 8-MHz operating frequency, that ($20). Since calling erase routine, must specify what type erase want page erase mass erase. This example illustrates setup perform mass erase where mass bit, CTRLBYT ninth location must set. valid FLASH address loaded into when doing mass erase. case page erase, address within that page would acceptable.
MASSERASE: BSET6 LDHX
#$20,CPUSPD CTRLBYT #$F000 ERARNGE
;SET CLOCK VALUE ;SET MASS ERASE HERE ;LOAD FLASH ADDRESS
call GETBYTE receive byte data communication port, only thing that needs done ensure that communication port configured input. next code example assumes that port communication port.
RECEIVEBYTE: BCLR DDRA GETBYTE
;CLEAR DATA DIRECTION ;REGISTER INPUT PTA0
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Application Note
final examples show call trim routine resident MC68HC908KX8 ROM, then call test routine verify accuracy internal clock. call trim ICG, several things must done. First, make sure that enabled (ICGON trim register set) internal clock selected trim register cleared). Then accumulator select port which receive break signal. this example, port used communication port where break signal will received. select port accumulator must contain non-zero value. We'll also this port input here.
TRIMTHEICG: BCLR
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0,DDRA #$80,ICGTR #$08,ICGCR #$FF ICGTRIM
;SET PTA0 INPUT ;SET TRIM REGISTER MIDPOINT ;TURN SELECT CLOCK SOURCE ;ANY NON-ZERO VALUE SELECT PTA0 COMM
There setup required call next routine which allows monitoring fraction operating frequency. port used output 1/16th operating frequency, port output routine. Therefore, only call required. stop execution this routine, needs pulled low. External interrupts disabled CCR) generate inadvertent interrupt when this exit this routine.
TESTTHEICG:
ICGTEST
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Application Note Example Routine
Example Routine
This section describes program containing routine which could used either monitor mode user mode purpose programming these devices. monitor mode, routine could downloaded monitor commands user mode routine could copied from FLASH.
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Those readers have read In-Circuit Programming FLASH Memory MC68HC908GP20, Motorola document order number AN1770/D, will recognize content structure this program. Refer AN1770 complete description protocol used send programming commands data this routine. PC-based host program described that application note been expanded support programming these other devices available software library Motorola site http://motorola.com/mcu routine here much smaller than that required MC68HC908GP20 because makes calls routine rather than have these routines included routine. latter situation would practical small RAM-array devices such ones that include these routines. source code this program follows. user this routine must make sure that assembler directives properly based device mode used. This routine also differs from GPZO's that only supports monitor comm port communication both user monitor mode programming. Since available these devices, communication described here. This program could modified easily support user mode programming. This program does include support trimming MC68HC908KX8. routine monitor mode trimming FLASH-based routine user mode trimming could generated user. Note though that host program referred previously used send break signal automatic trimming.
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Application Note
FILE NAME: GKJJRR.ASM PURPOSE: Provides FLASH erase, program, verify program TARGET DEVICE: MC68HC908GR8, MC68HC908KX8, MC68HC908JL3/JK3 MC68HC908JB8 ASSEMBLER: mcuEZ VERSION: 1.0.5 PROGRAM DESCRIPTION: This program loads routine with instructions/data located FLASH memory that: Receives data over monitor comm. Port Calls routine program FLASH with received data Calls routine read/verify FLASH range Calls routine bulk erase device upon command program assembler directives able program each device both user monitor modes. monitor mode, generated S-record file will contain only routine. will have code that would reside RAM. user mode, load routines incorporated that could contained user's application. load routines load programming routines into from there looks just like routine executed monitor mode. AUTHOR: Grant Whitacre LOCATION: Austin, Texas UPDATE HISTORY: AUTHOR DATE DESCRIPTION CHANGE ============ ======== ===================== WHITACRE 11/02/98 INITIAL VERSION WHITACRE 01/19/99 MOD. WHITACRE 04/22/99 MOD. WHITACRE 11/18/99 MOD. JB8, GENERAL CODING NOTES: names labeled with <port name><bit number> used commands that operate individual bits, such BSET BCLR. name followed indicates label that will used form mask. ASSEMBLER DIRECTIVES (INCLUDES, BASE, MACROS, SETS, CONDITIONS, DEFS, ETC.) BASE ;DEFAULT BASE NUMBER DESIGNATION ;Remember: ACTIVE LOW!!!!!!!!!!!!!!! SET, (NECESSARY) ROUTINES WILL ;ADDRESSED INITIALLY;THIS VERSION ;WOULD USED RECORD FILE ;THAT DOWNLOADED INTO MONITOR ;MODE FLASH PROGRAMMING
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RAMPROG:
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Application Note Example Routine
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SELECT ONLY FOLLOWING! GR8: ;SELECTS TARGET DEVICE KX8: ;SELECTS TARGET DEVICE JB8: ;SELECTS TARGET DEVICE JL3: ;SELECTS TARGET DEVICE APPLICATION-SPECIFIC MEMORY EQUATES VALUE SPDSET, WHICH fOP*4, normalizes delay routines absolute time. SPDSET OPER. FREQ. CONFIG1 MASSBIT ;CTRLBYT MASS RAMPRSZ ;NOT EXCEED SIZE ROUTINE RAMPRG ;START ROUTINE PRGSTRT $F000 ;START FLASH PROGRAM XFRCODE PRGSTRT+RAMPRG RSTVLOC $FFFE ;RESET VECTOR LOCATION FLCR $FE08 ;FLASH CONTROL REGISTER IFEQ COMPORT GETBYTE RDVRRNG ERARNGE PRGRNGE DELNUS GET_PUT GET_BIT PUT_BYTE ROWSIZ FLBPR ENDIF IFEQ COMPORT GETBYTE RDVRRNG ERARNGE PRGRNGE DELNUS GET_PUT GET_BIT PUT_BYTE ROWSIZ FLBPR ENDIF
$1C99 $1CAD $1DA0 $1CEC $1D96 $FE99 $FED2 $FEAE $FF7E
$1000 GETBYTE+3 GETBYTE+6 GETBYTE+9 GETBYTE+12 $FE97 $FECE $FEAA $FF7E
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Application Note
IFEQ COMPORT GETBYTE RDVRRNG ERARNGE PRGRNGE DELNUS GET_PUT GET_BIT PUT_BYTE ROWSIZ FLBPR ENDIF IFEQ COMPORT GETBYTE RDVRRNG ERARNGE PRGRNGE DELNUS GET_PUT GET_BIT PUT_BYTE ROWSIZ FLBPR ENDIF DATSTRC tools
$FC00 GETBYTE+3 GETBYTE+6 GETBYTE+9 GETBYTE+12 $FEBD $FF00 $FED0 $FE09
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$FC00 GETBYTE+3 GETBYTE+6 GETBYTE+9 GETBYTE+12 $FEC0 $FF00 $FED5 $FE09
RAM+8
;Leave 8-bit offset from start
VARIABLE DEFINITIONS SPACE USAGE DOWNLOADED RTNS SIZE RAM+$07 RES. DEV. TOOLS( BYTES) RAM+$08 TRANSFER SIZE CTRLBYT BYTE) RAM+$09 FIRST ADDRESS CPUSPD (2/1 BYTE) RAM+$0A:RAM+$0BDATA SIZE LAST ADDRESS (1/2 BYTES) RAM+$0C:RAM+$0D DATA ARRAY DATA ARRAY BYTES) PROGRAM BYTES) $EC-$FF STACK BYTES) TOTAL(128 BYTES) TEMP2B TEMPH TEMPL DATSTRC CTRLBYT CPUSPD LADDR DATA ROWSIZ
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Application Note Example Routine
Program Algorithm (User Mode Programming) Initialize variables ports. Monitor COMM port input block data programmed start address. Load with data array bytes), start address length data array. Transfer following subroutines address RAMPRG LDDATA MAINPRG Jump first byte main program (RAMPRG). Execute program MAINPRG then return comm port monitoring loop RAM. Program Algorithm Monitor Mode Programming Monitor comm port input block data programmed start address. Load with data array bytes), start address length data array. Execute program MAINPRG then return PTA0/PTB0 monitoring loop RAM. START PROGRAM IFNE RAMPROG PRGSTRT COMPORT #$11,CONFIG1 ;DISABLE NAME: LDRAMPR PURPOSE: LOADS MAIN PROGRAM NEC. SUBROUTINES ENTRY CONDITIONS: NONE EXIT CONDITIONS: NONE SUBROUTINES CALLED: EXTERNAL VARIABLES USED: DESCRIPTION: EXECUTED FLASH LDRAMPR LDHX #RAMPRG ;STORE START LOCATION STHX TEMPH ;WHERE CODE TRANSFERRED LDHX #XFRCODE ;LOAD ADDR FLASH CODE NXTMOVE X+,TEMP2B ;TRANSFER LOCATION PSHH PSHX ;PUSH CURRENT FLASH ADDDR STACK LDHX TEMPH ;LOAD ADDRESSES THAT HOLD DEST. TEMP2B,X+ ;TRANSFER DATA FROM TRANSFER LOCATION NEXT STHX TEMPH CPHX #RAMPRG+RAMPRSZ NEXT LOCATION DESTINATION PULX ;POP CURRENT FLASH ADDR FROM STACK PULH NXTMOVE DONE, CONTINUE RAMPRG ELSE ENDIF RAMPRG ;START MONITOR PROGRAM WHICH ORG'D XFRCODE ;START CODE TRANSFERRED
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Application Note
NAME: LDDATA PURPOSE: LOAD WITH USER'S DATA START ADDRESS COMM PORT; PROGRAMS THEN DUMPS DATA THAT DOWNLOADED; ONLY DUMPS DATA SPECIFIED NUMBER BYTES PROGRAMMED (DATASIZ) ENTRY CONDITIONS: EXIT CONDITIONS: SUBROUTINES CALLED: PRGFLSH, DUMPROW EXTERNAL VARIABLES USED: DESCRIPTION: EXECUTED STRUCTURE DATA RECEIVED FOLLOWS: LOCATION DESCRIPTION LOC. ======== ======== COUNT TOTAL NUMBER RAM+$08 BYTES SENT (INCL. THAT BYTE) FIRST ADDRESS WHERE RAM+$09 thru RAM+$0A FOLLOWING DATA PROGRAMMED NUMBER BYTES PROGRAMMED RAM+$0B 5-68 ARRAY SPACE DATA PROGRAMMED RAM+$0C thru RAM+$4B COUNT USED THAT GREATER THAN (PROGRAM LENGTH THEN ROUTINE WILL HANG AFTER LAST PROGRAM BYTE SENT. CONTINUOUSLY LOOPS LOOKING DATA COMM PORT. MUST RESET AFTER LAST DOWNLOAD. DATA ARRAY RECEIVED WITH NUMBER BYTES PROGRAMMED THEN PROGRAM WILL CONSTRUE THIS SIGNAL ERASE ENTIRE ARRAY. THIS MOST CONVENIENT IMPLEMENT BULK ERASE WITHOUT HAVING HAVE COMMAND BYTE DATA STRUCTURE. TRANSFERRED PROGRAM SIZE =================== ============ =========== RAM+$08 TRANSFER SIZE CTRLBYT BYTE) RAM+$09 FIRST ADDRESS (MSB) CPUSPD BYTE) RAM+$0A FIRST ADDRESS (LSB) LAST ADDRESS (MSB) BYTE RAM+$0B DATA SIZE (DATASIZ) LAST ADDRESS (LSB) BYTE) RAM+$0C-RAM+$4B DATA ARRAY DATA ARRAY BYTES) LDDATA: CLRH #CTRLBYT ;POINT LOCATION TRANSFER SIZE WAITRX: GET_PUT ;CALL ROUTINE MONITOR CODE #CTRLBYT ;BAD START KEEP LOOPING NON-0 STORNOW TSTA WAITRX STORNOW ;STORE DATA INCX ;MOVE NEXT LOCATION DBNZ CTRLBYT,WAITRX ;DEC. PROG SIZE CNTR (1st BYTE) ENTIRE PROG LODED, CONT. CPARSE LDHX CPUSPD ;$89 STHX TEMP2B ;MAINTAIN FIRST BYTE TEMP2B #SPDSET,CPUSPD ;PUT SPEED SELECTED EQUATE INTO CPUSPD ADDR LADDR+1,TEMPH ;MAINTAIN DATASIZ TEMP
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Application Note Routines Source Code
STHX LDHX COMA JUSTPRG
#ROWSIZ-1 LADDR TEMP2B TEMPH DUMPROW ERASE1 #$FF FLBPR PRGRNGE DUMPROW MASSBIT,CTRLBYT ERARNGE TEMP2B RDVRRNG LDDATA
THIS BOTH DUMP PROGRAM SIZE DATA PROGRAMMED THEN BRANCH DUMP SIZE FFH, THEN BULK ERASE
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ERASE1
BSET
DUMPROW LDHX CLRA
IFNE RAMPROG INTERRUPT RESET VECTORS RSTVLOC RSTVEC PRGSTRT ENDIF
Routines Source Code
following five flowcharts provide graphic explanations routines source code.
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Application Note
GETBYTE
PURPOSE: BYTE DATA PTA0. ATTEMPTS RECEIVE BYTE FROM EXTERNAL CONTROLLER PORTA0. ONCE CALLED, PROGRAM WILL REMAIN GETBYTE UNTIL BYTE RECEIVED. SIGNAL START RECEIVING BYTE VALID (LOW) START BIT. NOTE: CYCLE PATH EACH RECEPTION MUST KEPT SAME MAINTAIN STEADY BAUD RATE.
PORT
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CALL GET_BIT
RESULT GOOD, THEN BYTE RECEIVED. PORT CONFIGURED INPUT.
LOAD
GBIT CALL GET_BIT
ROTATE INTO
STOPBIT CALL GET_BIT
RETURN
Figure GETBYTE
AN1831 Rev. MOTOROLA
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Application Note Routines Source Code
RDVRRNG PURPOSE: READ AND/OR VERIFY RANGE FLASH MEMORY STORE DESTINATION TEMP1
INIT TEMP2 COMPARE STATUS
CONTAINS FIRST ADDRESS RANGE; LADDR CONTAINS LAST ADDRESS READ; CONTAINS DESTINATION FIRST BYTE READ DATA PTA0); DATA CONTAINS DATA COMPARE READ DATA AGAINST
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INIT TEMP0 INDEX INTO DATA RDVRRNG010 FLASH DATA FROM FADDR FADDR LADDR+1?
PASS/FAIL FROM TEMP2 DEST. SERIAL VERIFY FLASH DATA INPUT DATA STORE FAILURE ($7E) INTO TEMP2 CHECKSUM
RETURN
RDVRRNG020 CALL PUT_BYTE
WRITE FLASH DATA INTO DATA RDVRRNG030 ACCUMULATE CHECKSUM
FADDR
TEMP3 DATA POINTER
Figure RDVRRNG
AN1831 Rev. MOTOROLA
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Application Note
PRGRNGE
PRGSTP8 DELAY TPROG
BUMP
PRGSTP9 INCREMENT DESTINATION ADDRESS BUFFPTR DECREMENT BYTECNT LOOPING VAR.
PURPOSE: PROGRAMS RANGE ADDRESSES FLASH MEMORY. ALLOWS PROGRAMMING RANGE ADDRESSES, WHICH DOES HAVE PAGE BOUNDARIES, EITHER BEGINNING END. EXAMPLE, PROGRAMMING $F001 $F008 VALID. THIS PREVENT TRYING PROGRAM NON-FLASH ADDRESS GETTING BACK VERIFICATION.
STACK BUFFPTR STACK BYTECNT BYTES BETWEEN STARTADDR PAGE PRGSTP1 LOOPING VARIABLE FLCR PRGSTP2 READ FLBPR PRGSTP3 WRITE FIRST ADDRESS RANGE PRGSTP4 DELAY TNVS PRGSTP5 HVEN FLCR PRGSTP6 DELAY TPGS
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DESTADDR LADDR+1?
CONTAINS FIRST ADDRESS RANGE; CTRLBYT SPECIFIES PROGRAMMING MODE; LADDR CONTAINS LAST ADDRESS READ; DATA CONTAINS DATA PROGRAMMED; CPUSPD CONTAINS SPEED DELAY ACCURACY
BYTECNT NEXTPAGE BYTECNT DESTINATION ADDR
LOOPING VARIABLE BYTECNT PAGESIZ
CLEAR HVEN FLCR DEST ADDR LADDR? PRGSTP13 RECONCILE STACK POINTER
PRGSTP10 CLEAR FLCR PRGSTP11 DELAY TNVH PRGSTP12 CLEAR HVEN FLCR
PRGSTP7 FETCH DATA BUFFPTR INTO DATA ARRAY STORE DATA CURRENT DESTINATION ADDRESS
RETURN
Figure PRGRNGE
AN1831 Rev. MOTOROLA
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DELNUS
PURPOSE: DELAY N*12 MHZ; (DELAY TIME[US]/12) (fOP[MHZ]*4) CYCLES 5+(DELAY/12)* 3(4fOP-3)+9 5+DELAY*fOP
SUBTRACT FROM CPUSPD (Acc)
NXTX PUSH ONTO STACK
CONTAINS TIME/12 DELAY MICROSECONDS.); CONTAINS CPUSPD (CPU SPEED SPEED MUST
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SUBTRACT FROM CPUSPD (Acc)
DECREMENT
SPEED FROM STACK
DECREMENT REGISTER (DELAY VAR)
RETURN
Figure DELNUS
AN1831 Rev. MOTOROLA
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Application Note
ERARNGE
PURPOSE: ERASE RANGE ADDRESSES FLASH MEMORY. PRESERVES CONTENTS (ADDRESS PASSED).
STACK ADDRESS PASSED
MASSBIT CTRLBYT?
ERASE FLCR
CONTAINS ADDRESS RANGE ERASED; RANGE SIZE SPECIFIED CONTROL BYTE
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MASSBIT CTRLBYT? MASS FLCR
DELAY LOOP CNTR
DELAY LOOP CNTR
MASSBIT CTRLBYT?
BUMP CALL DELNUS WITH TNVHLQ CPUSPD CALL DELNUS WITH TNVHQ CPUSPD
READ BLOCK PROTECT REGISTER
CALL DELNUS WITH TERASEQ CPUSPD DECREMENT LOOP COUNTER
CLEAR HVEN FLCR
MASSBIT CTRLBYT? WRITE BLOCK PROTECT REGISTER WRITE CONTENT ADDRESS SPECIFIED CALL DELNUS WITH TNVSQ CPUSPD HVEN FLCR
LOOP COUNTER
RESTORE ADDRESS PASSED FROM STACK
RETURN
BUMP
CLEAR ERASE MASS BITS FLCR
Figure ERARNGE
AN1831 Rev. MOTOROLA
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Application Note Routines Source Code
Routines Source Code
FILE NAME: MAINPR.ASM PURPOSE: provide FLASH erase, program verify routines reside ROM. TARGET DEVICE: MC68HC908GR8, MC68HC908KX8, MC68HC908JL3/JK3 MC68HC908JB8 MEMORY USAGE RAM: 4-36 BYTES, DEPENDING DATA PASSED ROM: BYTES ASSEMBLER: MCUEZ VERSION: 1.0.5 PROGRAM DESCRIPTION: This program contains structure routines facilitate FLASH programming. These routines, which individually callable, intended reside user program, test/burn-in program, development/programming tools. This routines included, along with definition files, project file 9GR8ALLROM.ASM. AUTHOR: Grant Whitacre LOCATION: Austin Hill, Texas UPDATE HISTORY: AUTHOR DATE DESCRIPTION CHANGE ============ ======== ===================== WHITACRE 10/05/98 Initial release WHITACRE 02/17/99 MODIFIED FLASH WHITACRE 08/23/99 MODIFIED GETBYTE 9600 BAUD 2.4576 GENERAL CODING NOTES: names labeled with <port name><bit number> used commands that operate individual bits, such BSET BCLR. name followed indicates label that will used form mask. INCLUDED FILES INCLUDE EQUATES PROGRAMMING TIMES FOLLOWING DEFINED .FRK FILE *TPROG ;FLASH Byte Program Time *TERASE 1000 ;FLASH Page Erase Time *TMERASE 4000 ;FLASH Mass Erase Time *TNVS ;FLASH PGM/ERASE HVEN Setup Time AN1831 Rev. MOTOROLA
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*TPGS *TNVH *TNVHL *TRCV ;FLASH ;FLASH ;FLASH ;FLASH Program Hold Time High-Voltage Hold Time High-Voltage Hold Time (Mass Erase) Return Read Time
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TIMES REPRESENT VALUES THAT PASSED DELAY ROUTINE, WHICH DELAYS VALUES PASSED. TERASE TMERASE, ROUTINE CALLED µs*17*20=4080 TIMES, RESPECTIVELY, WITH BUMP BEFORE EACH CALL ECALLS MECALLS TPROGQ ;FLASH Program Time TERASEQ ;FLASH Block Erase Time TMERASEQ ;FLASH Mass Erase Time TNVSQ ;FLASH PGM/ERASE HVEN Setup Time TPGSQ ;FLASH Program Hold Time TNVHQ ;FLASH High-Voltage Hold Time TNVHLQ ;FLASH High-Voltage Hold Time (Mass Erase) TRCVQ ;FLASH Return Read Time ROUTINES NAME: GETBYTE PURPOSE: byte data PTA0 Entry Conditions: Port configured input. Exit Conditions: Acc=byte received. break received result then send break jump back start. Port configured input. SUBROUTINES CALLED: GET_BIT VARIABLES READ: VARIABLES MODIFIED: STACK USED: SIZE: BYTES DESCRIPTION: EXECUTED Attempts receive byte from external controller PortA0. Once called, program will remain GETBYTE until byte received Signal start receiving byte valid (low) start bit. NOTE: Cycle path each reception must kept same maintain steady baud rate. TIMING 9+(17+10*23) CYCLES 2.4576 9600 BAUD GETBYTE: BRSET0 ,PTA,GETBYTE ;Waiting start edge. GET_BIT ;try receive full start bit. GETBYTE ;Success? #$80 ;initialize receiver. GBIT: ;got start bit, byte. GET_BIT AN1831 Rev. MOTOROLA
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RORA
GBIT
STOPBIT: GET_BIT ;look stop NAME: RDVRRNG PURPOSE: Read and/or Verify range FLASH memory ENTRY CONDITIONS: contains first address range; LADDR contain last address read; contains Boolean read data goes PTA0 (0=PTA0, else Data Array) DATA contains data compare read data against EXIT CONDITIONS: good compare; contains checksum; DATA contains read FLASH data SUBROUTINES CALLED: VARIABLES READ: LADDR, DATA ARRAY VARIABLES MODIFIED: DATA ARRAY STACK USED: SIZE: BYTES DESCRIPTION: EXECUTED ROM; ALTHOUGH THIS ROUTINE SERVICES COP, THERE COULD STILL TIME UNDER CERTAIN CONDITIONS. THESE CONDITIONS ARE: USER MODE, ENABLED, USING SHORT TIMEOUT, USING SUCH THAT CGMXCLK/4 RDVRRNG: PSHA ;(A)SAVE DESTINATION FLAG STACK 4,SP CLRA ;LOCAL VARIABLE CHECKSUM STARTS PSHA ;(B)SAVE STACK 3,SP ;LOCAL VARIABL INDEX INTO DATA STARTS PSHA ;(C)SAVE STACK 2,SP COMA ;LOCAL VARIABLE VERIFY STATUS GOOD) PSHA ;(D)SAVE STACK 1,SP RDVRRNG010: $FFFF ;BUMP ;LOAD CONTENT FLASH ADDRESS INTO ACC. 4,SP ;CHECK DESTINATION FLAG RDVRRNG020 ;SKIP COMPARE DESTINATION PTA0 PSHX ;(E)STORE FADDR LATER PSHH ;(F) 4,SP ;GET INDEX INTO DATA FROM STACK CLRH DATA,X ;COMPARE ADDR COMPARE CONTENT RDVRRNG015 EQUAL THEN KEEP GOING. DATA,X ;WRITE FLASH DATA THAT DIFFERENT #$7E ;FAILED VERIFICATION CLEAR VERIFY STATUS 3,SP ;MUST KEEP DATA CHECKSUM BELOW RDVRRNG015: PULH ;(F')GET FADDR BACK AN1831 Rev. MOTOROLA
into next ;baud calculation
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PULX RDVRRNG020: ;(E') RDVRRNG030 PUT_BYTE ;NOT COMPARING, JUST DUMPING ;WRITE DATA PORT ;PUT_BYTE SAVES
RDVRRNG030: 3,SP ;ADD VALUE CURRENT BYTE CHECKSUM 3,SP ;MAINTAIN RUNNING 2,SP ;INCREMENT INDEX INTO DATA CPHX LADDR ;COMPARE SOURCE ADDR LAST ADDRESS NOMO DONE, LOOP ANOTHER ;INCREMENT SOURCE ADDRESS RDVRRNG010 NOMO PULA ;(D')GET PASS/FAIL INFO INTO CARRY PULA ;(C')TRASH INDEX INTO DATA PULA ;(B')RETURN CHECKSUM ACC. ;(A')TRASH DESTINATION FLAG NAME: PRGRNGE PURPOSE: Programs range addresses FLASH memory ENTRY CONDITIONS: contains FIRST address range; CTRLBYT contains Control Byte that specifies programming mode; LADDR contains last address read; DATA contains data programmed EXIT CONDITIONS: Next address SUBROUTINES CALLED: DELNUS VARIABLES READ: CONTROL BYTE, CPUSPD, LADDR, DATA ARRAY VARIABLES MODIFIED: SIZE: BYTES STACK SIZE (INCLUDING CALL): BYTES DESCRIPTION: EXECUTED Allows passing range addresses PRGRNGE, which does have boundaries, either beginning end. I.e., passing $F001 $F008 valid. This prevent trying program non-FLASH address. PRGRNGE: ;MASK INTERRUPTS THAT DELAYS AFFECTED CLRA ;STORES INDEX INTO DATA ARRAY PSHA ;(A) INDEX INTO DATA STACK PSHX ;(B)SAVE FADDR THAT DESTROYED PSHH ;(C) ;GET (FADDR MODULUS ROWSIZE) #ROWSIZ CLRH ;HIGH BYTE IGNORED BECAUSE ROWSIZE ALWAYS POWER LESS. MUST IGNORED THAT RESULT DIVIDE WILL BYTE. AN1831 Rev. MOTOROLA
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Application Note Routines Source Code
PSHH PULH PULH PULX PSHA PSHA
1,SP
;DIVIDE LEAVES REMAINDER (MODULUS) ;(D)PUSH REMAINDER ONTO STACK ;MOVE ROWSIZE ;SUBTRACT REMAINDER #BYTES PROGRAM ;(D')PULL REMAINDER FROM STACK THROW AWAY ;(C')GET FADDR BACK FROM STACK ;(B') ;(B)STORE #BYTES STACK ;(C) RESERVE STACK LOC. LOOPING VAR. ;3,SP LOOPING VARIABLE ;4,SP #BYTES ;5,SP INDEX INTO DATA ARRAY ;BUMP ;SET LOOPING VARIABLE ALLOW BUMP; ;NEED TURN HVEN OCCASIONALLY BUMP ;SET ;($FF-MERASE.-ERASE.) ;MAKE SURE ERASE BITS ;WRITE THIS FLASH CONTROL REG. ;READ FROM BLOCK PROT. REG.
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PRGSTP1: PRGSTP2 PRGSTP3: IFEQ ENDIF IFNE ENDIF PSHH PSHX PRGSTP4 PRGSTP5 LDHX PRGSTP6
$FFFF #$06 1,SP #PGM. FLCR #$F9 FLCR FLBPR
TESTMOD TESTMOD
;WRITE FLASH ADDRESS WITHIN PROGRAMMED WITH DATA ;(D) ;(E)
#TNVSQ CPUSPD DELNUS #FLCR #HVEN. #TPGSQ CPUSPD DELNUS
;DELAY TNVS
;SET HVEN FLCR
;DELAY TIME TPGS
PULX ;(E') PULH ;(D' AN1831 Rev. MOTOROLA
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NEED PROGRAM BYTES, TURN AND/OR HVEN, BUMP COP, PROGRAM ANOTHER BYTES, THEN REPEAT PROCESS UNTIL FINISHED WITH RANGE PRGSTP7 PSHH ;(D) PSHX ;(E) ;1,SP ADDR(LSB) ;2,SP ADDR(MSB) ;3,SP LOOPING VARIABLE ;4,SP #BYTES ;5,SP INDEX INTO DATA ARRAY CLRH ;GET 0:BUFFPTR INTO 5,SP ;GET INDEX INTO DATA ARRAY DATA,X ;LOAD BYTE PROG FROM DATA+BUFFPTR PULX ;(E') BYTE ADDR BACK INTO PULH ;(D') IFEQ TESTMOD ENDIF IFNE TESTMOD ;STORE DATA ADDR SPEC.BY ENDIF PSHH ;(D) PSHX ;(E) PRGSTP8 #TPROGQ ;DELAY TPROG CPUSPD DELNUS PULX ;(E') PULH ;(D') PRGSTP9: CPHX PRGSTP10: NEXTROW:
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#$01 3,SP 2,SP 1,SP LADDR PRGSTP10 2,SP PRGSTP10 1,SP PRGSTP7 CLR_P_H PRGSTP1
;INCREMENT DESTINATION ADDRESS ;INCREMENT POINTER INTO DATA ;DECREMENT BYTE COUNTER ;DECREMENT LOOPING VARIABLE ;CHECK RANGE ;EXIT LOOP PAST RANGE ;CHECK ;EXIT LOOP DONE WITH ;COP
CLR_P_H
2,SP
;CALL CLEAR HVEN ;DONE WITH ROW, READY EXIT ;1,SP LOOPING VARIABLE ;2,SP #BYTES ;3,SP INDEX INTO DATA ARRAY ;ADD BYTES PROGRAMMED BYTE AN1831 Rev.
MOTOROLA
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Application Note Routines Source Code
PSHH PULA PSHA PULH CPHX PRGSTP13: PULA PULA PULA DONEPRG
;(D) CORRECT HIGH BYTE CARRY, ;(D') ;(D) ;(D') #ROWSIZ 2,SP LADDR PRGSTP1 ;#BYTES ROWSIZE ;DECREMENT CURRENT ADDRESS COMP. LAST ADDR ;COMPARE FADDR LADDR ;PROGRAM ANOTHER LESS EQUAL ;NEXT INST. TAKE ;(C')REMOVE LOOP VARIABLE ;(B')REMOVE #BYTES ;(A')REMOVE INDEX INTO DATA ADDRESS
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FOLLOWING LOCAL SUB-ROUTINE CLEARS PGM, DELAYS, THEN CLEARS HVEN. CLR_P_H PSHH ;(D) PSHX ;(E) LDHX #FLCR ;CLEAR #PGM. PRGSTP11: #TNVHQ ;DELAY TNVH CPUSPD DELNUS PRGSTP12: LDHX #FLCR ;CLEAR HVEN #HVEN. PULA ;(E') PULH ;(D')
AN1831 Rev. MOTOROLA
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NAME: DELNUS PURPOSE: Delay ENTRY CONDITIONS: CONTAINS TIME/12 DELAY ms). CONTAINS SPEED BITS PRECISION) EXIT CONDITIONS: SUBROUTINES CALLED: VARIABLES READ: VARIABLES MODIFIED: SIZE: BYTES STACK USED (INCLUDING CALL): BYTES DESCRIPTION: EXECUTED Delay Routine MHz, Delay (delay time[µs]/12) H:X, (fOP[MHz]*4) then CYCLES 5+Delay/12[3(4fOP-3)+9] 5+DELAY*fOP then CYCLES 5+12(DELAY/12) 5+DELAY where delay DELNUS: DECA CYCLE NXTX PSHA DECA DECA DBNZA PULA DBNZX NXTX NAME: ERARNGE PURPOSE: Erase range addresses FLASH memory ENTRY CONDITIONS: contains address range erased; range size specified Control Byte then mass erase, otherwise erase page bytes GR8). EXIT CONDITIONS: Preserves contents (address passed) SUBROUTINES CALLED: DELNUS VARIABLES READ: CTRLBYT, CPUSPD VARIABLES MODIFIED: STACK USED: SIZE: BYTES DESCRIPTION: Does check blank range before erase necessary) after successful erase) ERARNGE: PSHH ;KEEP ADDRESS PASSED PSHX CLRA ;SET ERASE BIT, #ERASE. AN1831 Rev. MOTOROLA
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BRCLR MASSBIT,CTRLBYT,AMBS #MASS. AMBS: FLCR ERABLK FLBPR IFEQ TESTMOD FLBPR ENDIF IFNE TESTMOD BRCLR MASSBIT,CTRLBYT,NOBLWR FLBPR NOBLWR ENDIF LDHX BRCLR RWERASE ERADEL PSHA BUMPCOP PULA LDHX BRCLR LDHX PGSTUP LDHX STUPDEL #TNVSQ CPUSPD DELNUS #FLCR #HVEN. MASSBIT,CTRLBYT,RWERASE #MECALLS ERADEL #ECALLS
;MASS NECESSARY ;READ BLOCK PROTECT REGISTER ;WRITE ADDRESS ERASE RANGE
;DELAY TNVS
;SET HVEN FLCR
;DELAY LOOPS TMERASE ;DELAY LOOPS TERASE ;STACK INCREMENT COUNTER ;BUMP ;SAME TERASEQ TMERASEQ
$FFFF #TERASEQ CPUSPD DELNUS 1,SP BUMPCOP $FFFF #FLCR #ERASE. #($FF-MASS.) MASSBIT,CTRLBYT,PGSTUP #TNVHLQ STUPDEL #TNVHQ CPUSPD DELNUS
;PULL INCREMENT CNTR STACK ;BUMP WHEN DONE DELAYING ;CLEAR ERASE
;CLEAR MASS
;DELAY TNVHL ;DELAY TNVH
AN1831 Rev. MOTOROLA
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Application Note
LDHX #FLCR #HVEN. ;CLEAR HVEN
XERARNG PULX ;RESTORE ADDRESS PASSED PULH ;THESE INST. DELAY LEAST (TRCV)
NOTE:
following routines resident MC68HC908KX8 only.
ROUTINE NAME: ICGTRIM PURPOSE: TRIM ROUTINE BASED MEASUREMENT LENGTH BREAK SIGNAL SENSED PTA0 PTB4/RXD. ENTRY CONDITIONS: ENABLED (ICGON SET); INTERNAL CLOCK SELECTED CLEARED); CLEARED SELECT PTB4/RxD MONITOR BREAK SIGNAL, NON-ZERO SELECT PTA0; PORT USED BEEN CONFIGURED INPUT COMMUNICATION. EXIT CONDITIONS: CARRY TRIMMED SUCCESSFULLY; MONITOR PORT CONFIGURED INPUT SUBROUTINES CALLED: NONE VARIABLES READ: VARIABLES MODIFIED: ICGTR, ICGCR, ICGMR STACK USED: BYTE SIZE: BYTES DESCRIPTION: EXECUTED ROM, THIS ROUTINE CHECKS MANY CYCLES MEASURED DURING BREAK SIGNAL BITS) SENT 9600 BAUD HOST ADJUSTS TRIM MULTIPLIER REGISTERS. BREAK SIGNAL MORE THAN VARIATION FROM WHAT EXPECTED (.78-1.30 9600), THEN TRIMMING WILL PERFORMED. THIS ACCURACY LIMIT CONSISTENT WITH EXTENT ICG'S ABILITY FINE-TUNE TRIM REGISTER. ICGTRIM: #$20,ICGMR ;SET 307.2 9.8304 BRCLR ICGS,ICGCR,* ;WAIT CLOCK STABILIZE CLRX CLRH TSTA ;SEE PTA0 PTB4 USED MONPTB4 ;BRANCH BLANK MONITOR PTB4 BRSET 0,PTA,* ;WAIT BREAK SIGNAL START FOLLOWING LOOP EXECUTED UNTIL BREAK SIGNAL. BREAK SIGNAL LASTS TIMES. COMMUNICATING fOP/256 BPS, THEN TIMES 2560 CYCLES. EACH TIME THROUGH LOOP CYCLES, EXPECT EXECUTE LOOP TIMES SYNC SERIALLY WITH HOST. STAY LOOP LOOP CYCLES, THEN MUST RUNNING FASTER THAN EXPECTED, NEEDS SLOWED DOWN. AN1831 Rev. MOTOROLA
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STAY LOOP LOOP CYCLES THEN MUST RUNNING SLOWER THAN EXPECTED NEEDS SPEEDED AMOUNT THAT CHANGE SPEED EQUAL NUMBER LOOP CYCLES OVER UNDER 256. THROUGH LOOP TIMES, THEN RUNNING (256-240)/256 6.25% FAST. EACH INCREMENTAL CHANGE MAKE TRIM REGISTER (ICGTR) WILL MAKE 0.195% CHANGE INTERNAL CLOCK. THAT INCREMENTING REGISTER OVER DEFAULT VALUE STORED THERE WILL DECREASE INTERNAL CLOCK 0.195%, VICE VERSA. EACH EXECUTION LOOP OVER UNDER WHAT EXPECTED (256 TIMES) REPRESENTS ERROR 1/256 .391% ERROR. WE'LL NEED DOUBLE NUMBER LOOP CYCLES THIS NUMBER CORRECT TRIM REGISTER. PRECISION TRIMMING THEREFORE 0.391%. COUNTS RECEIVED DEVICE BAUD RATE 9600 (fOP 2.4576 MHZ): BAUD RATE EXPECTED COUNT COUNTS COUNTS ICGMR ========= ============== ========== ========== ========= 9600 (0100H) (00C0H) (0140H) ;(5) LOOP BREAK OVER ;(2) INCREMENT COUNTER ;(3) BACK CHECK SIGNAL AGAIN ;WAIT BREAK SIGNAL START ;(5) LOOP BREAK OVER ;(2) INCREMENT COUNTER ;(3) BACK CHECK SIGNAL AGAIN
CHKPTA0 BRSET 0,PTA,BRKDONE CHKPTA0 MONPTB4 BRSET 4,PTB,* CHKPTB4 BRSET 4,PTB,BRKDONE CHKPTB4 BRKDONE PSHH PULA TSTA SLOW FAST #$40 #$80 ICGDONE SLOW #$C0 #$80 ICGDONE ICGTR IFEQ TESTMOD ICGTEST ENDIF EXITTRM
;PUT HIGH BYTE WORK WITH LOOP CYCLES THEN BREAK TAKES ;FEW CYCLES THAN EXPECTED, TRIM SPEEDING fOP. ;SEE BREAK WITHIN TOLERANCE ;DON'T TRIM RANGE ;BREAK LONGER THAN EXPECTED, SLOW DOWN ;SEE BREAK WITHIN TOLERANCE ;DON'T TRIM RANGE
;SET CARRY SIGNIFYING TRIM OCCURRED ;CLEAR CARRY SIGNIFYING TRIMMED
AN1831 Rev. MOTOROLA
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Application Note
NAME: ICGTEST PURPOSE: Following tests above settings internal clock desired rate. Internal clock rate frequency sensed port ENTRY CONDITIONS: NONE EXIT CONDITIONS: PULLED EXIT, PTA4 OUTPUT SUBROUTINES CALLED: NONE VARIABLES READ: VARIABLES MODIFIED: PTA, DDRA STACK USED: SIZE: BYTES DESCRIPTION: EXECUTED ICGTEST BSET 4,DDRA ;bit output BITOFF BCLR 4,PTA cycles EXITLP cycles cycle BITON BSET 4,PTA cycles cycle BITOFF cycles EXITLP cycles
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Motorola, Inc., 2001
AN1831/D
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AN1831 Using MC68HC908 On-Chip FLASH Programming Routines Fr

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