AN1827 Freescale Semiconductor, Inc. Programming Erasing FLA

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AN1827 Freescale Semiconductor, Inc. Programming Erasing FLA

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Freescale Semiconductor, Inc.
Programming Erasing FLASH Memory MC68HC908AS60
Keating, Adeela Gill, Kazue Kikuchi Body Electronics Occupant Safety Matt Rutledge Non-Volatile Memory Technology Center
Introduction
Motorola released innovative type FLASH non-volatile memory (NVM) 8-bit M68HC08 Family microcontrollers. This FLASH technology allows in-circuit reprogrammability over entire automotive specification range. In-circuit reprogrammability offers these advantages: In-system code revision EPROM (erasable programmable read-only memory) replacement reusable code development platform Quick time market with chip code development production obsolete inventory with parts Allows last-minute code changes without waiting code lots
Motorola, Inc., 1999
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Freescale Semiconductor, Inc. Application Note
This application note explains FLASH MC68HC908AS60 provides example software program erase operations. reprogramming algorithms written both M68HC08 assembly code code. This code available download from Motorola's Semiconductor Product Sector's site http://mot-sps.com. FLASH topics covered this application note include: Features Implementation Motorola's M68HC08 microcontrollers Functional description Control block protect registers Charge pump Block protection Erase operation Page program/margin read algorithm Frequently asked questions Hardware schematic Assembly source code source code
Freescale Semiconductor, Inc.
Features
benefits FLASH MC68HC908AS60 include: Single power supply utilized program/erase. This feature simplifies program erase with respect EPROM high voltage power supply (ultraviolet) oven required), reduces program erase cycle time, enables in-circuit reprogrammability.
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Application Note Implementation Motorola's M68HC08 Microcontrollers
FLASH manufacturing process fully compatible with EEPROM (electrically erasable, programmable read-only memory) process. This process compatibility allows functionality both FLASH EEPROM non-volatile memories same chip. Meets automotive specifications Unlike many competing microcontrollers with FLASH, this FLASH operate meet reliability requirements automotive space. FLASH MC68HC908AS60 will read, program, erase over -40°C 125°C temperature range. specified program/erase endurance data retention lifetime valid over entire temperature range. Multiple arrays Multiple arrays MC68HC908AS60 allow code execution array while programming erasing other array. Smart programming algorithm smart programming algorithm ensures minimum program time while still guaranteeing automotive environment operation data retention.
Freescale Semiconductor, Inc.
Implementation Motorola's M68HC08 Microcontrollers
specific FLASH technology found MC68HC908AS60 known FLASH 2TS, reference 2-transistor source-select cell. FLASH commonly found Motorola's M68HC08 Family microcontrollers, exclusive FLASH technology HC08 core. FLASH technology discussed this application note referred generically FLASH. This FLASH technology available array sizes between Kbytes Kbytes. parts requiring more than Kbytes, multiple arrays size between Kbytes Kbytes, with 2-Kbyte boundaries, placed chip. Typically, only charge pump used parts with multiple arrays. This constrains program erase operations array time, conserves area.
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Freescale Semiconductor, Inc. Application Note
FLASH cell consists transistors series, referred select-gate control-gate transistors. floating gate associated with control gate transistor stores charges which represent different data states memory. high threshold condition cell erased state threshold condition programmed state. select gate prevents cell leakage unselected wordlines during read operations when floating gate programmed.
Freescale Semiconductor, Inc.
Although size shape array mostly transparent user, does help when determining "cared addresses" during erase algorithm. term function "cared addresses" explained Erase Operation this application note. now, important know that cared addresses determine exactly which block will erase during erase operation. More importantly, size shape memory array alter size programming page. term page refers number consecutive bytes that programmed during page program/margin read operation. larger memory arrays, like arrays found MC68HC908AS60, page equals eight bytes. array scaled down, page proportionally scaled either four, two, byte(s). This will affect programming algorithm that appears later this application note. only other obvious difference implementation FLASH array size blocks that protected against undesired program erase operation. Again, this depends size memory microcontroller. Check appropriate documentation each specific microcontroller determine size memory array, page program size, erase block sizes.
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Application Note Functional Description
Functional Description
FLASH memory MC68HC908AS60 physically consists independent arrays with bytes block protection additional bytes user vectors. erased reads logic programmed reads logic Program erase operations facilitated through control bits memory mapped registers. Details these operations appear later this application note.
Freescale Semiconductor, Inc.
Memory FLASH array organized into pages within rows. There eight pages memory with eight bytes page. minimum erase block size single row, bytes. Programming performed per-page basis, eight bytes time. address ranges user memory, control registers, block protect registers, vectors listed here. FLASH memory MC68HC908AS60 consists $0450-$05FF, FLASH-2 array, bytes $0E00-$7FFF, FLASH-2 array, 29,184 bytes $8000-$FDFF, FLASH-1 array, 32,256 bytes $FE0B, FLASH-1 control register, FLCR1 $FE11, FLASH-2 control register, FLCR2 $FF80, FLASH-1 block protect register, FLBPR1 $FF81, FLASH-2 block protect register, FLBPR2 $FFDA-$FFFF, FLASH-1 vector space, bytes
program FLASH, each page must erased before programmed. erase block sizes found Erase Operation. four 64-byte address boundaries MC68HC908AS60 are: $xx00-$xx3F $xx40-$xx7F $xx80-$xxBF $xxC0-$xxFF
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Freescale Semiconductor, Inc. Application Note
When programming FLASH, exact program time must used program page. Excessive program time result program disturb condition, which case erased being programmed becomes unintentionally programmed. Program disturb avoided using iterative program margin read technique known smart programming algorithm. smart programming algorithm required whenever programming FLASH. Page Program/Margin Read Algorithm.
NOTE:
security feature prevents viewing FLASH contents.1 Programming tools available from Motorola. Contact local Motorola representative more information.
Freescale Semiconductor, Inc.
Control Block Protect Registers
Each FLASH array registers that control operation, FLASH control register (FLCR) FLASH block protect register (FLBPR). Figure Figure
Read: FDIV1 Write: Reset: FDIV0 BLK1 BLK0 HVEN MARGIN ERASE
Figure FLASH Control Register (FLCR) There FLASH control registers, FLCR1 FLCR2, FLASH-1 FLASH-2 arrays, respectively. $FE0B FLASH-1 control register (FLCR1) $FE11 FLASH-2 control register (FLCR2)
security feature absolutely secure. However, Motorola's strategy make reading copying FLASH difficult unauthorized users.
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Application Note Control Block Protect Registers
FDIV1 Frequency Divide Control This read/write together with FDIV0 selects factor which charge pump clock divided from clock. Charge Pump. FDIV0 Frequency Divide Control This read/write together with FDIV1 selects factor which charge pump clock divided from clock. Charge Pump.
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BLK1 Block Erase Control This read/write together with BLK0 allows erasing blocks varying sizes. Erase Operation description available block sizes. BLK0 Block Erase Control This read/write together with BLK1 allows erasing blocks varying sizes. Erase Operation description available block sizes. HVEN High-Voltage Enable This read/write enables charge pump drive high voltages program erase operations array. HVEN only either ERASE proper sequence erase page program/margin read followed. High voltage enabled array charge pump High voltage disabled array charge pump MARGIN Margin Read Control This read/write configures memory margin read operation. MARGIN cannot HVEN MARGIN will automatically clear (MARGIN asserted when HVEN Margin read operation selected Margin read operation unselected
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Freescale Semiconductor, Inc. Application Note
ERASE Erase Control This read/write configures memory erase operation. ERASE interlocked with such that both bits cannot same time. Erase operation selected Erase operation unselected Program Control This read/write configures memory program operation. interlocked with ERASE such that both bits cannot same time. Program operation selected Program operation unselected
Read: Write: Reset: BPR3 BPR2 BPR1 BPR0
Freescale Semiconductor, Inc.
Non-volatile, programmed, erased Don't care
Figure FLASH Block Protect Register (FLBPR) There FLASH block protect registers, FLBPR1 FLBPR2, FLASH-1 FLASH-2 arrays, respectively. $FF80 FLASH-1 block protect register (FLBPR1) $FF81 FLASH-2 block protect register (FLBPR2)
BPR3 Block Protect Register This protects memory contents address range: FLASH-1 $C000 $FFFF FLASH-2 $4000 $7FFF. Address range protected from erase program Address range open erase program
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Application Note Charge Pump
BPR2 Block Protect Register This protects memory contents address range: FLASH-1 $A000 $FFFF FLASH-2 $2000 $7FFF. Address range protected from erase program Address range open erase program BPR1 Block Protect Register This protects memory contents address range: FLASH-1 $9000 $FFFF FLASH-2 $1000 $7FFF. Address range protected from erase program Address range open erase program BPR0 Block Protect Register This protects memory contents address range: FLASH-1 $8000 $FFFF FLASH-2 $0450 $7FFF. Address range protected from erase program Address range open erase program
Freescale Semiconductor, Inc.
Charge Pump
internal charge pump required program, margin read, erase operations FLASH. charge pump dynamic circuit that uses specific clocking sequence capacitors switches generate voltages higher magnitude than VDD. This charge pump design requires clock frequency range between operate FLASH correctly. charge pump clock derived from clock. FDIV1 FDIV0 bits FLASH control register able divide internal clock generate charge pump clock. These divide ratios allow enough tolerance several commonly available crystal frequencies. Table common divide ratios based upon internal frequency.
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Freescale Semiconductor, Inc. Application Note
NOTE:
When FLASH memory programmed/erased with monitor mode, frequency always same external clock frequency divided four. Since charge pump frequency derived from frequency, confirm frequency being used. Table Frequency Divide Ratios Charge Pump Clock
fBus (MHz) 2.000 FDIV1 FDIV0 Division fPump (MHz) 2.000 2.4576 2.000 2.4576 2.000 2.100
Freescale Semiconductor, Inc.
2.4576 4.000 4.9152 8.000 8.400
NOTE:
charge pump frequency between MHz, Motorola does guarantee operation, electrical, reliability specifications FLASH. HVEN FLASH control register enables charge pump generate high voltages program erase modes. charge pump also generates regulated voltage margin read mode smart programming algorithm. During programming, HVEN should asserted only time. (See Figure Asserting HVEN longer than time risks program disturb, where erased same becomes unintentionally programmed. Program disturb common soft fault recovered erasing reprogramming using smart programming algorithm.
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Application Note Block Protection
Block Protection
protect contents FLASH array from being inadvertently programmed erased run-away code user application, FLASH block protect register option implemented. This register composed non-volatile bytes within FLASH-1 array, with byte FLASH array. Once block protect bits FLBPR registers, defined address ranges protected from being programmed erased. Control Block Protect Registers description address ranges. FLBPR register itself erased programmed only with external voltage pin. defined voltage between block protect register additional measure prevent inadvertent programming erasing FLASH contents application.
Freescale Semiconductor, Inc.
NOTE:
implement in-system program erase protected area FLASH, high voltage signal must routed pin.
Erase Operation
erase FLASH array, follow this 9-step procedure. Figure shows flowchart this procedure. ERASE bits FDIV bits. ERASE configures FLASH memory erase operation. bits determine erase block size: whole array, half array, bytes bytes. FDIV bits determine charge pump frequency. frequency should selected within range between MHz. Refer Charge Pump. Read FLASH block protect register. block protect registers must read before high voltage enabled. desired address step protected block, erase will fail.
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Freescale Semiconductor, Inc. Application Note
Write FLASH address within block address range desired. "cared" bits FLASH address latched used determine address range that will erased. details discussed later this section. HVEN Internal high voltage applied erasing. Wait time, tErase.
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tErase block erase time. HVEN Internal high voltage disabled. Wait time, tKill. This allows high voltage discharged completely. ERASE Disable erase operation. Wait time, tHVD. After time, tHVD, memory accessed normal read mode.
NOTE:
bulk erase attempted FLASH array where either part array block protected, then none FLASH memory that array erased.
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Application Note Erase Operation
ERASE FLASH
ERASE BIT, BITS FDIV BITS
READ BLOCK PROTECT REGISTERS (FLBPR)
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WRITE ADDRESS BLOCK ERASE
HVEN
WAIT TIME, tErase
CLEAR HVEN
WAIT TIME, tKill
CLEAR ERASE
WAIT TIME, tHVD
ERASE OPERATION COMPLETE
Figure FLASH Erase Operation Flowchart
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Freescale Semiconductor, Inc. Application Note
Although overall procedure relatively simple, step could some clarification. Since specified address address within block erase, microcontroller must somehow know exactly which memory range erase. This where "cared address" becomes important. step size block erase writing bits FLCR. Table shows various block sizes which erased erase operation.
Freescale Semiconductor, Inc.
Table Erase Block Sizes
BLK1 BLK0 Block Size Full array: Kbytes One-half array: Kbytes Eight rows: bytes Single row: bytes Cared Addresses A15-A14 A15-A9 A15-A6
When address specified step certain address lines latched pertaining this block size, they establish start addresses block. larger erase block, smaller size cared address. example, bits such that erase block size single (BLK0 BLK1 address $9AF0 specified step then bits 15-6 $9AF0 "cared addresses." Therefore, values these address bits fixed.
Binary
Cared Addresses Figure Cared Address Example $9AF0
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Application Note Erase Operation
result, beginning address block which will erased
Binary
Cared Addresses
Freescale Semiconductor, Inc.
Figure Erase Beginning Address Example address block which will erased
Binary
Cared Addresses Figure Erase Address Example This results erasing bytes from address $9AC0 $9AFF.
NOTE:
memory arrays shaped differently, equal bytes like MC68HC908AS60. Refer appropriate documentation pertinent device apply these same principles.
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Freescale Semiconductor, Inc. Application Note Page Program/Margin Read Algorithm
MC68HC908AS60, programming FLASH memory done page-by-page basis. page consists eight bytes, from addresses $XXX0 $XXX7 from $XXX8 $XXXF. Therefore, addresses first byte page must $XXX0 $XXX8. This FLASH memory requires smart programming algorithm. smart programming algorithm defined iterative program margin read sequence. Every page program operation followed margin read until data programmed successfully. margin read step smart programming algorithm used ensure programmed bits programmed sufficient margin data retention over device's lifetime. smart programming algorithm steps shown here Figure flowchart. Initialize attempt counter. sequence will attempted until count reaches flsPulses. FDIV bits. configures FLASH memory program operation enables latching address data programming. FDIV bits determine charge pump frequency. frequency should selected within range between MHz. Refer Charge Pump. Read FLASH block protect register. block protect register must read before high voltage enabled. desired address protected block, programming will fail. Write data page being programmed (typically bytes). This requires separate write operations each byte addresses page must $XXX0 $XXX7, $XXX8 $XXXF.
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Application Note Page Program/Margin Read Algorithm
HVEN Internal high voltage applied programming. Wait time, tStep. tStep time high voltage applied every program pulse. HVEN Internal high voltage disabled. Wait time, tHVTV.
Freescale Semiconductor, Inc.
Wait programming voltages dissipate before margin reading. MARGIN This configures FLASH memory margin read operation. Wait time, tVTP. Time discharge margin read voltage. This step disables programming operation. Wait time, tHVD. After time, tHVD, memory accessed normal read mode. Read programmed data (margin read process). This requires separate read operations each byte. Compare margin read data with data written Step This requires separate read operations each byte. Clear MARGIN bit. Disable margin read operation. Increment attempt counter since programming successful. byte programmed data does match margin read data, then there options. count less than maximum (flsPulses(); return step repeat programming same page. attempt program count reached flsPulses, programming operation failed.
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Freescale Semiconductor, Inc. Application Note
Notes: This algorithm mandatory programming FLASH. This page program algorithm assumes page(s) programmed initially erased.
PROGRAMMING FLASH
INITIALIZE ATTEMPT COUNTER
FDIV BITS
READ FLBPR
Freescale Semiconductor, Inc.
WRITE DATA SELECTED PAGE
HVEN WAIT TIME, tStep CLEAR HVEN WAIT TIME, tHVTV MARGIN WAIT TIME, tVTP CLEAR WAIT TIME, tHVD CLEAR MARGIN MARGIN READ PAGE DATA
INCREMENT ATTEMPT COUNTER BYTES MARGIN READ DATA EQUAL WRITE DATA CLEAR MARGIN
ATTEMPT COUNT EQUAL flsPulses PROGRAMMING OPERATION FAILED
PROGRAMMING OPERATION COMPLETE
Figure FLASH Smart Programming Algorithm Flowchart
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INTERNAL SIGNALS USER CONTROLLABLE REGISTERS
tStep WAIT TIME, tStep WAIT TIME, tHVTV MARGIN WAIT TIME, tVTP CARE DATA CLEAR HVEN tHVTV tVTP tHVD CLEAR WAIT TIME, tHVD MARGIN READ PAGE DATA COMPARE MARGIN READ DATA WRITE DATA CLEAR MARGIN
IT12
FDIV1
FDIV0
HVEN
MARGIN
STEP
INITIALIZE ATTEMPT COUNTER (NOT SHOWN)
FDIV BITS
READ FLBPR
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WRITE DATA SELECTED PAGE
HVEN
Application Note Page Program/Margin Read Algorithm
Figure Timing Diagram Page Program-Margin Read Step Smart Programming Algorithm
Freescale Semiconductor, Inc. Application Note
smart programming algorithm ensures programming data retention minimum program time reduces possibility program disturb. margin read operation imposes more stringent read condition cell that long-term data retention ensured. operation same ordinary read operation except margin (MARGIN However, when margin read operation executed, data read automatically with seven additional cycles byte. This additional settling time allows sensing lower cell current.
Freescale Semiconductor, Inc.
smart programming algorithm also uses multiple short program pulses instead using long program pulse. Therefore, whenever margin read successful, page programming completed even program pulses reach maximum. program pulses reach maximum, means that programming operation failed.
NOTE:
When enabled, seven additional cycles margin read operation must considered. Since counter continues during additional cycles, additional cycles need added feed loop. When block protect bits FLASH block protect register set, portion memory will locked that further erase program operation performed. However, when high voltage applied pin, whole FLASH memory unprotected. details described Control Block Protect Registers.
NOTE:
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Application Note Frequently Asked Questions
Frequently Asked Questions
These questions answers designed help user with frequent concerns.
Question Answer
cannot program/erase FLASH memory all. What should consider make program/erase code work? Check following: smart programming algorithm your programming code? smart programming algorithm ensures that FLASH programmed sufficient data retention minimum program time. Furthermore, following this algorithm lead overprogramming, which risks program disturb. smart programming algorithm highly recommended. (Refer Page Program/Margin Read Algorithm.) each step smart programming algorithm erase algorithm) performed right order? sequence program erase operations interlocked hardware only prescribed order these operations occur. However, other non-FLASH operations occur between steps shown. memory block where want program/erase unprotected? block protect feature FLASH present prevent unintentional programming erasing. block protect bits must such that memory erased programmed unprotected. only override block protect bits apply voltage during erase program algorithms. (Refer Block Protection.) delay times such tStep, tErase, tHVD, etc., within specification? Timing critical ensure proper FLASH operation. Delay times that long short alter FLASH performance point where does work reliable. Motorola does
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Freescale Semiconductor, Inc. Application Note
guarantee FLASH performance wrong delay times used. correct FLASH register being written enable erase program? MC68HC908AS60 FLASH arrays with separate sets control block protect registers. Make sure appropriate register being addressed. Refer Control Block Protect Registers. maximum pulse value (flsPulses) correctly according specification? Usually, FLASH will program fewer than maximum specified number program pulses allowed. However, specification chosen ensure that even worst-case (slowest) bits program allowing enough programming time. Setting this value lower than specification work time. Refer electrical specifications MC68HC908AS60 Advance Information, Motorola document order number MC68HC908AS60/D. charge pump frequency correct? charge pump frequency between MHz. speed between MHz, must FDIV bits generate suitable charge pump frequency. Refer Charge Pump. enabled? enabled, make sure that cleared before reset occurs. Remember that margin read mode, every byte requires seven additional cycles sensing. Refer Page Program/Margin Read Algorithm.
Freescale Semiconductor, Inc.
Question Answer
What FLASH charge pump? charge pump dynamic (clocked) circuit which generates high voltages internally FLASH program erase non-volatile memory.
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Application Note Frequently Asked Questions
Question
MC68HC908AS60 FLASH programs page (eight bytes) time. always have program entire page? necessary program entire page. Addresses which programmed left they were before page programming started. page includes reserved bytes, these bytes should programmed.
Answer
Question
have smart programming algorithm? smart programming algorithm required. Motorola does guarantee performance FLASH this algorithm followed. Refer Page Program/Margin Read Algorithm.
Freescale Semiconductor, Inc.
Answer
Question Answer
During program/erase process, execute interrupt service include additional steps? Unrelated (non-FLASH) steps included between steps program/erase algorithms long sequence steps remains consistent. However, interrupt service routines cause errors program erase timing lead corrupt missing data FLASH. Motorola does guarantee performance FLASH interrupts masked during program erase operations.
Question
executing program/erase code memory arrays. same array programmed/erased?
Answer
Question
running program/erase code memory arrays, other memory array programmed/erased? Yes. MC68HC908AS60 FLASH memory arrays. array used executing code while programming/erasing other.
Answer
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Freescale Semiconductor, Inc. Application Note
Question Answer program/erase both FLASH arrays same time? charge pump shared between both arrays minimize silicon area cost. Therefore, only high voltage FLASH operation (either program erase) occur time MC68HC908AS60.
Question
FLASH specification states that maximum eight page program cycles done between erase cycles. What does this mean? This specification states that bytes eight pages) should programmed more than eight times before erasing. Programming excess eight times risks inadvertent programming erased bits. (This type fault known program disturb.) Programming done per-page basis where eight smart programming cycles used typically program eight pages, programming entire bytes. further programming required after eight program cycles, must erased first before programmed again.
Freescale Semiconductor, Inc.
Answer
Question
When writing eight bytes data page FLASH memory programming, does order written data matter? long bytes written within page, data latched programming operation.
Answer
Question Answer
cannot program/erase FLASH block protect register (FLBPR). program erase FLBPR, must apply pin. Refer Control Block Protect Registers.
Question
Does frequency affect programming time? example, programming time using 8-MHz frequency shorter than using 2-MHz frequency? FLASH program times using 8-MHz verses 2-MHz have minimal difference.
Answer
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Application Note Frequently Asked Questions
Question
sending external data serially into MC68HC908AS60 programming. speed this process? MC68HC908AS60 higher speed, improve non-FLASH overhead during programming.
Answer
Question
program FLASH with 2-MHz frequency, read FLASH with 8-MHz frequency without problems? Yes. FLASH will meet specifications, including data retention performance, FLASH programmed/erased used within specification limits.
Freescale Semiconductor, Inc.
Answer
Question Answer
maximum number program attempts (flsPulses) high? This limit high account worst case manufacturing process variations, ensuring that slowest FLASH will still program. average, page program times much faster than this worst case limit.
Question Answer
program/erase operation successful monitor mode. FLASH memory protected monitor mode make difficult unauthorized users view memory contents. Before programming/erasing FLASH, security feature part must "broken" view FLASH contents. When attempt break security fails, FLASH addressed during reads invalid data will observed. Refer monitor section, which describes break security, MC68HC908AS60 Advance Information, Motorola document order number MC68HC908AS60/D.
Question
have failed break security monitor mode. execute bulk erase? Yes. Bulk erase only FLASH operation attempt when failing break security monitor mode. Make sure block protect feature asserted override bulk erase device.
Answer
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Freescale Semiconductor, Inc. Application Note
Question monitor mode, tell break security been successful? security check unsuccessful, memory reads will return same data every byte read instead code data expected.
Answer
Question
need confirm memory contents after programming FLASH? recommended that code used program FLASH also include verification step ensure integrity data programmed into FLASH. Some sort error flag should data FLASH does agree with what programmed.
Freescale Semiconductor, Inc.
Answer
Question
block memory FLASH array protected programming block protect register. When execute bulk erase without applying high voltage pin, will array, except protected block, erased? part array being bulk erased protected, bulk erase operation defeated unless high voltage placed IRQ.
Answer
Question Answer
What expected lifetime FLASH memory? minimum program/erase endurance data retention lifetime FLASH memory conditions found MC68HC908AS60 Advance Information, Motorola document order number MC68HC908AS60/D.
Question Answer
What steps take prolong life FLASH memory? FLASH memory finite program/erase data retention lifetime. However, specification shows minimum lifetime considering worst case conditions applied part. general, FLASH will last longer used temperatures much lower than maximum specified, such 25°C. program/erase endurance data retention this FLASH memory worst 125°C.
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Application Note Schematic
Question
program/erase/read FLASH maximum temperature limits continuously specified lifetime part? Yes.
Answer
Question Answer
What modes operation cause most noise? Program erase modes cause significant amount (electromagnetic interference) power supply noise high transient current demand charge pump. High accuracy (analog-to-digital) conversions possible while FLASH programming erasing.
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Schematic
Figure shows hardware schematic FLASH 2TS.
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Application Note
0.1uF
3333222222222 4210987654321
RESET SWITCH
0.1uF
VOLTAGE SWITCH
0.1uF
MC68HC908AS60
444555 7890121234567
RST* IRQ* DSXSS DSFCC AAC21
OUTGND
0.1uF
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9.8304MHz
Note: should applied times, except when programming FLASH block protect registers. When programming FLASH block protect registers, high voltage (VHi) must applied IRQ.
Body Electronics Systems Engineering
Title Programming Erasing FLASH Memory Size Document Number Release Level Date: October 1999 Sheet
Figure Hardware Schematic Programming Erasing FLASH MC68HC908AS60
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Application Note Assembly Source Code
Assembly Source Code
Sample assembly source code FLASH programming erasing included this section. routines Erase.mrt Program.mrt respective main routines erasing programming. Both disable initialize charge pump clocks. main routines also parameters required subroutines such FLASH_addr size erase block data bytes programmed. Erase.mrt erase 64-byte, 512-byte, 16-Kbyte, 32-Kbyte block FLASH. Program.mrt programs page (eight bytes) FLASH with data Figure Figure flowcharts Erase.mrt Program.mrt. subroutine EraseRoutine includes erasing flowchart called from Erase.mrt. calls subroutine WriteFLCR clear various bits FLCR register subroutine Delay generate required delays between steps. Prog8Bytes smart programming algorithm subroutine called from Program.mrt. also uses WriteFLCR Delay subroutines. Note that Prog8Bytes make multiple attempts value flsPulses) program page. flowcharts EraseRoutine, Prog8Bytes, WriteFLCR Delay Figure Figure Figure Figure respectively.
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NOTE:
should applied times, except when programming FLASH block protect registers. When programming FLASH block protect registers, flip switch such that high voltage applied IRQ.
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Freescale Semiconductor, Inc. Application Note
Erase.mrt Er_mrt.c
DISABLE
WRITE FDIV BITS FLCR REGISTERS CHARGE PUMP CLOCK
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LOAD FLASH ADDRESS WITHIN BLOCK ADDRESS RANGE ERASED INTO FLASH_addr
BITS FLCR ACCORDING SIZE BLOCK ERASE
CALL EraseRoutine ERASE BLOCK
Figure Erasing Main Routine Flowchart
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Application Note Assembly Source Code
Program.mrt Prog_mrt.c
DISABLE
WRITE FDIV BITS FLCR REGISTERS CHARGE PUMP CLOCK
Freescale Semiconductor, Inc.
LOAD SELECTED FLASH PAGE STARTING ADDRESS INTO FLASH_addr
LOAD DATA BUFFER WITH BYTES PROGRAM
CALL Prog8Bytes PROGRAM PAGE
ERROR OCCURS?
PROGRAMMING FAILURE
PROGRAMMING SUCCESS
Figure Programming Main Routine Flowchart
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Freescale Semiconductor, Inc. Application Note
EraseRoutine (Prog_er.srt Prog_er_srt.c)
MASK INTERRUPTS
STEP
CALL WriteFLCR ERASE
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STEP
READ FLASH BLOCK PROTECT REGISTERS
STEP
WRITE FLASH_addr WITH DATA VALUE STEP CALL Delay WAIT tKill
STEP
CALL WriteFLCR HVEN
STEP STEP CALL WriteFLCR CLEAR ERASE CALL Delay WAIT tErase STEP STEP CALL WriteFLCR CLEAR HVEN CALL Delay WAIT tHVD
CLEAR ENABLE INTERRUPTS
RETURN
Figure Subroutine EraseRoutine Flowchart
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Application Note Assembly Source Code
Prog8Bytes (Prog_er.srt Prog_er_srt.c)
MASK INTERRUPTS
STEP
CLEAR ATTEMPT COUNTER
Freescale Semiconductor, Inc.
STEP
CALL WriteFLCR
REPROGRAM SAME PAGE
STEP
READ FLASH BLOCK PROTECT REGISTERS
STEP
COPY DATA FROM BUFFER SELECTED FLASH PAGE STEP
CALL WriteFLCR MARGIN
STEP
CALL WriteFLCR HVEN STEP CALL Delay WAIT tVTP
STEP
CALL Delay WAIT tStep STEP CALL WriteFLCR CLEAR
STEP
CALL WriteFLCR CLEAR HVEN
STEP
CALL Delay WAIT tHVTV
Figure Subroutine Prog8Bytes Flowchart
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Freescale Semiconductor, Inc. Application Note
STEP
CALL Delay WAIT tHVD
STEPS EACH BYTE PROGRAMMED CORRECTLY STEP CALL WriteFLCR CLEAR MARGIN
Freescale Semiconductor, Inc.
STEP INCREMENT ATTEMPT COUNTER
CALL WriteFLCR CLEAR MARGIN STEP ATTEMPT COUNTER flsPulses?
CLEAR ENABLE INTERRUPTS
PROGRAMMING FAILURE
REPROGRAM SAME PAGE RETURN NOTE
Note: ACCUMULATOR VALUE RETURNED VALUE) INDICATES PROGRAMMING RESULT. ZERO VALUE PROGRAMMING SUCCESS NON-ZERO VALUE PROGRAMMING FAILURE
Figure Subroutine Prog8Bytes Flowchart (Continued)
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Application Note Assembly Source Code
WriteFLCR (Prog_er.srt Prog_er_srt.c)
FLASH_addr FLASH-1 ($8000)
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CLEAR FLCR1
CLEAR FLCR2
RETURN
Figure Subroutine WriteFLCR Flowchart
DELAY (Prog_er.srt Prog_er_srt.c)
WRITE VARIABLE AMOUNT TIME DEPENDING VALUE ACCUMULATOR FUNCTION PARAMETER)
RETURN
Figure Subroutine Delay Flowchart
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Freescale Semiconductor, Inc. Application Note Assembly Source Code
Erase FLASH Memory MC68HC908AS60 File Name: Erase.mrt Copyright Motorola 1999 Current Revision: Current Release Level: Current Revision Release Date: 9/6/99 Current Release Written Sparks Motorola Systems Engineering Austin, Assembled Under: CASM08 (P&E Micro Inc.) Ver.: 3.06 Project Folder Name: FLASH_2TS Part Family Software Routine Works With: HC08 Part Module(s) Software Routine Works With: fls32k_a01 Routine Size (Bytes): Stack Space Used (Bytes): Used (Bytes): Global Variables Used: FLASH_addr Subroutine Called: EraseRoutine, WriteFLCR Full Functional Description Routine Design: Erase.mrt main routine that demonstrates erase different size blocks FLASH memory MC68HC908AS60. Motorola reserves right make changes without further notice product herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product, circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters vary different applications. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure
Freescale Semiconductor, Inc.
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Application Note Assembly Source Code
Freescale Semiconductor, Inc.
Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such intended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola Motorola symbol registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer. ***** Include Files ***** NOLIST $INCLUDE "H908as60.frk" ;Equates registers bits MC68HC908AS60 ***** Program Specific Equates ***** eraseallrows. %00000000 ;Full array: Kbytes (A15) erasehalfrows. %00010000 ;One-half array: Kbytes (A15 A14) erase8rows. %00100000 ;Eight rows: bytes (A15-A9) erase1row. %00110000 ;Single row: bytes (A15-A6) ***** Variable Declarations ***** ram1 $INCLUDE "Prog_er.var" ;RAM variable definitions LIST ***** Erase Main Routine ***** This routine initializes 908AS60 before calling erasing routine, EraseRoutine. user plans incorporate EraseRoutine into his/her program, make sure FLASH control registers FLASH_addr initialized before calling EraseRoutine. After initialization, EraseRoutine called erase data block bytes, bytes, Kbytes bytes depending value control registers. FLASH_addr address within block that will erased. This program does verify that operation successful.
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Freescale Semiconductor, Inc. Application Note
Start: ldhx #$71,config-1 #$00 flcr1 flcr2 #$4001 ;Turn COP, leave ;Set frequency divide control bits flcr1 flcr2 appropriate charge pump clock ;Any address within block that will erased ;Set address erase block ;Set BLK1 BLK0 appropriate FLASH control register specify size block erase ;Erase block FLASH including specified address flash-1
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sthx
FLASH_addr #eraseallrows. WriteFLCR
EraseRoutine
***** Subroutine Body Includes Section ***** $INCLUDE "prog_er.srt" ;WriteFLCR Delay subroutines ***** Reset Vectors ***** reset Start Program Margin Read FLASH Memory MC68HC908AS60 File Name: Program.mrt Copyright Motorola 1999 Current Revision: Current Release Level: Current Revision Release Date: 9/6/99 Current Release Written Sparks Motorola Systems Engineering Austin, Assembled Under: CASM08 (P&E Micro Inc.) Ver.: 3.06 Project Folder Name: FLASH_2TS AN1827 More Information This Product, www.freescale.com MOTOROLA
Application Note Assembly Source Code
Freescale Semiconductor, Inc.
Part Family Software Routine Works With: HC08 Part Module(s) Software Routine Works With: fls32k_a01 Routine Size (Bytes): Stack Space Used (Bytes): Used (Bytes): Global Variables Used: FLASH_addr, data, attempt Subroutine Called: Prog8Bytes Full Functional Description Routine Design: Program.mrt main routine programming operation. demonstrates smart programming algorithm that minimizes amount time needed program page FLASH memory MC68HC908AS60. page consists eight consecutive bytes FLASH memory starting either address $xxx0 $xxx8. ***** Include Files ***** NOLIST $INCLUDE "H908as60.frk" ;Equates registers bits MC68HC908AS60 ram1 $INCLUDE "Prog_er.var" ;RAM variable definitions LIST ***** Program/Margin Read Main Routine ***** This routine initializes 908AS60 before calling programming routine, Prog8Bytes. user plans incorporate Prog8Bytes into his/her program, make sure FLASH control registers, FLASH_addr data buffer initialized before calling Prog8Bytes. After initialization, Prog8Bytes called program data bytes, page FLASH memory. programming successful, then program will jump branch always statement "No_Error." programming failed, then program will remain branch always statement "Load." flash-2 Start: ldhx sthx AN1827 MOTOROLA More Information This Product, www.freescale.com #$71,config-1 #$00 flcr1 flcr2 #$8000 FLASH_addr ;Turn COP, leave ;Set frequency divide control bits flcr1 appropriate charge pump clock ;Load FLASH_addr with address where bytes should start being
Freescale Semiconductor, Inc. Application Note
programmed. Must XXX0 XXX8 clrh decx cbeqa ;Fill buffer, data, with values program into FLASH. (ie. 01,02,03,04,05,06,07,08)
Load:
data-1,X Load Prog8Bytes #0,No_Error
;Program data bytes ;Check programming error occurred **Programming failed** Take appropriate action **Programming successful** program
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No_Error:
***** Subroutine Body Includes Section ***** $INCLUDE "prog_er.srt" ;Prog8Bytes, WriteFLCR Delay subroutines ***** Vectors ***** reset Start Programming Erasing FLASH Memory MC68HC908AS60 File Name: Prog_er.var Copyright Motorola 1999 Current Revision: Current Release Level: Current Revision Release Date: 9/6/99 Current Release Written Sparks Motorola Systems Engineering Austin, Assembled Under: CASM08 (P&E Micro Inc.) Ver.: 3.06 Project Folder Name: FLASH_2TS Part Family Software Routine Works With: HC08 Used (Bytes): AN1827 More Information This Product, www.freescale.com MOTOROLA
Application Note Assembly Source Code
Description: variable definitions Program.mrt Erase.mrt ***** Variables ***** FLASH_addr Address FLASH memory erase program data: ;Eight data bytes that will programmed attempt: ;Counts number attempts program page Program Margin Read Erase FLASH Memory Subroutines File Name: Prog_er.srt Copyright Motorola 1999 Current Revision: Current Release Level: Current Revision Release Date: 9/6/99 Current Release Written Sparks Motorola Systems Engineering Austin, Assembled Under: CASM08 (P&E Micro Inc.) Ver.: 3.06 Project Folder Name: FLASH_2TS Part Family Software Routine Works With: HC08 Part Module(s) Software Routine Works With: fls32k_a01 Module Size (Bytes): EraseRoutine Prog8Bytes WriteFLCR Delay Stack Space Used (Bytes): EraseRoutine Prog8Bytes WriteFLCR Delay Used (Bytes): EraseRoutine Prog8Bytes WriteFLCR Delay Global Variable(s) Used: EraseRoutine FLASH_addr Prog8Bytes FLASH_addr, data, attempt WriteFLCR FLASH_addr Delay None Submodule(s) Called: EraseRoutine WriteFLCR, Delay Prog8Bytes WriteFLCR, Delay AN1827 MOTOROLA More Information This Product, www.freescale.com
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Freescale Semiconductor, Inc. Application Note
WriteFLCR None Delay None Calling Sequence: EraseRoutine, Prog8Byte WriteFLCR, Delay Entry Label: EraseRoutine, Prog8Bytes, WriteFLCR Delay Entry Conditions: EraseRoutine bytes address defined FLASH_addr Prog8Bytes bytes address defined FLASH_addr programming bytes located variables data WriteFLCR bytes address defined FLASH_addr FLCR (FLASH Control Register) definition passed accumulator Delay Delay variable passed accumulator Number Exit Points: Exit Label: EraseRoutine Erase990 Prog8Bytes Prog990 WriteFLCR FLCR990 Delay Delay990 Exit Conditions: EraseRoutine None Prog8Bytes pass/fail result accumulator WriteFLCR None Delay None Full Functional Description Subroutine: Prog_er.srt consists primary subroutines called EraseRoutine Prog8Bytes. These demonstrate flash erasing programming algorithms, respectively. routines also call other subroutines WriteFLCR Delay. ***** FLASH Delay Equates ***** Each delay time related FLASH program erase operations calculated with speed 2.4576 MHz. tERASE: ;FLASH block/bulk erase time (~102 tKILL: ;FLASH high-voltage kill time (~209 tHVD: ;FLASH return read time (~66 tSTEP: ;FLASH page program step size tHVTV: ;FLASH HVEN MARGIN high AN1827 More Information This Product, www.freescale.com MOTOROLA
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Application Note Assembly Source Code
Freescale Semiconductor, Inc.
time (~66 ;FLASH MARGIN high time (~168 flsPULSES: ;FLASH maximum page program pulses (100 pulses) ***** Erase Block FLASH Memory Subroutine ***** This routine erases block FLASH size specified FLASH Control Registers location specified FLASH_addr. FLASH_addr address within block erased. routine follows basic step sequence FLASH erase operation. Initializations required: charge pump clock block erase size FLCR1 FLCR2; FLASH_addr Values returned: none EraseRoutine: ;Disable interrupts ldhx FLASH_addr ;Load starting address block erased tVTP: #erase. WriteFLCR flbpr1 flbpr2 ;Step ERASE
;Step Read from block protect registers ;Step Write FLASH address within block address range erased with data value ;(indexed, offset=H:X+$00) ;Step HVEN
pshx Again: dbnzx pulx AN1827 MOTOROLA
#hven. WriteFLCR #terase #$14 Delay Again
;Step Wait time tERASE
#hven. WriteFLCR #tkill Delay
;Step Clear HVEN
;Step Wait time tKILL
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Freescale Semiconductor, Inc. Application Note
#erase. WriteFLCR #thvd DELAY
;Step Clear ERASE
;Step Wait time tHVD
;Enable interrupts
Erase990: ***** Program/Margin Read Bytes FLASH Memory Subroutine ***** This routine programs bytes data from data buffer FLASH memory starting FLASH_addr. programming done ascending order, data[0] FLASH_addr[0], data[1] FLASH_addr[1], etc. routine structured into loop smart programming that minimum amount high voltage applied FLASH. Each time through loop called "pulse." Each pulse consists steps shown application note, with programming time, tSTEP, equal approximately bytes program correctly approximately time period, then routine exits returns control calling program. bytes program correctly, another attempt(pulse) made. This continues maximum number pulses (flsPULSES). bytes programmed successfully after maximum number pulses, then programming error flag incremented, routine exited error value (any non-zero value) returned accumulator. Initializations required: charge pump clock FLCR1 FLCR2; FLASH_addr set; data buffer filled Values returned: Program Success/Error Flag Prog8Bytes: interrupts allowed during programming NextAttempt: ldhx attempt ;Step Clear attempt counter
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FLASH_addr
;Load address page programmed register ;Step
#pgm. WriteFLCR
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Application Note Assembly Source Code
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flbpr1 flbpr2 data data+1 data+2 data+3 data+4 data+5 data+6 data+7 #hven. WriteFLCR #tSTEP Delay #hven. WriteFLCR #tHVTV Delay #margin. WriteFLCR #tVTP Delay #pgm. WriteFLCR #tHVD Delay data Repeat data+1 Repeat
;Step Read from block protect registers ;Step Copy bytes data from buffer appropriate FLASH locations
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;Step HVEN
;Step Wait time tSTEP
;Step Clear HVEN
;Step Wait time tHVTV
;Step MARGIN
;Step Wait time tVTP
;Step Clear
;Step Wait time tHVD
;Step Check correct data programmed FLASH page. not, jump Repeat another attempt. jump Complete.
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Freescale Semiconductor, Inc. Application Note
Repeat: cbeqa #margin. WriteFLCR attempt attempt #flsPULSES,Return NextAttempt Program Failure ;Step Clear MARGIN ;Step Increment attempt counter data+2 Repeat data+3 Repeat data+4 Repeat data+5 Repeat data+6 Repeat data+7 Repeat Complete
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;Step attempt less than flsPULSES, back NextAttempt (Step Program Success ;Clear MARGIN
Complete: clra Return:
#margin. WriteFLCR
;Clear interrupt mask return programming unsuccessful flsPULSES, accumulator non-zero value
Prog990:
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Application Note Assembly Source Code
Freescale Semiconductor, Inc.
***** Write FLASH Control Register ***** This routine determines whether flcr1 flcr2 should written based FLASH address specified FLASH_addr. Initializations required: FLASH_addr Values returned: None WriteFLCR: cphx #flash-1 FLASH_addr FLASH-1 array, Array1 jump Array1 Array1: flcr1 ;Write flcr1 register flcr1 FLCR990: ***** Delay Routine ***** This routine delays variable amount time depending value passed into routine accumulator (A). Delay Freq Initializations required: delay variable Values returned: None Delay: pshx cyc., Store lower address FLASH_addr stack Loop: #$0F cyc., Initialize inner loop dbnzx cyc., cycles dbnza Loop cyc., Decrement value passed accumulator repeat necessary pulx cyc., Restore lower address Delay990: cyc., Return flcr2 flcr2 FLCR990 ;Write flcr2 register
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Freescale Semiconductor, Inc. Application Note Source Code
sample assembly source code contained previous section written language this section. main routines called Er_mrt.c Prog_mrt.c. same flowcharts apply.
Erase FLASH Memory MC68HC908AS60 File Name: Er_mrt.c Copyright Motorola 1999 Current Revision: Current Release Level: Current Revision Release Date: 10/02/99 Current Release Written Adeela Gill Motorola Systems Engineering Austin, Texas Compiled Under: HiCross HC08 (HiWare) Ver.: 5.0.5 Project Folder Name: FLASH_2TS Part Family Software Routine Works With: HC08 Part Module(s) Software Routine Works With: fls32k_a01 Routine Size (Bytes): Stack Space Used (Bytes): Used (Bytes): Global Variables Used: FLASH_addr Subroutine(s) Called: EraseRoutine, WriteFLCR Full Functional Description Routine Design: Er_main.c main routine that demonstrates erase different size blocks FLASH memory MC68HC908AS60. Motorola reserves right make changes without further notice product herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product, circuit, specifically disclaims liability, including without limitation consequential
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AN1827 More Information This Product, www.freescale.com MOTOROLA
Application Note Source Code
incidental damages. "Typical" parameters vary different applications. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such intended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola Motorola symbol registered trademarks Motorola, Inc. /***** Include Files *****/ #include <as60_flash_frk.c> Equates registers bits HC908AS60 that used #include <prog_er_var.c> variable definitions /***** Program-Specific Defines *****/ #define eraseallrows 0x00 full array erase: Kbytes cared addresses #define erasehalfrows 0x10 one-half array erase: Kbytes cared addresses A15-A14 #define erase8rows 0x20 eight erase: Bytes cared addresses A15-A9 #define erase1row 0x30 single erase: Bytes cared addresses A15-A6 /***** Function Definitions *****/ extern void EraseRoutine (void); extern void writeFLCR (unsigned char); /***** Erase Main Routine *****/ This routine initializes 908AS60 before calling erasing routine, EraseRoutine. user plans incorporate EraseRoutine into his/her program, make sure FLASH control registers variable FLASH_addr initialized before calling EraseRoutine. After initialization, EraseRoutine called erase data AN1827 MOTOROLA More Information This Product, www.freescale.com
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Freescale Semiconductor, Inc. Application Note
block bytes, bytes, Kbytes 32bytes depending value control registers. FLASH_addr address within block that will erased. This program does verify that operation successful. void main CONFIG1 0x71; /*Turn COP, leave FLCR1 0x00; FLCR2 0x00; /*Set frequency divide control bits flcr1 flcr2 appropriate charge pump clock /*Set address erase block. This address within block that will erased /*Set BLK1 BLK0 appropriate FLASH control register specify size block erase /*Erase block FLASH including specified address
Freescale Semiconductor, Inc.
FLASH_addr=(unsigned char *)0x4001;
writeFLCR(eraseallrows);
EraseRoutine while (1);
/**** Subroutine Body Includes ****/ #include <prog_er_srt.c> /*Prog8Bytes, WriteFLCR Delay Subroutines Program Margin Read FLASH Memory MC68HC908AS60 File Name: Prog_mrt.c Copyright Motorola 1999 Current Revision: Current Release Level: Current Revision Release Date: 10/02/99 Current Release Written Adeela Gill Motorola Systems Engineering Austin, Texas Compiled Under: HiCross HC08 (HiWare) Ver.: 5.0.5 Project Folder Name: FLASH_2TS Part Family Software Routine Works With: HC08 Part Module(s) Software Routine Works With: fls32k_a01 AN1827 More Information This Product, www.freescale.com MOTOROLA
Application Note Source Code
Routine Size (Bytes): Stack Space Used (Bytes): Used (Bytes): Global Variables Used: FLASH_addr, data, attempt Subroutine(s) Called: Prog8Bytes Full Functional Description Routine Design: Prog_mrt.c main routine programming operation. demonstrates smart programming algorithm that minimizes amount time needed program page FLASH memory MC68HC908AS60. page consists eight consecutive bytes FLASH memory starting either address $xxx0 $xxx8. /***** Include Files *****/ #include <as60_flash_frk.c> Equates registers bits HC908AS60 that used #include <prog_er_var.c> variable definitions /***** Function Definitions *****/ extern void writeFLCR (unsigned char); extern unsigned char Prog8Bytes (void); /***** Program/Margin Read Main Routine *****/ This routine initializes 908AS60 before calling programming routine, Prog8Bytes. user plans incorporate Prog8Bytes into his/her program, make sure FLASH control registers, FLASH_addr data buffer initialized before calling Prog8Bytes. After initialization, Prog8Bytes called program data bytes, page FLASH memory. programming successful, then program will jump while(1) statement "if" expression. programming failed, then program will remain while(1) statement "else" expression. void main unsigned char count; Variable count down bits unsigned char pgmsuccess; Return value from Prog8Bytes CONFIG1 0x71; /*Turn COP, leave /*Set frequency divide control bits flcr1 appropriate charge pump clock
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FLCR1 0x00; FLCR2 0x00;
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Freescale Semiconductor, Inc. Application Note
FLASH_addr (unsigned char *)0x8000; /*Load FLASH_addr with address where bytes should start being programmed. Must XXX0 XXX8 (count count count-) data[count-1]=count; Fill array, data, with values program into FLASH. (ie. 01,02,03,04,05,06,07,08) pgmsuccess=Prog8Bytes(); Program data bytes (pgmsuccess!=0) Check programming error occurred Programming failed Take appropriate action Programming successful program
Freescale Semiconductor, Inc.
while (1);
else while (1);
/***** Subroutine Body Includes Section *****/ #include <prog_er_srt.c> Prog8Bytes, WriteFLCR Delay Subroutines HC908AS60 FLASH Framework File Name: as60_flash_frk.c Copyright Motorola 1999 Current Revision: Current Release Level: Current Revision Release Date: 10/02/99 Current Release Written Adeela Gill Motorola Systems Engineering Austin, Texas Compiled Under: HiCross HC08 (HiWare) Ver.: 5.0.5 Project Folder Name: FLASH_2TS Part Family Software Routine Works With: HC08 Part Module(s) Software Routine Works With: fls32k_a01 Framework Description: This framework generated using MC68HC908AT60 General Release Specification reference. AN1827 More Information This Product, www.freescale.com MOTOROLA
Application Note Source Code
/***** Register Equates *****/ #define CONFIG1 (*((volatile unsigned char *)0x001F)) Configuration Register #define FLCR1 #define FLCR2 (*((volatile unsigned char *)0xFE0B)) FLASH Control Register (*((volatile unsigned char *)0xFE11)) FLASH Control Register (*((volatile unsigned char *)0xFF80)) FLASH Block Protect Register (*((volatile unsigned char *)0xFF81)) FLASH Block Protect Register
#define FLBPR1
Freescale Semiconductor, Inc.
#define FLBPR2
#define FLASH1
(*((volatile unsigned char *)0x8000)) Start Address FLASH Array #define FLASH2 (*((volatile unsigned char *)0x0450)) Start Address FLASH Array /***** Equates *****/ #define HVEN 0x08 High-Voltage Enable #define MARGIN 0x04 Margin Read Control #define ERASE 0x02 Erase Control #define 0x01 Program Control Programming Erasing FLASH Memory MC68HC908AS60 File Name: Prog_er_var.c Copyright Motorola 1999 Current Revision: Current Release Level: Current Revision Release Date: 10/02/99 Current Release Written Adeela Gill Motorola Systems Engineering Austin, Texas Compiled Under: HiCross HC08 (HiWare) Ver.: 5.0.5 Project Folder Name: FLASH_2TS Part Family Software Routine Works With: HC08 Part Module(s) Software Routine Works With: fls32k_a01 Used (Bytes): Description: AN1827 MOTOROLA More Information This Product, www.freescale.com
Freescale Semiconductor, Inc. Application Note
variable definitions Prog_mrt.c Er_main.c /**** Variables ****/ unsigned char FLASH_addr; address FLASH memory erase program unsigned char data[8]; Eight data bytes that will programmed unsigned char attempt; Counts number attempts program page Program Margin Read Erase FLASH Memory Subroutines File Name: Prog_er_srt.c Copyright Motorola 1999 Current Revision: Current Release Level: Current Revision Release Date: 10/02/99 Current Release Written Adeela Gill Motorola Systems Engineering Austin, Texas Compiled Under: HiCross HC08 (HiWare) Ver.: 5.0.5 Project Folder Name: FLASH_2TS Part Family Software Routine Works With: HC08 Part Module(s) Software Routine Works With: fls32k_a01 Routine Sizes (Bytes): composite with called routines: Prog8Bytes bytes EraseRoutine bytes Delay bytes WriteFLCR bytes Stack Space Used (Bytes): composite with called routines: Prog8Bytes bytes EraseRoutine bytes Delay bytes WriteFLCR bytes Used (Bytes): composite with called routines: Prog8Bytes bytes EraseRoutine bytes Delay bytes WriteFLCR bytes Global Variable(s) Used: Prog8Bytes FLASH_addr, data, attempt AN1827 More Information This Product, www.freescale.com MOTOROLA
Freescale Semiconductor, Inc.
Application Note Source Code
EraseRoutine Delay WriteFLCR Submodule(s) Called: Prog8Bytes EraseRoutine Delay WriteFLCR
FLASH_addr None FLASH_addr WriteFLCR, Delay WriteFLCR, Delay None None
Calling Sequence:
EraseRoutine int=Prog8Bytes WriteFLCR (unsigned char) Delay (unsigned char) void EraseRoutine(), unsigned char Prog8Bytes() void WriteFLCR (unsigned char) void Delay (unsigned char) EraseRoutine byte address defined FLASH_addr Prog8Bytes bytes address defined FLASH_addr programming bytes located variable data WriteFLCR bytes address defined FLASH_addr byte FLCR definition passed Delay byte delay value passed EraseRoutine Prog8Bytes WriteFLCR Delay EraseRoutine Prog8Bytes WriteFLCR Delay
Entry Label:
Entry Conditions:
Number Exit Points: Exit Label:
Erase990 Prog990 FLCR990 Delay990 None pass/fail result returned None None
Exit Conditions:
Full Functional Description Subroutine: Prog_er_srt.c consists primary subroutines called EraseRoutine Prog8Bytes. These demonstrate flash erasing programming algorithms, respectively. routines also call other subroutines WriteFLCR Delay.
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Freescale Semiconductor, Inc. Application Note
/***** FLASH Delay Equates *****/ Each delay time related FLASH program erase operations calculated with speed 2.4576 MHz. #define tERASE 0xF0 FLASH block/bulk erase time (~101 #define tKILL 0x0A FLASH high-voltage kill time (~210 #define tHVD 0x02 FLASH return read time (~51 #define tSTEP 0x32 FLASH page program step size #define tHVTV 0x02 FLASH HVEN MARGIN high time (~51 #define tVTP 0x07 FLASH MARGIN high time (~151 #define flsPULSES 0x64 FLASH maximum page program pulses (100 pulses) /***** Necessary Assembly-Level Commands Defines *****/ #define EnableInterrupts {asm CLI;} #define DisableInterrupts {asm SEI;} /***** Function Initializations *****/ void EraseRoutine (void); unsigned char Prog8Bytes (void); void writeFLCR (unsigned char); void Delay (unsigned char); /**** Erase Block FLASH Memory Subroutine *****/ This routine erases block FLASH size specified FLASH Control Registers location specified FLASH_addr. FLASH_addr address within block erased. routine follows basic step sequence FLASH erase operation. Initializations required: charge pump clock block erase size FLCR1 FLCR2; FLASH_addr Values returned: none void EraseRoutine unsigned char Blk_Protect1; local variables unsigned char Blk_Protect2; unsigned char loop;
Freescale Semiconductor, Inc.
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Application Note Source Code
DisableInterrupts; writeFLCR (ERASE); Blk_Protect1 FLBPR1; Blk_Protect2 FLBPR2; *FLASH_addr 0xFF;
Disable interrupts Step ERASE Step Read from block protect registers
Step Write FLASH address within block address range with data value Step HVEN
writeFLCR (HVEN);
Freescale Semiconductor, Inc.
(loop=0x15; loop !=0; loop-) Delay (tERASE); writeFLCR (HVEN); Delay (tKILL); writeFLCR (ERASE); Delay (tHVD); EnableInterrupts;
Step Wait time tERASE Step Clear HVEN Step Wait time tKILL Step Clear ERASE Step Wait time tHVD Enable Interrupts
Erase990: return; /**** Program/Margin Read Bytes FLASH Memory Subroutine *****/ This routine programs bytes data from data array FLASH memory starting FLASH_addr. programming done ascending order, data[0] FLASH_addr[0], data[1] FLASH_addr[1], etc. routine structured into loop smart programming that minimum amount high voltage applied FLASH. Each time through loop called "pulse". Each pulse consists steps shown application note, with programming time, tSTEP, equal approximately bytes program correctly approximately time period, then routine exits returns control calling program. bytes program correctly, another attempt(pulse) made. This continues maximum number pulses (flsPULSES). bytes programmed successfully after maximum number pulses, then programming error flag incremented, routine exited error value (any non-zero value) returned.
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Freescale Semiconductor, Inc. Application Note
Initializations required: charge pump clock FLCR1 FLCR2; FLASH_addr set; data buffer filled Values returned: Program Success/Error Flag unsigned char Prog8Bytes unsigned char Blk_Protect1; local variables unsigned char Blk_Protect2; unsigned char byte,status; DisableInterrupts; interrupts allowed during programming Step Clear attempt counter Repeat Loop writeFLCR (PGM); Blk_Protect1 FLBPR1; Blk_Protect2 FLBPR2; Step Step Read from block protect registers Step Copy bytes data from buffer appropriate FLASH locations (byte=0;byte<8;byte++) *(FLASH_addr+byte)=data[byte]; writeFLCR (HVEN); Delay (tSTEP); writeFLCR (HVEN); Delay (tHVTV); status=0; writeFLCR (MARGIN); Delay (tVTP); writeFLCR (PGM); Delay (tHVD); Step MARGIN Step Wait time tVTP Step Clear Step Wait time tHVD Step HVEN Step Wait time tSTEP Step Clear HVEN Step Wait time tHVTV
Freescale Semiconductor, Inc.
attempt=0;
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Application Note Source Code
(byte=0; byte<8; byte++) (*(FLASH_addr+byte) data[byte]) status++; Step Check correct data programmed FLASH page. not, proceed with bracketed expressions. skip next statement. (status Program Failure Step Clear MARGIN
Freescale Semiconductor, Inc.
writeFLCR (MARGIN); attempt++; (status writeFLCR (MARGIN);
Step Increment attempt counter
Program Success Clear MARGIN
while ((status!=8) (attempt<flsPULSES)); Step attempt less than flsPULSES, back step EnableInterrupts; Prog990: return (8-status); Clear interrupt mask
programming unsuccessful flsPULSES, non-zero value returned
/**** Write FLASH Control Register *****/ This routine determines whether flcr1 flcr2 should written based FLASH address specified FLASH_addr. Initializations required: FLASH_addr Values returned: None void writeFLCR (unsigned char FLASH-1=$8000, FLASH-2=$0450 (FLASH_addr &FLASH1) /*If FLASH_addr FLASH-1 array FLCR1 FLCR1 write FLCR1 Register else FLCR2 FLCR2 FLCR990: return; AN1827 MOTOROLA More Information This Product, www.freescale.com else write FLCR2 Register
Freescale Semiconductor, Inc. Application Note
/**** Delay Routine *****/ This routine delays variable amount time depending value passed into routine variable Delay time (11+72+11)*A Freq This equation includes cycles from calling delay routine until hitting next line code. This allows user accurately predict delay between steps code. Initializations required: Pass variable Delay Value Values returned: None void Delay (unsigned char unsigned char count; while (A!=0) (count=0x03;count!=0;count-); Delay990: return;
Freescale Semiconductor, Inc.
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reach USA/EUROPE/Locations Listed: Motorola Literature Distribution, P.O. 5405, Denver, Colorado 80217, 1-303-675-2140 1-800-441-2447. Customer Focus Center, 1-800-521-6274 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku, Tokyo, 106-8573 Japan. 81-3-3440-8573 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, King Street, Industrial Estate, N.T., Hong Kong. 852-26668334 MfaxTM, Motorola Back System: RMFAX0@email.sps.mot.com; http://sps.motorola.com/mfax/; TOUCHTONE, 1-602-244-6609; Canada ONLY, 1-800-774-1848 HOME PAGE: http://motorola.com/sps/ Mfax trademark Motorola, Inc.
Motorola, Inc., 1999
AN1827/D More Information This Product, www.freescale.com

AN1827 Freescale Semiconductor, Inc. Programming Erasing FLA

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