AN1816 Freescale Semiconductor, Inc. USING HC912B32 IMPLEMEN

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AN1816 Freescale Semiconductor, Inc. USING HC912B32 IMPLEMEN

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Freescale Semiconductor, Inc.
USING HC912B32 IMPLEMENT DISTRIBUTED SYSTEMS INTERFACE (DSI) PROTOCOL
Tracy McHenry August 1999
Introduction
System design requirements continually changing systems become increasingly complex. conventional systems where sensors actuators connected directly microcontroller (MCU), number pins available limits system expansion. result, extra costs incurred another required hardware redesigned accommodate higher count MCU. alternative approach move distributed architecture. This option allows master interconnect many remote sensors actuators. Distributed Systems Interface (DSI) such master/slave system, with central control module being master remote sensors actuators acting slave devices. feature architecture that sensors actuators connected same bus. Another benefit that promotes standard components interfaces which enables maximum re-use accelerates time market. This great advantage systems designers therefore able develop flexible system solutions. initially developed automotive market although equally suited other applications that require distributed sensors and/or actuators. Examples possible applications include occupant safety systems, body networks, building industrial controls. This application note provides overview describes hardware software design demonstrator system.
Motorola, Inc., 1999
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Application Note Distributed Systems Interface (DSI) Overview
Distributed Systems Interface (DSI) designed interconnect multiple remote sensor actuator devices central control module. provides simultaneous support sensors actuators using 2-wire that provides both power communications. This results savings wiring costs connector complexity. Unlike conventional systems, size connector control module does need grow accommodate every sensor actuator. sensor actuator added without reconfiguring system design. DSI, therefore, enables development easily expandible systems. communication simple robust. Signals superimposed onto power line and, communication between master slave nodes bi-directional, makes efficient bandwidth. Also, ensure message integrity, each message contains 4-bit Cyclic Redundancy Check (CRC). Slave nodes attached daisy chain parallel connections. Each slave device unique address. daisy chain connection allows central module establish node addresses power-up. parallel configuration used devices that have pre-programmed fixed addresses. possible have combination with maximum number nodes being master slaves).
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Signalling
uses mediums signalling voltage mode messages from master slaves, current mode responses from slaves. voltage mode signal bits sent ratio shown Figure Voltage Mode Encoding.
Voltage Mode Encoding
Logic
Logic
Logic
Logic
Figure Voltage Mode Encoding
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Distributed Systems Interface (DSI) Overview
protocol been designed such that first third voltage mode signal always last third always high. central third defines signal value. logic zero master produces signal that time high final 1/3. logic signal time high time. Each slave built-in oscillator. This feature message protocol created high immunity temporal distortion. Consequently, each slave simpler cheaper design while still able capture messages accurately. added benefit that allows range operating frequencies.
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Voltage Levels
voltage mode signalling uses tri-level shown Figure Tri-level bus.
Idle High Threshold Signal High Threshold Signal First ("0") Word Start Word Second ("1") Start Next Word
Figure Tri-level provides power slave nodes well supporting bi-directional communication between slave nodes master. When idle voltage, which ranges from volts, supplies power slave nodes. high threshold level (typically threshold level (typically play significant part message transmission. start word occurs when voltage drops from idle voltage below high threshold level then below threshold level. Data values determined ratio time spent above below threshold. voltage rising above high threshold level signals word. Current Mode Encoding Slave responses commands returned modulating amount current sunk device. This measured each determine `zero' `one' response. When responding with logic one,
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Freescale Semiconductor, Inc. Application Note
slave draws additional current from source during time. Conversely, extra current drawn when responding with logic zero. Figure Current Waveform shows representation current waveform referenced voltage waveform.
Voltage (from Master) Logic Logic Logic Logic
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Current (from Slave) Logic Logic Logic Logic
Figure Current Waveform
Message Format
messages composed individual words separated minimum frame delay. Transfers full duplex, that command messages from master occur same time responses from slaves. This important feature doubles effective signal bandwidth. Slave responses commands occur during next command message. This allows slaves time decode command, upon then respond master. minimum frame delay present allow recharge energy storage devices slaves. This necessary because slave receives power from signal line. Message encoding depends direction transfer. Command control messages sent from master slave. Response messages sent from slaves master. both cases there long word short word messages. long word consists 16-bits information followed 4-bit cyclic redundancy check (CRC). short word composed 8-bits information followed 4-bit CRC.
Message Encoding
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Distributed Systems Interface (DSI) Overview
Command Control Messages
long word command control message encoding shown Figure Long Word Command Control Message.
DATA
ADDRESS
COMMAND
Figure Long Word Command Control Message message consists bits data, encoded 4-bit address intended slave device, 4-bit encoded command, calculated 4-bit CRC. short word command control message encoding shown Figure Short Word Command Control Message.
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ADDRESS
COMMAND
Figure Short Word Command Control Message message consists encoded 4-bit address intended slave device, 4-bit encoded command, calculated 4-bit CRC. Response Messages long word response message sent from slave master response long word command control message slave's address. response transmitted during next command control message. long word response message encoding shown Figure Long Word Response Message.
DATA BYTE
DATA BYTE
Figure Long Word Response Message message consists 8-bit data bytes calculated 4-bit short word response message sent from slave master response short word command control message slave's address. response transmitted during next command
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Freescale Semiconductor, Inc. Application Note
control message. short word response message encoding shown Figure Short Word Response Message.
DATA
Figure Short Word Response Message message consists 8-bit data byte calculated 4-bit CRC.
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Long words always sent response long word commands short words always sent response short word commands. When word format changes between successive commands, first response sent during format will invalid since will have proper number bits.
Error Checking
master slaves calculate information portion their received messages. message valid only calculated matches sent part message. error master when receives invalid message. slaves discard ignore invalid received messages addition respond them. Each slave device must given unique 4-bit address (from (0001) (1111)) assigned four groups. Address (0000) used address slave nodes once. After system power master must address daisy chain slave devices with programmable addresses before network communications commence. These devices have switch power/signal line. power programmable device switches open only close once initialisation message been received. With first switch open, only goes first slave. When master sends slave initialisation command, first slave device stores address information closes switch. second daisy chain slave connected network. When master initialises second slave's address, first device responds with initialisation response message. response message echoes programming information back master that knows that address successfully established. Each slave sends initialisation response message only once after receiving program address command message.
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Slave Device Addressing
Programmable Devices
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HARDWARE DESIGN
advantage having programmable devices present system that they replaced and/or system reconfigured adding nodes system will automatically reconfigure itself next power Pre-programmed Devices Slaves with pre-programmed addresses require switch. power-up stored pre-programmed address becomes slave address. However, pre-programmed devices must still receive Initialisation Command reply with Initialisation Response before responding other commands.
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HARDWARE DESIGN
Master Board
HC912B32
MC68HC55 Peripheral
DSI0F SCLK DSI1F DSI0S
MC33790 Transceiver
CH.0
DSI0R
DSI0O TWO-WIRE Signal DSI1O Return
(master)
MOSI MISO
CH.1
DSI1S DSI1R
Slav
Figure Level System Connections Several used development system Master board HC912B32 MC68HC55 Peripheral MC33790 Transceiver Slave board evaluation slave device,
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Freescale Semiconductor, Inc. Application Note Master Board
Figure Level System Connections shows connected together. should noted that diagram shows daisy chain connected slave slave nodes also connected onto parallel. parallel configuration used slave nodes that have pre-programmed addresses. HC912B32 such that acts master communication from HC912B32 MC68HC55 SPI. MC33790, physical layer interface bus, sends commands receives responses from slave devices. Software required control system programmed into HC912B32's FLASH memory. also bytes EEPROM RAM. used provide MC68HC55 with system clock. such that channel output port (PP0) connected SCLK MC68HC55 Peripheral. HC912B32's board element communication protocol follows. MOSI, MISO SCLK pins HC912B32 connected MC68HC55's pins respectively. Port (PS7) connected MC68HC55. should then defined software general-purpose drive MC68HC55. active signal that controlled HC912B32. When driven indicates start message transmission from HC912B32 MC68HC55 turn MC33790 then slave nodes. This start what termed burst transfer (refer section: `Initialisation SPI' Software Design section this Application Note). burst transfer signalled HC912B32 pulling high. Commands sent responses received from slave nodes during burst transfer. data written data register transferred into MC68HC55's data register, which transmits message slave nodes MC33790 Transceiver. MC68HC55 protocol controller system controls digital functions DSI. contains independent channels, each capable interfacing slave nodes. MC68HC55 Peripheral uses pins transmit message MC33790 Transceiver. DSIxS (signal) MC68HC55 transmits data output signal MC33790. Data bits this signal line pulse length encoded voltage levels. logic zero starts with falling edge DSIxS thirds time then high third time. logic starts with falling edge DSIxS third time then high thirds time. DSIxF (frame) output idles high driven during each transfer frame. DSIxR data input signal from MC33790. MC68HC55 samples CMOS level this time. This level corresponds current sensed MC33790.
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HARDWARE DESIGN
MC33790 Transceiver analogue SmartMOSdevice, which serves physical interface two-wire bus. uses combination pulse length encoded voltage levels transmit data slave nodes current return signals receive data same time.
DSIxF (frame) from MC68HC55
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DSIxS (signal) from MC68HC55
Idle Idle High
DSIxO from MC33790
Figure MC68HC55 frame output signals with respect MC33790 DSIx0 signal When MC33790 receives data transmission slave nodes from MC68HC55, transmitter circuit converts volt inputs from MC68HC55's DSIxF (frame) DSIxS (signal) voltage level output DSIxO which connects BUS_IN first slave node. value output DSIxO MC33790 depends values DSIxF DSIxS shown Table DSIxO Truth Table. also Figure MC68HC55 frame output signals with respect MC33790 DSIx0 signal.
DSIxF
DSIxS
DSIxR Return Data Return Data
DSIxO (1.5V) High (4.5V) High Impedance Idle
Table DSIxO Truth Table When MC33790 receiving data from slave nodes, samples current responses rising edge final third time. current response then compared against reference point, which determines whether high been returned.
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Schematics Layout Considerations Master Board
0.1µF DSID Ch.0 Data
0.1µF
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PP0/PW0 PS6/SCK PS5/MOSI
SCLK
DSI0F DSI0S DSI0R n.c.
DSIP DSI0F DSI0S DSI0R DSI1F DSI1S DSI1R n.c. CPCAP Gnd0 DSI0O Vsup DSI1O Gnd1 n.c. n.c.
PINS
PS7/SS
RESET DSI1F DSI1S DSI1R
PE1/IRQ
Ch.1 Data
0.1µF
n.c. Power 10µF
Figure Master Board Schematic Figure Master Board Schematic shows schematic master board. board based existing HC912B32 Evaluation Board (EVB) with addition required circuitry. HC912B32 circuitry allows board used evaluate prototype hardware software. When laying circuitry master board, traces MC33790 were made wide possible deal with presence higher voltage (the maximum idle voltage 25V). components were positioned where clock trace lengths could kept minimum. 0.1µF capacitors were used filter supply voltage decouple power supplies MC68HC55 MC33790. These capacitors were placed close possible.
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DSI1
DSI0
PS4/MISO
HARDWARE DESIGN
Slave Board
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slave board discussed this application note that designed part evaluation tool kit. contains Evaluation Module (BEM) which slave interface evaluation device. provides bi-directional communications from bus. slave board contains board potentiometer which used vary voltage input This voltage converted digital signal that then transmitted over bus. Alternatively, accelerometer other analogue output device could connected using wire wrap area slave board jumper setting changed such that output accelerometer input Multiple slave nodes attached daisy chaining them together.
Schematics Layout Considerations Slave Board
DESCRIPTION
SLAVE BOARD
signals from BUS_IN BUS_OUT CON3WAY DIODE
DATE
TEST POINT VREG SIGIN BUSIN BUSOUT TEST POINT TEST POINT DIODE 0.1uF SIG_IN BUS_IN BUS_GND BUS_GND AGND AGND TEST POINT BUS_OUT VREG FILT_CAP 1.0uF 4.7uF
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COMPUTER GENERATED DRAWING REVISE MANUALLY
Title SLAVE BOARD Size Document Number SLAVE.SCH Date: August 1999 Sheet
Figure Slave Board Schematic
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Freescale Semiconductor, Inc. Application Note
Figure Slave Board Schematic shows schematic slave board. benefit architecture that slave board requires only additional components. Zener diodes used protect against damage signals BusIn BusOut. (filt_cap) supplies power during signalling. When laying slave board, pads capacitor, were enlarged that they could accommodate various values capacitor from 4.7µF depending what required evaluation system. slave node described this Application Note capacitor selected being capable storing enough charge power during signalling. components were positioned where signal trace lengths could kept minimum signal traces were made wide possible. Also, analogue digital grounds were connected together close possible.
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SOFTWARE DESIGN
initialisation software divided into sections initialisation SPI, initialisation MC68HC55 peripheral's registers initialisation slave nodes.
Initialisation
HC912B32 provides system clock (SCLK) MC68HC55 Peripheral. system software must initialise that supplies clock signal MC68HC55 Peripheral with appropriate duty cycle period. example possible source code that used perform this set-up shown function InitPWM Appendix Source Code. registers, this example, generate clock signal with duty cycle period 3.5µs (frequency 285kHz). such that slave select (SS) HC912B32 (connected chip select (CS) MC68HC55 Peripheral) configured general purpose allowing software control This necessary Burst Transfers, thus enabling HC912B32 communicate with slave nodes MC68HC55 MC33790. Figure Burst Transfer Example shows example burst transfer.
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SOFTWARE DESIGN
COMMAND (000) WRITE DSI0H (000) WRITE DSI0L (001)
ZEROS transfer after reset)
READ DSI0H (000)
READ DSI0L (001)
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Figure Burst Transfer Example When driven HC912B32, MC68HC55 Peripheral enabled first transfer after this command transfer. Bit7 this command determines read write command. Bits[2:0] specify address eight MC68HC55 registers internal pointer established. Data sent back HC912B32 from MC68HC55 during command transfer read data from adress previously pointed (this would zeros first transfer after reset). additional transfers result write-to read-from successive registers MC68HC55. internal register pointer incremented transfer will roll over from (111) 0(000). remains throughout whole burst sequence driven high HC912B32. Possible software routines perform set-up control transfer data burst mode shown source code detailed functions InitSpi SpiBurst Appendix Source Code.
Initialisation MC68HC55 Peripheral's Registers
Table Registers shows MC68HC55 registers. HC912B32 read-from write-to MC68HC55's seven registers through interface. Data transferred slave nodes written into
DSI0H Data Access DSI/D Channel (high byte) Bit-15 Bit-14 Bit-13 Bit-12 Bit-11 Bit-10 Bit-9
address Bit-8 High
DSI0L- Data Access DSI/D Channel (low byte) Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1
address Bit-0
Table Registers
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DSI1H Data Access DSI/D Channel 1(high byte) Bit-15 Bit-14 Bit-13 Bit-12 Bit-11 Bit-10 Bit-9
address Bit-8 High
DSI1L- Data Access DSI/D Channel 1(low byte) Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1
address Bit-0
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DSISTAT- Status Register TFE1 TFNF1 RFNE1 TFE0 TFNF0
address RFNE0
DSI0CTRL- Channel Control Register CDIV0B CDIV0A DLY0B DLY0A RIE0 TIE0
address
DSI1CTRL- Channel Control Register CDIV1B CDIV1A DLY1B DLY1A RIE1 TIE1
address
DSIENABL
address
Table Registers (Continued) DSIxH:DSIxL register pair 16-bit messages; DSIxL 8-bit. transfer begins once DSIxL been written Similarly, responses from slave nodes written into these registers. DSISTAT register provides status information should checked before after transfers. contains error flag, ERx, which indicates master received invalid value. Also, transmit receive status information, TFEx, TFNFx RFNEx, available through this register. DSIxCTRL register written before data sent over bus. This register used specify additional divider between SCLK input timing circuitry, CDIVx[B:A], well defining
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Summary
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interframe delay, DLYx[B:A]. also used enable interrupts, RIEx TIEx, select -bit data bits plus bits) 20-bit data bits plus bits) messages, MSx. This register updated soon data received over interface, however, value does take affect until next clock cycle after conclusion write this register. Finally, DSIENABL register used enable disable each channel. function SetupDSI shown source code Appendix Source Code example MC68HC55 Peripheral's registers. uses burst routine discussed section: `Initialisation SPI' sets registers initialisation programmable slave nodes.
Initialising Slave Nodes
Programmable Devices source code shown main section program that calls functions PgmAddr, PgmChk ChkRsp Appendix Source Code details very simple routine program addresses into slave nodes. programs slave nodes sequentially starting with address (0001) finishing with address (1111). ensure response from slave node whose address being captured, MC68HC55's clock period SCLK divided interframe delay times. This achieved writing MC68HC55's DSIxCTRL register (refer section: `Initialisation MC68HC55 Peripheral's Registers'). When network configured with pre-programmed devices initialisation procedure similar that programmable devices. initialisation command that contains address slave node being initialised sent that slave node. slave node then responds initialisation command master know present network.
Pre-programmed Devices
Summary
This Application Note discussed total system solution using full suite Motorola ICs. Although initial target application automotive airbag systems could used other applications which require remote sensors. Distributed Systems Interface (DSI) many advantages that allows flexibility system design, easily expandible allows central module size decrease while system content grows.
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Freescale Semiconductor, Inc. Application Note References
Specification; internal Motorola document MC68HC55 Peripheral Specification; data sheet, order number MC68HC55/D Specification; only available with Evaluation System (contact sales office more details) MC33790 Physical Layer ASIC Specification; internal Motorola document MC68HC912B32 Advance Information; order number MC68HC912B32/D
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Appendix Source Code
Appendix Source Code
FILE B32DSI.h Header file referenced program InitB32DSI.c define register addresses COP, Define register #define COPBASE (volatile char *const)(0x16) #define COPCTL (*(COPBASE+0)) Define PORTA general purpose #define PTABASE (volatile char *const) (0x00) #define PORTA (*(PTABASE+0)) #define DDRA (*(PTABASE+2)) Define registers #define #define #define #define #define #define #define #define #define #define Define Registers #define #define #define #define #define #define #define #define #define
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PWMBASE (volatile char *const)(0x40) PWCLK (*(PWMBASE+0)) PWPOL (*(PWMBASE+1)) PWEN (*(PWMBASE+2)) PWRES (*(PWMBASE+3)) PWPER0 (*(PWMBASE+0xc)) PWDTY0 (*(PWMBASE+0x10)) PWCTL (*(PWMBASE+0x14)) PORTPP (*(PWMBASE+0x16)) DDRP (*(PWMBASE+0x17))
SPIBASE (volatile char *const)(0xd0) SP0CR1 (*(SPIBASE+0)) SP0CR2 (*(SPIBASE+1)) SP0BR (*(SPIBASE+2)) SP0SR (*(SPIBASE+3)) SP0DR (*(SPIBASE+5)) PORTS (*(SPIBASE+6)) DDRS (*(SPIBASE+7)) PURDS (*(SPIBASE+0xb))
FILE InitB32DSI.c code programmed into FLASH HC912B32 which initialises HC912B32 then sets registers MC68HC55 Peripheral I.C. before programming address into programmable slave nodes
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Freescale Semiconductor, Inc. Application Note
This source code example code that could used perform initialisation. Motorola reserves right make changes without further notice product herein improve reliability, function, design. Motorola does assume liability arising application product, circuit software described herein; neither does convey licensed under patent rights right others. Motorola products designed, intended authorised components intended surgical implant into body, other applications intended support life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such intended unauthorised application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorised use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola Motorola logo registered trademarks Motorola Ltd. #include <stdio.h> #include "B32DSI.h" #define ArraySize 0x0F
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(no. slave nodes)
short TBytes [ArraySize]; Array bytes transmitted short RBytes [ArraySize]; Array received bytes short ChkBytes [ArraySize]; Array check bytes check received data correct short ErrorCode [ArraySize]; Array Error codes This function sets HC912B32 void InitPWM(void) PWCLK 0x00; Don't divide clock PWPOL 0x00; clock polarity until duty count reached PWPER0 0x1b; Period 3.5µs (frequency 285.71 kHz) PWDTY0 0x0d; Duty cycle DDRP 0x01; PTP0 output PWCTL 0x00; Left aligned mode CENTR=0 PWEN 0x01; Enable This function sets HC912B32 void InitSPI(void) PURDS 0x00; Leave normal conditions SP0BR 0x00; clock frequency SP0CR1 0x00; CPOL CPHA DDRS 0xe0; PTS[7:5] outputs (SS, SCLK MOSI)
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Appendix Source Code
SP0CR1 0x10; Enable master mode SSOE=0, therefore SP0CR1 0x50; Enable system This function called SpiBurst function. writes information into data register when transfer complete flag sends back information received short TransmitReceive(short SendByte) dummy=0; short result;
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SP0DR SendByte; while ((SP0SR 0x80) complete flag dummy++; result SP0DR; return (result);
Wait until transfer
This function sets Burst transfer routine. enables MC68HC55 Peripheral driving then transfers required bytes data complete burst transfer. finishes driving high disabling MC68HC55 Peripheral void SpiBurst(int ByteCount) count; PORTS 0x00; Transmit bytes (count=0; count<ByteCount; count++) RBytes[count] TransmitReceive(TBytes[count]); HIGH PORTS 0x80; This function sets registers SetupDSI(void) ErrCnt=0; ChkCnt; DSI/D Registers TBytes[0] 0x85; Send (write reg. addr.
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TBytes[1] 0xb0; Rec./Transmit Interrupts disabled, size 20Bits 4CRC) TBytes[2] 0x00; ctrl same TBytes[3] 0x01; Only ENABLE (0x03 enable 0x02 enable ch.1 only) SpiBurst(4); TBytes DSI/D Transmits info.
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TBytes[0] 0x05; Cmd. read DSI/D registers starting address SpiBurst(4); RBytes[x] will return contents DSI/D registers ChkBytes[1] 0xb0; contents DSI0CTRL reg. ChkBytes[2] 0x00; contents DSI1CTRL reg. ChkBytes[3] 0x01; contents DSIENABL reg. should match RBytes[1] should match RBytes[2] should match RBytes[3]
Compare RBytes[1 ChkBytes[1 equal ErrCnt incremented returned main (ChkCnt=1; ChkCnt<4; ChkCnt ((RBytes[ChkCnt] 0x00ff) (ChkBytes[ChkCnt] 0x00ff)) ErrCnt++; return (ErrCnt); This function here allow visibility failures when using debugger tool void FlagError(int Err, Adr) ErrorCode[Err]=Adr; This function checks that TFNF0 flag void TFFlag(int Address) TBytes[0] 0x04; SpiBurst(2); (!(RBytes[1] 0x02)) FlagError(2,Address); (;;); error loop until device reset This function waits loop until RFNE0 flag therefore data been written into data registers void RFFlag(void) TBytes[0] 0x04;
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Appendix Source Code
SpiBurst(2); while ((RBytes[1] 0x01) SpiBurst(2); This function programs address into first slave node response expected void PgmAddr(int Addr) TFFlag(Addr); Check TFNF0 flag TBytes[0] 0x80; send (write DSI0H) receive TBytes[1] Addr; Addr into DSI0H then TBytes[2] DSI0L TBytes[2] 0x00; SpiBurst(3); RFFlag(); This function programs addresses into slave nodes through checks responses from slave nodes void PgmChk(int Addr, LastAddr) unsigned short DsiDat; unsigned short DsiChk; dummy=0; TFFlag(Addr); Check TFNF0 flag TBytes[0] 0x80; send (write DSI0H) TBytes[1] Addr; Addr written into DSI0H DSI0L TBytes[2] 0x00; SpiBurst(3); RFFlag(); Check (RBytes[1] 0x08) FlagError(4,LastAddr); (;;); error loop until device reset TBytes[0] 0x00; Read DSI0H DSI0L SpiBurst(3); DsiDat RBytes[1] 0x0000; shift DsiDat times DsiDat DsiDat DsiDat+RBytes[2]; need check response that bits[15:12] Prev. Slave Addr DsiDat DsiChk LastAddr 0x0000; (DsiDat DsiChk)
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FlagError(6,LastAddr); (;;); error loop until device reset
This function checks response program address command last slave node (number void ChkRsp(int Addr, ADCcmd)) unsigned short DsiDat; unsigned short DsiChk; dummy=0; TFFlag(Addr); Check TFNF0 flag TBytes[0] 0x80; send (write DSI0H) TBytes[1] 0x00; written into DSI0H DSI0L TBytes[2] 0xADCcmd; /*dummy command allow response from final addr captured SpiBurst(3); RFFlag(); Check (RBytes[1] 0x08) FlagError(4, Addr); (;;); /*error loop until device reset TBytes[0] 0x00; Read DSI0H DSI0L SpiBurst(3); DsiDat RBytes[1] 0x0000; shift DsiDat times DsiDat DsiDat DsiDat+RBytes[2]; need check response that bits[15:12] Slave Addr DsiDat DsiChk Addr 0x0000; (DsiDat DsiChk) FlagError(6,Addr); (;;); error loop until device reset main (int argc, char* argv[] Result=-1; short SlaveNum; address slave node programmed short PrevAddr; address previous slave node whose response requires checked COPCTL 0x00; Disable resets InitPWM(); InitSPI(); Result SetupDSI(); ctrl enable
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Appendix Source Code
registers (Result=0) OK*/ (Result FlagError(1,1); need stop program well (;;); error loop until device reset Program address into each slave node check response this version slave nodes (the maximum) PgmAddr(0x01); (SlaveNum=0x02, PrevAddr=0x01; SlaveNum<0x10; SlaveNum++, PrevAddr++) PgmChk(SlaveNum, PrevAddr); ChkRsp(0x0F, 0x02); return;
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Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
reach USA/EUROPE/Locations Listed: Motorola Literature Distribution, P.O. 5405, Denver, Colorado 80217, 1-800-441-2447 1-303-675-2140. Customer Focus Center, 1-800-521-6274 JAPAN: Motorola Japan Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 03-5487-8488 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd., Ping Industrial Park, Ting Road, N.T., Hong Kong. 852-26629298 MfaxTM, Motorola Back System: RMFAX0@email.sps.mot.com; http://sps.motorola.com/mfax/; TOUCHTONE, 1-602-244-6609; Canada ONLY, 1-800-774-1848 HOME PAGE: http://motorola.com/sps/ Mfax trademark Motorola, Inc. Motorola, Inc., 1999
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AN1816/D

AN1816 Freescale Semiconductor, Inc. USING HC912B32 IMPLEMEN

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