AN1774 Freescale Semiconductor, Inc. Interfacing MC68HC912B3

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AN1774 Freescale Semiconductor, Inc. Interfacing MC68HC912B3

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AN1774
Freescale Semiconductor, Inc.
Interfacing MC68HC912B32 Module
Mark Glenewinkel Field Applications Engineering Austin, Texas
Introduction
More more applications requiring liquid crystal displays (LCD) communicate effectively outside world. This application note describes hardware software interface needed display information from MC68HC912B32 (B32). Some suppliers provide only glass that waveforms needed directly drive segments have generated microcontroller (MCU) microprocessor (MPU). Other suppliers provide module, which glass segment drivers provided small packaged circuit board. This application note uses module from Optrex Corporation, part number DMC16207 (207). utilizes Hitachi driver, HD44780, provide segment waveforms simple parallel port interface that easily interfaces bus. Circuitry example code given also demonstrate ability providing pre-defined messages from memory display. code modified easily take serial peripheral interface (SPI) serial communication interface (SCI) data display module.
Motorola, Inc., 1999
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Freescale Semiconductor, Inc. Application Note Module Hardware Interface
Optrex many module configurations that have varying display lines display line character lengths. module 2-line, 16-character line display. Each character displayed using pixel font matrix. module character generator capable displaying ASCII characters. parallel interface work with either 4-bit 8-bit buses. Once data presented bus, latched clocking device. Depending pin, data will used instruction ASCII character.
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Descriptions
Table describes interface pins found module. Table Module Pinout
Number
Signal
Power Power Power (ground) volts volts drive voltage
Function
Selects registers Instruction register (for write), address counter (for read) Data register (for write read) Selects read write Write Read Starts data read/write falling edge Four high order bidirectional 3-state data pins. Used data transfer receive between 207. used busy flag. Four order, bidirectional, 3-state data pins. Used data transfer receive between 207. These pins used during 4-bit operation.
14-11
DB7-DB4
10-7
DB3-DB0
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Application Note Module Hardware Interface
Timing Table Timing Electricals
Spec Enable cycle time Enable pulse width (high level) Enable rise decay time Address setup time, R/W, Data delay time Symbol tCYCLE PWEH tEr, tDDR tDSW tDHR Unit
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Data setup time Data hold time (write) Data hold time (read) Address hold time
PWEH DB0-DB7 tDSW VALID DATA tCYCLE
Figure Write Timing Operation
PWEH DB0-DB7 tDDR VALID DATA tCYCLE tDHR
Figure Read Timing Operation
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Freescale Semiconductor, Inc. Application Note
Interface Figure Figure show examples 8-bit 4-bit timing sequences, respectively.
NOTE:
(busy flag) check needed maximum instruction execution time respected before sending another instruction.
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INTERNAL OPERATION
EXEC TIME
DB7-DB0
DATA INSTRUCTION WRITE
BUSY BUSY FLAG CHECK
BUSY BUSY FLAG CHECK
DATA INSTRUCTION WRITE
Figure 8-Bit Timing Sequence
INTERNAL OPERATION
EXEC TIME BUSY
DB7-DB0
D7-D4
D3-D0
BUSY
D7-D4
D3-D0
INSTRUCTION WRITE
BUSY FLAG CHECK
BUSY FLAG CHECK
INSTRUCTION WRITE
Figure 4-Bit Timing Sequence 4-bit interface data, only four lines (DB7-DB4) used transfer. lines DB3-DB0 disabled.
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Application Note Module Software Interface
data transfer completed after 4-bit data been transferred twice. four high order bits transferred first (DB7-DB4), then order bits transferred (DB3-DB0).
Module Software Interface
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Instruction Commands
module many different configurations that implemented easily sending correct function command device. These commands listed Table followed explanation each function they execute. Table Module Instruction Code
Instruction Clear display Return cursor home Entry mode Display on/off control Cursor display shift Function CGRAM address DDRAM address Read busy flag address Write data DDRAM Read data from DDRAM
Execution Time (max) 1.64 1.64
DDRAM: Display data CGRAM: Character generator ACG: CGRAM address ADD: DDRAM address; corresponds cursor address Address counter used both DDRAM CGRAM addresses
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Freescale Semiconductor, Inc. Application Note
Clear Display
Clear display writes space code into DDRAM addresses. then sets DDRAM address into address counter returns display original status shifted. other words, display disappears cursor blinking goes left edge first line display. entry mode (increment mode). entry mode left unchanged. Return cursor home sets DDRAM address into address counter returns display original status shifted. DDRAM contents change. cursor blinking goes left edge first line display.
Return Cursor Home
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Entry Mode
Increments (I/D decrements (I/D DDRAM address when character code written into read from DDRAM. cursor blinking moves right when incremented left when decremented same applies writing reading CGRAM. Shifts entire display either right (I/D left (I/D when display does shift will seem cursor does move display does. display does shift when reading from DDRAM. Also, writing into reading from CGRAM does shift display.
Display On/Off Control
display when when When off, display data remains DDRAM, displayed instantly setting cursor displayed when displayed when Even cursor disappears, function other specifications will change during display data write. cursor displayed using five dots eighth line character. character indicated cursor blinks when blinking displayed switching between blank dots displayed characters speed 409.6-ms intervals when fOSC (HD44780 operating frequency) kHz. cursor blinking display simultaneously. (The blinking frequency changes according fOSC. example, when fOSC, kHz, 409.6 (250/270) 379.2 ms.)
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Application Note Module Software Interface
Cursor Display Shift
Cursor display shift shifts cursor position display right left without writing reading display data. (See Table This function used correct search display. 2-line display, cursor moves second line when passes 40th digit first line. first second line displays will shift same time. When displayed data shifted repeatedly, each line moves only horizontally. second line display does shift into first line position.
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address counter (AC) contents will change only action performed display shift. Table Cursor Display Shift Combination
Description Shifts cursor position left; decremented Shifts cursor position right; incremented Shifts entire display left; cursor follows display shift Shifts entire display right; cursor follows display shift
Function
Sets interface data length. Data sent received 8-bit lengths (DB7 DB0) when 4-bit lengths (DB7 DB4) when When 4-bit length selected, data must sent received twice. Sets number display lines Sets character font
NOTE:
Perform function instruction beginning program before executing instructions (except read busy flag address instruction). From this point, function instruction cannot executed unless interface data length changed.
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Freescale Semiconductor, Inc. Application Note
CGRAM Address
CGRAM address sets CGRAM binary address ACG5-ACG0 into address counter. Data written read from CGRAM. DDRAM address sets DDRAM binary address ADD6-ADD0 into address counter. Data written read from DDRAM. Read busy flag address reads busy flag (BF) indicating that system internally operating previously received instruction. internal operation progress. next instruction will accepted until reset Check status before next write operation. same time, value address counter binary (AC6-AC0) read out. This address counter used both CGRAM DDRAM addresses, value determined previous instruction. address contents same instructions CGRAM address DDRAM address. Write data CGRAM DDRAM writes 8-bit data CGRAM DDRAM. write into CGRAM DDRAM determined previous specification CGRAM DDRAM address setting. After write, address incremented decremented automatically according entry mode. entry mode also determines display shift. Read data from CGRAM DDRAM reads 8-bit data from CGRAM DDRAM. previous designation determines whether CGRAM DDRAM read. Before entering this read instruction, either CGRAM DDRAM address instruction must executed. executed, first read data will invalid. When serially executing read instructions, next address data normally read from second read. address instructions need executed just before this read instruction when shifting cursor cursor shift instruction (when reading DDRAM).
DDRAM Address
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Read Busy Flag Address
Write Data CGRAM DDRAM
Read Data from CGRAM DDRAM
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Application Note Module Software Interface
operation cursor shift instruction same DDRAM address instruction. After read, entry mode automatically increases decreases address However, display shift executed regardless entry mode.
Address
Table shows address HD44780. character positions module shown first table with addresses shown beneath them. uses only first addresses.
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NOTE:
addresses seven bits wide when writing DDRAM, (bit always Therefore, write address $02, 8-bit data sent will binary 10000010%.
Understand that when display shifted, whole address used. other words, when shift right executed, character address moved position first line display. Table Address
Initialization Routines
ensure proper initialization module, sequence instruction codes must executed. These instructions data width, font type, number display lines. addition, cleared, entry mode data set. Figure shows power-on reset initialization 8-bit data bus, while Figure shows power-on reset initialization 4-bit data bus.
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Freescale Semiconductor, Inc. Application Note
POWER
WAIT MORE THAN AFTER RISES CANNOT CHECKED BEFORE THIS INSTRUCTION FUNCTION INTERFACE BITS
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WAIT MORE THAN CANNOT CHECKED BEFORE THIS INSTRUCTION FUNCTION INTERFACE BITS
WAIT MORE THAN CANNOT CHECKED BEFORE THIS INSTRUCTION FUNCTION INTERFACE BITS CHECKED AFTER THESE INSTRUCTIONS FUNCTION INTERFACE BITS SPECIFY DISPLAY LINES FONTS. SETTINGS CANNOT CHANGED AFTER THIS POINT. DISPLAY DISPLAY CLEAR ENTRY MODE
Figure Power-On Reset 8-Bit Initialization
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Application Note Module Software Interface
POWER
WAIT MORE THAN AFTER RISES CANNOT CHECKED BEFORE THIS INSTRUCTION FUNCTION INTERFACE BITS
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WAIT MORE THAN CANNOT CHECKED BEFORE THIS INSTRUCTION FUNCTION INTERFACE BITS
WAIT MORE THAN CANNOT CHECKED BEFORE THIS INSTRUCTION FUNCTION INTERFACE BITS CHECKED AFTER THESE INSTRUCTIONS DISPLAY DISPLAY CLEAR ENTRY MODE FUNCTION INTERFACE BITS FUNCTION INTERFACE BITS SPECIFY DISPLAY LINES FONTS SETTINGS CANNOT CHANGED
Figure Power-On Reset 4-Bit Initialization
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Freescale Semiconductor, Inc. Application Note MC68HC912B32 Hardware Interface
16-bit device with standard on-chip peripherals including: Kbytes FLASH EEPROM Kbyte bytes EEPROM Asychronous serial communications interface (SCI) Serial peripheral interface (SPI) 8-channel, 16-bit timer 8-channel, 8-bit analog-to-digital converter (ADC) 4-channel pulse-width modulator (PWM) J1850-compatible byte data link communications module (BDLC)
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maximum (input/output) pins single-chip mode. These pins share functionality with on-chip peripheral modules. Rarely will system have these pins available. module works either 8-bit 4-bit data bus. data size should defined from I/O, peripheral, code space usage application. Three pins also needed control. schematic used testing B32-to-207 interface MC68HC912B32 evaluation board shown Figure test circuit designed either 4-bit 8-bit databus. Although connected B32, grounded only writes executed. Since cannot check flag, delay times stated Table must observed. Although these routines were tested MC68HC912B32 device, HC12 device with enough memory execute these routines. simple change memory should allow code ported other HC12s.
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Application Note MC68HC912B32 Software Interface
DMC16207 MODULE
Freescale Semiconductor, Inc.
INTERFACE NOTE: 4-BIT INTERFACE, DB3-DB0 PINS CONNECTED.
Figure B32-to-207 Interface Test Circuit
MC68HC912B32 Software Interface
software written demonstrate MC68HC912B32-to-LCD module interface shown sections titled Flowcharts, 4-Bit Code, 8-Bit Code. flowchart roughly sketches routines. code written take pre-defined messages easily display them calling subroutine. receiving messages from SCI, ASCII data temporary buffer change message routines start reading ASCII characters from start buffer.
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Freescale Semiconductor, Inc. Application Note Development Tools
interface created tested using these development tools: M68HC12B32EVB Motorola's MC68HC912B32 evaluation board IDE- Microcomputer Systems integrated development environment, version 1.02 CASM12W Microcomputer Systems HC12 assembler, version 3.08 ICD12W Microcomputer Systems HC12 in-circuit debugger, version 1.04 build
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References
MC68HC912B32 Technical Summary, Motorola document order number MC68HC912B32TS/D, 1997. M68HC12 CPU12 Reference Manual, Motorola document order number CPU12RM/AD, 1997.
DMC-16207 Digikey #73-1025-ND. 1997 Optrex Databook Digikey #73-1001-ND. Motorola's HC12 website:
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Application Note Flowcharts
Flowcharts
START
INITIALIZE PORT PINS WAIT
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SEND FUNCTION CODE WAIT
SEND FUNCTION CODE WAIT SEND FUNCTION CODE
FUNCTION CODE BUS, ROWS, DOTS LCD_WRITE
DISPLAY CODE DISPLAY CURSOR OFF, BLINKING LCD_WRITE
CLEAR DISPLAY CODE CLEAR DISPLAY, CURSOR ADDR LCD_WRITE WAIT
ENTRY MODE CODE INCREMENT, DISPLAY SHIFT LCD_WRITE
JUMP MESSAGE1
JUMP MESSAGE2
INFINITE LOOP
Figure Main Flowchart
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Freescale Semiconductor, Inc. Application Note
LCD_WRITE
STORE ACCA DATA PORT
CLOCK
WAIT
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RETURN FROM
Figure LCD_Write Subroutine Flowchart
LCD_ADDR
CLEAR INSTRUCTION MODE
STORE ACCA DATA PORT
CLOCK
WAIT
INSTRUCTION MODE
RETURN FROM
Figure LCD_ADDR Subroutine Flowchart
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Application Note Flowcharts
MESSAGE
LOAD ACCA WITH ADDRESS
LCD_ADDR
CLEAR INDEX REGISTER
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LOAD ACCA FROM POINTING MESSAGE BUFFER
ACCA BUFFER? LCD_WRITE
INCREMENT INDEX REGISTER
RETURN FROM
Figure Message Subroutine Flowchart
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Freescale Semiconductor, Inc. Application Note 8-Bit Code
File name: H12_LCD8.ASM Example Code Module (DMC16207) using 8-bit interfacing with MC68HC912B32 Ver: Date: September 1998 Author: Mark Glenewinkel Motorola Field Applications Assembler: CASM12W 3.08 *For code explanation flowcharts, please consult Motorola Application Note "Interfacing MC68HC912B32 Module" Literature AN1774/D Note: Code originates instead FLASH SYSTEM DEFINITIONS EQUATES Internal Register Definitions PORTA ;LCD data PORTB ;LCD control signals DDRA ;data direction PortA DDRB ;data direction PortB Application Specific Definitions LCD_DATA LCD_CTRL Memory Definitions RAM_START $0800 RAM_VAR $0BF0 MSG_STORAGE $0B00 Vectors RESET
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;PORTA ;PORTB ;PORTB, ;PORTB, ;PORTB,
;start ;start variables ;start message block
$FFFE
;vector reset
VARIABLES RAM_VAR TIME ;used delay time MAIN ROUTINE RAM_START ;start begining Initialize Stack Pointer #$0BFF ;init
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Application Note 8-Bit Code
Intialize Ports START movb movb
LCD_CTRL LCD_DATA #$FF,DDRA #$FF,DDRB
;clear ;clear ;PortA ;PortB
LCD_CTRL LCD_DATA output output
INITIALIZE Wait 15ms movb #150T,TIME VAR_DELAY Send Init Command movb #$38,LCD_DATA bset LCD_CTRL,E bclr LCD_CTRL,E
;set delay time ;sub 0.1ms delay ;LCD init command ;clock data
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Wait 4.1ms movb
#41T,TIME VAR_DELAY
;set delay time ;sub 0.1ms delay ;LCD init command ;clock data
Send Init Command movb #$38,LCD_DATA bset LCD_CTRL,E bclr LCD_CTRL,E Wait movb #1T,TIME VAR_DELAY
;set delay time ;sub 0.1ms delay ;LCD init command ;write data
Send Init Command ldaa #$38 LCD_WRITE Send Function Command bus, rows, dots ldaa #$38 LCD_WRITE Send Display Ctrl Command display cursor off, blinking ldaa #$0C LCD_WRITE Send Clear Display Command clear display, cursor addr=0 ldaa #$01 LCD_WRITE movb #16T,TIME VAR_DELAY Send Entry Mode Command increment, display shift ldaa #$06 LCD_WRITE SEND MESSAGES Messages have address content predefined MESSAGE1 MESSAGE2 DUMMY AN1774 MOTOROLA DUMMY
;function command ;write data
;display ctrl command ;write data ;clear display command ;write data ;set delay time 1.6ms ;sub 0.1ms delay ;entry mode command ;write data
;send Message1 ;send Message2 ;done with example
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Freescale Semiconductor, Inc. Application Note
SUBROUTINES Routine creates delay according formula TIME*~100µs using 8MHz internal Cycle count instruction shown VAR_DELAY ldab #199T dbne B,L1 TIME VAR_DELAY Routine sends Data LCD_WRITEstaa LCD_DATA bset LCD_CTRL,E bclr LCD_CTRL,E ldaa #107T dbne A,L2 Routine sends LCD_ADDR bclr staa bset bclr ldaa dbne bset Message Routines MESSAGE1 ldaa ldaa OUTMSG1 MESSAGE2 ldaa ldaa Address LCD_CTRL,RS LCD_DATA LCD_CTRL,E LCD_CTRL,E #107T A,L4 LCD_CTRL,RS #$84 LCD_ADDR MSG1,X OUTMSG1 LCD_WRITE #$C4 LCD_ADDR MSG2,X OUTMSG2 LCD_WRITE
;clock data ;40µs delay
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;LCD command mode ;clock data ;40µs delay ;LCD data mode ;addr ;send addr ;load AccA w/char from ;end msg? ;write data ;increment ;loop finish ;addr ;send addr ;load AccA w/char from ;end msg? ;write data ;increment ;loop finish
OUTMSG2
MESSAGE STORAGE MSG_STORAGE MSG1 'Motorola' MSG2 'HC12 MCU' VECTOR TABLE RESET START AN1774 More Information This Product, www.freescale.com MOTOROLA
Application Note 4-Bit Code
4-Bit Code
File name: H12_LCD4.ASM Example Code Module (DMC16207) using 4-bit interfacing with MC68HC912B32 Ver: Date: September 1998 Author: Mark Glenewinkel Motorola Field Applications Assembler: CASM12W 3.08 code explanation flow charts, please consult Motorola Application Note "Interfacing MC68HC912B32 Module" Literature AN1774/D Note: Code originates instead FLASH SYSTEM DEFINITIONS EQUATES Internal Register Definitions PORTA ;LCD data PORTB ;LCD control signals DDRA ;data direction PortA DDRB ;data direction PortB Application Specific Definitions LCD_DATA LCD_CTRL Memory Definitions RAM_START $0800 RAM_VAR $0BF0 MSG_STORAGE $0B00 Vectors RESET $FFFE ;PORTA ;PORTB ;PORTB, ;PORTB, ;PORTB, ;start ;start variables ;start message block ;vector reset
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VARIABLES RAM_VAR TIME ;used delay time MAIN ROUTINE RAM_START ;start beginning Initialize Stack pointer #$0BFF ;init Initialize Ports START movb movb AN1774 MOTOROLA More Information This Product, www.freescale.com LCD_CTRL LCD_DATA #$FF,DDRA #$FF,DDRB ;clear ;clear ;PortA ;PortB LCD_CTRL LCD_DATA output output
Freescale Semiconductor, Inc. Application Note
INITIALIZE Wait 15ms movb #150T,TIME VAR_DELAY Send Init Command movb #$30,LCD_DATA bset LCD_CTRL,E bclr LCD_CTRL,E Wait 4.1ms movb #41T,TIME VAR_DELAY
;set delay time ;sub 0.1ms delay ;LCD init command ;clock data
;set delay time ;sub 0.1ms delay ;LCD init command ;clock data
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Send Init Command movb #$30,LCD_DATA bset LCD_CTRL,E bclr LCD_CTRL,E Wait movb #1T,TIME VAR_DELAY
;set delay time ;sub 0.1ms delay ;LCD init command ;write data
Send Init Command ldaa #$30 LCD_WRITE Send Function Command bus, rows, dots ldaa #$20 LCD_WRITE ldaa #$20 LCD_WRITE ldaa #$80 LCD_WRITE Send Display Ctrl Command display cursor off, blinking ldaa #$00 LCD_WRITE ldaa #$C0 LCD_WRITE Send Clear Display Command clear display, cursor addr=0 ldaa #$00 LCD_WRITE movb #16T,TIME VAR_DELAY ldaa #$10 LCD_WRITE movb #16T,TIME VAR_DELAY
;function command ;write data ;function command ;write data ;function command ;write data
;function command ;write data ;display ctrl command ;write data ;clear display command ;write data ;set delay time 1.6ms ;sub 0.1ms delay ;clear display command ;write data ;set delay time 1.6ms ;sub 0.1ms delay
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Application Note 4-Bit Code
Send Entry Mode Command increment, display shift ldaa #$00 LCD_WRITE ldaa #$60 LCD_WRITE SEND MESSAGES Messages have address content predefined DUMMY MESSAGE1 MESSAGE2 DUMMY
;entry ;write ;entry ;write
mode data mode data
command command
;send Message1 ;send Message2 ;done with example
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SUBROUTINES Routine creates delay according formula TIME*~100µs using 8MHz internal Cycle count instruction shown VAR_DELAY ldab #199T dbne B,L1 TIME VAR_DELAY Routine sends LCD_WRITE staa bset bclr ldaa dbne Routine sends LCD_ADDR bclr staa bset bclr ldaa dbne bset Message Routines MESSAGE1 ldaa ldaa ldaa ldaa asla asla asla asla AN1774 MOTOROLA More Information This Product, www.freescale.com Data LCD_DATA LCD_CTRL,E LCD_CTRL,E #107T A,L2 Address LCD_CTRL,RS LCD_DATA LCD_CTRL,E LCD_CTRL,E #107T A,L4 LCD_CTRL,RS
;clock data ;40µs delay ;LCD command mode ;clock data ;40µs delay ;LCD data mode
#$80 LCD_ADDR #$40 LCD_ADDR MSG1,X OUTMSG1 LCD_WRITE MSG1,X
;addr ;send ;addr ;send
addr addr
;load AccA w/char from ;end msg? ;write data ;load AccA w/char from ;shift
Freescale Semiconductor, Inc. Application Note
OUTMSG1 MESSAGE2
LCD_WRITE
;write data ;increment ;loop finish
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ldaa #$C0 ;addr LCD_ADDR ;send addr ldaa #$40 ;addr LCD_ADDR ;send addr ldaa MSG2,X ;load AccA w/char from OUTMSG2 ;end msg? LCD_WRITE ;write data ldaa MSG2,X ;load AccA w/char from asla ;shift asla asla asla LCD_WRITE ;write data ;increment ;loop finish OUTMSG2 MESSAGE STORAGE MSG_STORAGE MSG1 'Motorola' MSG2 'HC12 MCU' VECTOR TABLE RESET START
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AN1774 Freescale Semiconductor, Inc. Interfacing MC68HC912B3

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