AN1770 Freescale Semiconductor, Inc. In-Circuit Programming

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AN1770
Freescale Semiconductor, Inc.
In-Circuit Programming FLASH Memory MC68HC908GP20
Grant Whitacre Microcontroller Division Austin, Texas
Introduction
This application note describes methods programming FLASH memory Motorola MC68HC908GP20 (GP20) microcontroller, general-purpose device based 68HC08 architecture that Kbytes on-board FLASH. Programming FLASH array done either user mode monitor mode. information given here details: FLASH programmed erased in-circuit each these modes control protection registers programmed Additional considerations when dealing with this type memory
illustrate GP20's in-circuit programming capabilities, sample program included which executes programming routines from RAM.
Motorola, Inc., 1999
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Freescale Semiconductor, Inc. Application Note
These routines loaded ways: When programming user mode, routines would part transferred into bigger program residing FLASH. This program could initiated user's main program, perhaps through monitoring input port, could loaded into FLASH stand-alone seed program which would later enable re-programming entire FLASH array with actual user program. Alternatively, routines could loaded directly into external host with device monitor mode.
Freescale Semiconductor, Inc.
main routine this dual mode program monitors (serial communications interface) port when user mode programming, port when monitor mode programming, input data address range FLASH where data programmed. then makes necessary calls other RAM-loaded routines necessary erasing, programming, verifying. host program's necessary functionality also described this application note. specifically used generation this document Windows application accommodates both modes programming. available free download from Motorola site, user will able in-circuit program GP20 either monitor mode user mode with: This host program MC68HC908GP20 programs format target system that configured communicate with host basic understanding device FLASH memory
Windows registered trademark Mircrosoft U.S. other countries.
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Application Note Description FLASH Memory MC68HC908GP20
Description FLASH Memory MC68HC908GP20
Memory FLASH Location
memory MC68HC908GP20 shown Figure Note that FLASH memory occupies addresses from $B000 $FDFF, single byte block protection register $FF80, block user vectors from $FFDC $FFFF. total addressable FLASH capacity 20,005 bytes.
$0000 $003F $0040 $023F $0240 $AFFF $B000 $FDFF $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 $FE06 $FE07 $FE08 Break Status Register (SBSR) Reset Status Register (SRSR) Reserved (SUBAR) Break Flag Control Register (SBFCR) Interrupt Status Register (INT1) Interrupt Status Register (INT2) Interrupt Status Register (INT3) Reserved (FLTCR) FLASH Control Register (FLCR) FLASH Memory 19,968 Bytes Unimplemented 44,480 Bytes Bytes Registers Bytes
Freescale Semiconductor, Inc.
Figure Memory (Sheet
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Freescale Semiconductor, Inc. Application Note
$FE09 $FE0A $FE0B $FE0C $FE0D $FE0F
Break Address Register High (BRKH) Break Address Register (BRKL) Break Status Control Register (BRKSCR) Status Register (LVISR) Unimplemented Bytes
Freescale Semiconductor, Inc.
$FE10 $FE1F $FE20 $FF52 $FF53 $FF7F $FF80 $FF81 $FFDB Note: $FFF6-$FFFD Also Used Security Bytes $FFDC $FFFF
Unimplemented Bytes Reserved Compatibility with Monitor Code A-Family Parts Monitor Bytes
Unimplemented Bytes FLASH Block Protect Register (FLBPR) Unimplemented Bytes
FLASH Vectors Bytes
Figure Memory (Sheet
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Application Note Description FLASH Memory MC68HC908GP20
FLASH Control Register
FLASH control register located $FE08 user memory map. This register provides means erase, program, verify FLASH. bits this register read written time. register structure shown Figure
Address: $FE08 Read: FDIV1 Write: FDIV0 BLK1 BLK0 HVEN MARGIN ERASE
Freescale Semiconductor, Inc.
Reset:
Figure FLASH Control Register (FLCR) FDIV bits frequency divide control bits ensure proper operation charge pump. optimum frequency about derived dividing internal frequency value stored FDIV1 FDIV0. Setting these bits should made according frequency shown Table Table Charge Pump Clock Frequency Function Frequency
FDIV1 FDIV0 Pump Clock Frequency frequency frequency frequency frequency When Frequency 1.8-2.5 3.6-5.0 3.6-5.0 7.2-10.0
NOTE:
There mechanism step pump clock frequency from frequency lower than attain charge pump frequency about MHz. Also, programming erasing FLASH cannot done charge pump frequency lower than MHz. BLK1 BLK0 block erase control bits used specify size location block FLASH erased. Erasing take place chunks single bytes), eight rows (512 bytes), Kbytes, Kbytes, entire array. procedure erasing
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Freescale Semiconductor, Inc. Application Note
these blocks FLASH discussed Procedure Erasing FLASH. setting bits corresponds erase block shown Table Table Size Erase Blocks
BLK1 BLK0 Block Size Full array: Kbytes Partial array*: Kbytes Eight rows: bytes Single row: bytes
Freescale Semiconductor, Inc.
$B000-$BFFF $C000-$FFFF, depending address written
HVEN high-voltage enable provides control apply charge pump voltage cells erased programmed. MARGIN used during programming verify that page attempting programmed gets programmed adequately. only verification after HVEN turned off. high when HVEN turned will clear automatically. Setting MARGIN puts FLASH "hard read" state, which ensures that FLASH verified this state then guarantees good read during normal operation. ERASE (program) control bits required when erasing programming, respectively. Both cannot same time.
Block Protection
block protection register provides preventing block FLASH from being erased programmed. This register, itself FLASH address, four bits with each protecting progressively larger block FLASH starting $FFFF. Figure shows register contents FLASH range that protected setting each bit. Erasing this register clears bits removes protection from blocks.
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Application Note Description FLASH Memory MC68HC908GP20
NOTE:
Setting more than redundant, three bits provide protection FLASH range some whose locations available GP20. Setting bits protects FLASH, setting only protects lower 1000H bytes.
Read: Write: Reset: BPR3 BPR2 BPR1 BPR0
Freescale Semiconductor, Inc.
Unaffected reset. Initial value from factory
Figure FLASH Block Protect Register (FLBPR) Table Block Protection Register Size Location Block Protected
Location Name BPR0 BPR1 BPR2 BPR3 Address Block Protected $B000-$FFFF $B000-$FFFF $B000-$FFFF $C000-$FFFF
Protection block protects block protection register because located address $FF80. only circumvent block protection modify FLASH enter monitor mode with VTST applied line upon reset. (See monitor mode entry Circuit Requirements.) When this occurs, FLASH, including block protection register, erased programmed regardless block protection.
NOTE:
Since block protection register located $FF80, first byte whose range $FF80-$FFBF. There other implemented FLASH locations within this row, this register erased with impact other locations specifying erasing with bits FLASH control register (BLK1 BLK0 program FLASH user mode, make sure that FLASH modified block protected; otherwise, turn block protection example described here.
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Freescale Semiconductor, Inc. Application Note Procedure Erasing FLASH
FLASH array erased block, size which determined bits FLASH control register, shown Table Follow this step-by-step procedure erase block FLASH reliably. Make sure that block erased protected settings block protection register. Block Protection description clearing protection block.
Freescale Semiconductor, Inc.
Write FLASH control register with pattern that sets appropriate FDIV bits bits. ERASE same time. Read block protect register that FLASH control logic latch content. Write data FLASH address within block erased. HVEN FLASH control register apply programming (charge pump) voltage. Delay time, tErase (FLASH erase time), while programming voltage applied. Consult memory characteristics information electrical specifications section MC68HC908GP20 Advance Information, Motorola document order number MC68HC908GP20/D, this value other times referenced this application note. Clear HVEN turn programming voltage. Delay time, tKill (high voltage kill time), allow high voltage charge pump dissipate. Clear ERASE bit. Delay time, tHVD (FLASH return read time), before trying read from this block FLASH. Optionally, erase verification performed after step This verification would done with normal read each location FLASH, location would verified erased value read.
NOTE:
recommended that erased after eight programs page/pages row.
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Application Note Procedure Programming FLASH
Procedure Programming FLASH
FLASH array programmed page time, where page defined eight contiguous bytes whose first byte 8-byte boundary. normal programming sequence includes verification step during which FLASH "margin read" verification mode. this mode, control gates held lower voltage than normal read. allow sensing lower cell current, reads this mode last eight machine cycles longer than normal read.
Freescale Semiconductor, Inc.
Follow this procedure reliably program verify page FLASH. Make sure that page programmed within protected block. block protection section description clearing protection block. Write FLASH control register with pattern that sets appropriate FDIV bits. same time. Read block protect register that FLASH control logic latch content. Write individual data each eight bytes page programmed. HVEN FLASH control register apply programming (charge pump) voltage. Delay time, tPROG (FLASH program time), while programming voltage applied. Clear HVEN turn programming voltage. Delay time, tHVTV (FLASH HVEN MARGIN high time), allow enough time between applying high voltage doing verification. MARGIN initiate verification mode. Delay time, tVTP (FLASH MARGIN high time). Clear bit. Delay time, tHVD (FLASH return read time), before trying read from this block FLASH.
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Freescale Semiconductor, Inc. Application Note
Read individual data each eight byte locations compare what intended programmed. Clear MARGIN bit. Repeat steps through each page until data matches.
Practical Considerations Programming, Verifying, Erasing
Freescale Semiconductor, Inc.
Life Expectancy Terms Program/Erase Cycling
FLASH MC68HC908GP20 endurance specification erase/program cycles. Therefore, suited short-term temporary non-volatile parameter storage. This limitation could alleviated somewhat devising scheme move parameter storage area when approaches 100-cycle limit. example, bytes) parameter data stored updated frequent basis program short enough occupy less than two-thirds 20-Kbyte capacity, then method moving location parameter block when number erase/program cycles approach (cycle count could stored this block) could implemented. this example, this would effectively increase number parameter updates 10,400. Unused FLASH: 19,968 bytes 6656 bytes rows cycles/row rows unused FLASH space 10,400 erase/program cycles Since smallest block erased entire row, whenever byte changed, entire would need erased reprogrammed. Because this limitation with FLASH, using store non-volatile temporary values limited usefulness.
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Application Note Programming MC68HC908GP20 User Mode
Margin Programming
Margin, bump, programming method FLASH programming which done successive periods relatively short duration, such millisecond. After each "bump," page that attempted programmed checked margin mode, verification byte page fails, entire page re-programmed, without erasing, another bump period. This process repeated until bytes page pass verification. Bump programming minimizes programming time, only user's benefit also endurance FLASH. minimizing amount time that FLASH cell exposed programming voltage, life cell maximized possibility disturbing (inadvertently programming) neighboring cells excessively long programming time minimized. program contained this application note utilizes this method programming, does information Procedure Programming FLASH.
Freescale Semiconductor, Inc.
Programming MC68HC908GP20 User Mode
Program Algorithm
Included this application note program that demonstrates capability perform in-circuit programming. setting assembler directives, this program loaded into FLASH user mode, special mode entry hardware required. After initialization loading routine executed from FLASH, initiated either upon reset subroutine call from user's existing main program, program branches place where program execution resumes. From RAM, serial communication port monitored download data programmed into FLASH starting address place this data. After this data received, main routine calls necessary subroutines, also located RAM, perform necessary FLASH erasing, programming, verification, memory dumping. bytes) data downloaded time, although there stipulations when downloading data programmed.
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Freescale Semiconductor, Inc. Application Note
They are: data downloaded must intended reside within single boundary. This means that start address must divisible when entire programmed. data forming less than entire downloaded, previous rule still applies. intended addresses must within single boundary. Additionally, since programming takes place eight bytes time, multiple eight bytes should downloaded starting address must page (8-byte) boundary. program checks intended addresses erased before attempting program. cell erased, then entire erased. programming less than entire row, remember that entire will erased block designated reprogramming completely erased. completion each block programming, data read from current bytes sent port, even less than entire reprogrammed.
Freescale Semiconductor, Inc.
This main routine executes continuous loop that multiple data downloads take place without program ever leaving RAM. fact, entire FLASH array (re)programmed this manner. completion programming, device will need reset take monitoring routine execute code FLASH. After receiving data programmed loading with necessary programming code, program execution jumps actual FLASH programming. program consists functions listed here: Initialize variables, ports, selected), SCI. Transfer these subroutines RAM: LOADDATA Polls data programmed, start address, length data array (see Message Structure Communicate between Host GP20). This routine also calls other routines needed.
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Application Note Programming MC68HC908GP20 User Mode
DUMPROW Dumps contents current bytes) PRGFLSH Controls routine program FLASH ERACHK Checks FLASH needs erased does necessary DELNUS Delays microseconds preloaded into H:X) PRGPAGE Programs page (eight bytes) FLASH Execute code program FLASH RAM, making necessary calls other routines perform actual programming/erasing. Return port monitoring loop
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Utilization Program Execution
Since program execution cannot occur FLASH block same time being modified, since this device only block nonvolatile memory, execution code modify FLASH must from from monitor which will discussed later). program which resides FLASH loads necessary programming erasing modules then jumps main routine which, when appropriate, makes calls other modules. Since capacity GP20 bytes, code executed kept that size. Therefore, only programming, erasing dumping routines, array data programmed, necessary variables, stack into RAM. Almost used program, variables, message buffer, stack.
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Freescale Semiconductor, Inc. Application Note
utilization found Table Table Utilization
Function Unused Download size Start address block program Number bytes program Allocated Space bytes byte bytes byte bytes bytes bytes bytes bytes Address Range $40-$4F $51-$52 $54-$93 $94-$A7 $A8-$DF $E0-$FF $100-$23F
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Data array Variables routines Stack routines
Assembler Directives
switches program implemented through assembler directives. They were left program mode configuration ease user testing, especially emulation environment. directive constant meaning outlined Table Table Assembler Directives
Assembler Constant MONPROG set, (necessary) routines will addressed initially. This version would used record file that downloaded into monitor mode FLASH programming. When set, changes programming/erase routines. Done prevent illegal write error when emulating. Programming attempted verification step will fail. When set, always causes erase verification true. Done exercise good loop logic.
TESTMOD
ERSDTST
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Application Note Programming MC68HC908GP20 User Mode
Other ApplicationSpecific Memory Equates
Several other constants used program which modified desired user. This necessary user wishes incorporate this program into existing program which already fixed memory. Table Program Constants
Constant CPUSPD
Default Value $B000
Other Possible Settings $40-$4F Dependent location branch page Anywhere FLASH Anywhere after variable space value larger than program size plus stack size,
Description Specifies frequencies: 2.45 MHz, 4.92 MHz, Specifies start address RAM. locations offset from this value. Specifies amount reserved stack Start FLASH program that launches program Start program. here, just after variable space Length program plus stack area Value bytes, except size bytes, used test mode instead downloaded value. this value that first address used ($C0C0) boundary Number attempts program page FLASH before giving
Freescale Semiconductor, Inc.
STCKSIZ PRGSTRT RAMPRG
RAMPRSZ
$1A7
TESTDAT
byte value
PRGTRIES VTPGM VHLFTER VTKILL VTHVD VTHVTV VTVTP PLLCHK NHI, NLO,
1000 50,000 $2C, $80,
value greater than
programming timing specification data book
Programming times
setup procedure data book
Input port used check initiated; initiated when port high setup parameters; values used allow external clock 32.768 stepped 2.45-MHz frequency
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Freescale Semiconductor, Inc. Application Note
Proper Clock Selection constant called CPUSPD application-specific memory (input/output) equates section program. purpose allow programmer select three frequencies this constant, which directly affects SCI, FLASH control register, timing constants particular, based CPUSPD setting corresponding internal frequency 2.4576, 4.9152, MHz, communicate 9600 baud (assuming selection internal clock clock source (see Setup) FDIV FLASH control register cause closest optimum setting charge pump frequency MHz. external clock frequency such that causes frequency lower than required proper charge pump operation, enabled. turned upon initial program execution port set. this event, program assumes external clock 32.768 steps this 2.4576-MHz frequency. initialization routine sets baud rate 9600 FDIV divider divide-by-1 charge pump frequency 2.4576 MHz. Make sure that CPUSPD constant described earlier enabled. Also, external clock frequency other than 32.768 exists that would necessitate (external clock less than MHz), then setup this SCI/FDIV initialization routine (SFINIT) will have modified proper communication charge pump frequency requirements. (See note FLASH Control Register.)
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Setup
Since this application note control PLL, description here brief. settings used justified with calculations, means making these settings shown. significance each each register covered. Refer clock generator module section GP20 data manual details about proper setup. control status registers GP20's shown Figure
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Application Note Programming MC68HC908GP20 User Mode
Addr.
Register Name Read: Control Register Write: (PCTL) Reset: Read: Bandwidth Control Write: Register (PBWC) Reset:
PLLIE AUTO
PLLF
PLLON
PRE1
PRE0
VPR1
VPR0
$0036
LOCK
$0037
MUL11
MUL10 MUL2 VRS2 RDS2
MUL9 MUL1 VRS1 RDS1
MUL8 MUL0 VRS0 RDS0
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Read: Multiplier Select High $0038 Write: Register (PMSH) Reset: Read: Multiplier Select $0039 Write: Register (PMSL) Reset: Read: Select Range Write: Register (PMRS) Reset: Read: Reference Divider Write: Select Register (PMDS) Reset:
MUL7 VRS7
MUL6 VRS6
MUL5 VRS5
MUL4 VRS4
MUL3 VRS3 RDS3
$003A
$003B
Reserved
Unimplemented Notes:
When AUTO PLLIE forced clear read-only. When AUTO PLLF LOCK read clear. When AUTO read-only. When PLLON VRS7:VRS0 forced clear read-only. When PLLON programming register read-only. When PLLON forced read-only.
Figure Control Status Registers
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Freescale Semiconductor, Inc. Application Note
intention boost external clock 32.768 2.45 frequency. This done through these steps: desired frequency four times desired frequency. fVCLKDES fBUSDES 2.4576 9.83 reference divider, which represented RDS3-RDS0 PCTL register, (default). power-of-two multiplier, which represented PRE1-PRE0 PCTL register, (default) this frequency. Calculate frequency multiplier, which represented MUL11-MUL0 PMSH PMSL registers, with this formula: round[R fVCLKDES fRCLK] where fRCLK reference (external) frequency 32.768 power-of-two range multiplier, which represented VPR1-VPR0 PCTL register, this clock frequency. Calculate center-of-range linear multiplier, which represented VRS7-VRS0 PMRS register, with this formula:
Freescale Semiconductor, Inc.
round[fVCLK fNOM)] round[9.83/(1*38.4 kHz)] where fNOM range nominal multiplier operating voltage ranges previous settings will produce VCO-programmed center-of-range frequency fVRS fNOM 38.4 9.83 only hardware requirements using PLL, aside from oscillator circuit, filter capacitor CGMXFC pin, bypass capacitor VDDA pin, pullup resistor about PB0. Consult data manual recommended values capacitors.
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Application Note Setup
Setup
Registers
Freescale Semiconductor, Inc.
clocked from external oscillator from internal clock. Selecting clock done through software programming bit, SCIBDSRC, CONFIG2 register. default this selects external oscillator clock source. external clock very slow being stepped PLL, this application, then necessary internal clock source reasonably fast baud rate. This application does this able derive 9600 transfer rate when oscillator 32.768 kHz. Figure shows structure content CONFIG register. Description other bits this register will addressed here, other than that PMPSGVLVEN must kept default state when operating with above volts.
Read: Write: Reset:
PMPSGV- OSCSCIBDLVEN STOPENB
Unimplemented
Figure Configuration Register (CONFIG2) Several registers used configure monitor module. Most settings need changed from default values this application, this discussion focuses values that need changed from default.
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Freescale Semiconductor, Inc. Application Note
control status registers shown Figure
Addr. Register Name ENSCI TCIE SCTE TXINV SCRIE DMARE SCRF ILIE DMATE IDLE WAKE ORIE ILTY NEIE FEIE PEIE
$0013
Read: LOOPS Control Register Write: (SCC1) Reset: Read: Control Register Write: (SCC2) Reset: Read: Control Register Write: (SCC3) Reset: Read: Status Register Write: (SCS1) Reset: Read: Status Register Write: (SCS2) Reset: Read: Data Register Write: (SCDR) Reset: Read: Baud Rate Register Write: (SCBR) Reset: SCTIE
$0014
Freescale Semiconductor, Inc.
$0015
$0016
$0017
$0018
Unaffected reset SCP1 SCP0 Reserved SCR2 Unaffected SCR1 SCR0
$0019
Unimplemented
Figure Control Status Registers
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Application Note Setup
This procedure used program SCI: Enable setting ENSCI SCC1. Enable both transmitting receiving setting bits SCC2. baud rate 9600 writing baud rate register (SCBR) with value that dependent frequency, shown Table Table Baud Rate Register Settings
Frequency 4.9152 2.4576 SCP1 SCP0 SCR2 SCR1 SCR0 Written SCBR
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other settings left defaults. Note that program selects programs baud rate register based value CPUSPD constant described Proper Clock Selection. On-Board Circuitry Required RS-232 Communication communicate another device over RS-232 line, voltage levels need adjusted that 5-volt signal transmitted received GP20 controller gets converted ±12-volt signal used programming device vice versa. This implemented level translator (integrated circuit) capacitors. possible external circuit this interconnection shown Figure another controller other device used which uses 0-volt 5-volt signal levels serial communication, then level translator needed.
NOTE:
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Freescale Semiconductor, Inc. Application Note
MC145407
MC68HC908GP20
DB-25
Freescale Semiconductor, Inc.
Figure RS-232 Circuit Serial Communication Message Structure Communicate between Host GP20 structure data sent GP20 simple, consisting components Table Table Message Structure
Message Byte Location Description Count total number bytes downloaded, including this byte First address where following data programmed Number bytes programmed, just dump this referenced row, value between erase entire FLASH array Locations bytes data programmed Final Location $51-$52
5-68
$54-$93
aware that only number bytes specified first byte will downloaded, byte which specifies number bytes programmed greater than value byte erroneous data will programmed. Also, fewer than number bytes specified byte included data block, erroneous data will programmed.
NOTE:
byte equal then nothing will programmed. content referenced first address bytes will uploaded
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Application Note Setup
host. This first address, this case, need starting address this row, bytes downloaded will within boundary. example, address $B3B3 downloaded with byte being then bytes range $B380-$B3BF will downloaded. This useful when performing host verification without programming. Note also that byte value between $FF, then entire FLASH array will erased. this case, first erased FLASH ($B000-$B03F) uploaded.
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Uploads will have header bytes. Instead, they will contain only data bytes. host message format should sent with same protocol which been initialized, namely 9600 baud, start bit, stop bit, parity.
Host Program
host program used program GP20 that executing this FLASH programming program, provided that conforms communication message structure requirements specified Message Structure Communicate between Host GP20. Windows-based program been developed in-circuit programming GP20 specifically this program this application note. downloaded cost from Motorola site installation this host program self-explanatory and, fact, explanation will offered. That since Motorola development tool product, support provided this program, user's risk.
CAUTION:
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Freescale Semiconductor, Inc. Application Note Programming MC68HC908GP20 Monitor Mode
General
Freescale Semiconductor, Inc.
MC68HC908GP20, like other HC08 Familiy devices, contains monitor utility which allows host control device. Only very basic, low-level instructions necessary available support this remote control. With supported instructions, location memory read, location written small program loaded into executed from area. instructions, READSP, allows reading stack pointer location, thereby giving host control where execution commences upon issuance another instruction, RUN. Monitor mode necessary programming blank device, since user mode programming requires initial program FLASH load FLASH programming routines jump them execution. These monitor commands used program FLASH GP20. couple approaches adopted implement monitor mode programming. host program directly control reading writing control registers, write specific locations FLASH, cause necessary delays during FLASH programming cycle only using monitor mode commands host program user interface. overhead here serial transmission time each command. alternate approach load program then start execution using monitor mode commands. program monitors same (input/output) port, port serial data/address transfers that used when communicating with monitor. Because inherent efficiency similarity user mode program, this latter approach what used this application note. Serial communication between host GP20 monitor mode half-duplex where both transmission reception data through single port. following sections discuss circuit, communications, security requirements enter GP20's monitor.
Circuit Requirements
schematic Figure shows recommended circuit enable entry into monitor mode 908GP20.
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Application Note Programming MC68HC908GP20 Monitor Mode
68HC08 VTST (SEE NOTE (SEE NOTES VDDA $FFFF VDDA CGMXFC
RESET VECTORS $FFFE
Freescale Semiconductor, Inc.
0.47
MC145407 32.768 XTAL 6-30 6-30 (SEE NOTE (SEE NOTE
0.01
OSC1 OSC2 PTA7 VSSAD/VREFL VSSA VDDAD/VREFH PTA0 PTC3 PTC0 PTC1
DB-25
MC74HC125
(SEE NOTE
Notes: monitor mode entry when VTST: SW1: Position clock CGMXCLK CGMVCLK SW1: Position clock CGMXCLK SW2, SW3, SW4: Position Enter monitor mode using external oscillator SW2, SW3, SW4: Position Enter monitor mode using external XTAL internal Table voltage level requirements.
Figure Monitor Mode Circuit Requirements
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Freescale Semiconductor, Inc. Application Note
Table shows requirements options entering monitor mode. short, enter monitor mode when reset vector blank, PTC0 must high PTC1 must low. reset vector ($FFFE-$FFFF) blank, then monitor mode entered without having high voltage (VTST special configuration port pins. this situation, monitor checks initializes 2.4576-MHz frequency based 32.768-kHz oscillator frequency.
Freescale Semiconductor, Inc.
reset vectors non-zero, then high voltage necessary automatic initialization performed. This means that device already programmed, then only test voltage required into monitor mode, port pins must correctly configured external clock must provided that generate desired internal frequency baud rate without PLL. course, could monitor commands initiate PLL, this presupposes that host communicate with device PLL. external clock 32.768 used, initial baud rate will bps.
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MOTOROLA
Table Monitor Mode Signal Requirements Options
External Clock(1) PTA0 Rate(2) operation until reset goes high Disabled PTA7 Baud CGMOUT Frequency Serial Communication Comment
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PTC0 PTC1 PTC3 4.9152 4.9152 2.4576 Disabled 9600 PTC0 voltages only required VTST; PTC3 determines frequency divider 9600 9.8304 4.9152 2.4576 Disabled PTC0 PTC1 voltages only required VTST; PTC3 determines frequency divider 32.768 4.9152 2.4576 Disabled Enabled 9600 9600 enabled (BCS set) monitor code Enters user mode will encounter illegal address reset Enabled Enters user mode External frequency always divided 9.8304 4.9152 2.4576 Disabled
RESET
$FFFE/ $FFFF
VTST
VTST
VTST
VTST
$0000
$0000
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VTST
$0000
VTST
Non-zero
Application Note Programming MC68HC908GP20 Monitor Mode
Notes: External clock derived 32.768-kHz crystal 4.9152/9.8304-MHz off-chip oscillator. PTA0 serial communication; PTA0 parallel communication PTA7 serial, PTA7 parallel communication security code entry does apply, don't care
Freescale Semiconductor, Inc. Application Note Communication Protocol
communication format which must used when communicating with GP20 monitor mode non-return-to-zero mark/space format. data format start bit, eight data bits, stop bit. Since device probably will communicate 9600 bps, host should same. Whatever source reference clock, remember that baud rate which device communicates always frequency divided 256. This requires that 9600 desired, then internal frequency must 2.4576 MHz. This frequency achieved three means: Using external oscillator frequency 4.9152 with PTC3 Using external oscillator frequency 9.8304 with PTC3 high Using external oscillator frequency 32.768 with during reset turn PLL; only offered when reset vector
Freescale Semiconductor, Inc.
NOTE:
monitor mode serial interface uses "bit banged" serial stream instead dedicated protocol. This constrains monitor mode baud rate, and, therefore, frequency, identically match host baud rate. example, frequency would yield baud rate 9766, which within tolerance will work with monitor mode. This reason monitor mode frequencies multiples 2.4576 MHz. monitor understands processes different commands. Table lists commands, their functions, their opcode, total number bytes required send command.
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Application Note Communication Protocol
Table Monitor Mode Command
Command READ WRITE IREAD IWRITE READSP Function Read memory Write memory Indexed read memory Indexed write memory Read stack pointer user program Opcode Number Bytes Sent Returned Value read; byte None values read; bytes None Address stack pointer; bytes None
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important note couple things regarding host-to-monitor communication. They are: First, using circuit described prior section connect port then there will loop-back data from host's transmit port receive port. This needs dealt with. Second, each command data byte sent GP20 echoed back host exactly time after stop that byte received. Therefore, adequate delay must built into host program ensure that next byte transmitted sent least time after echoed byte received.
time received byte does match what sent, command abort execution last command sent host. This command form break signal, which consists bits including start sent within times having received echo last byte command aborted. complete command, with follow-on address and/or data, must sent before break sent. Therefore, error perceived after echo byte command, transmission entire command should completed, followed transmission break signal. full break signal will echoed back host after 2-bit time delay having received one. Also, note that break signal sent host does have bits long does have start exactly time after data
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Freescale Semiconductor, Inc. Application Note
byte echo received. that necessary that least bit, like start transmitted byte, sent within1-bit time within 11-bit time period following reception echo last byte command. this point, monitor code waits host relinquish PTA0 sensing high signal after duration, then echoes complete break signal host. Refer GP20 data book, Motorola document order number HC908GP20GRS/D, timing diagrams further description each commands break signal. Most commands easily understood, sequence operation start execution program command worth discussing. Follow this procedure stack start execution loaded program. This procedure assumes that start routine resides first page RAM. Issue read stack pointer command ($0C). Monitor returns high byte then byte (SP+1) location. Ignore high byte will since stack pointer will first page memory) byte determine location write high byte routine start address. this location value determine locations write byte routine start address. Registers preloaded writing their intended value these locations:
(MSB) (LSB) (SP+1) (SP+1) (SP+1) (SP+1)
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Write each values step appropriate locations using WRITE IWRITE commands. Issue command.
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Application Note Security Requirements
Example sequence: start execution routine with start location $A8, with registers preloaded $00, condition code register preloaded with $68: Read stack pointer (SP+1) high byte (SP+1) byte Write (SP+1) byte
($0C)
($49, $00, [(SP+1) byte], $00) ($19, $68) ($19, $00) ($19, $00) ($19, $00) ($19, $A8) ($28)
Freescale Semiconductor, Inc.
Indexed write (SP+1) byte+1 Indexed write (SP+1) byte+2 Indexed write (SP+1) byte+3 Indexed write (SP+1) byte+4 Indexed write (SP+1) byte+5 Issue command.
Security Requirements
monitor security feature which requires host input correct string data before gain access control GP20. Without entering exact sequence data, which must match data contained locations $FFF6-$FFFD, access FLASH memory disabled. 8-byte data stream entered time after cycles have elapsed following rising edge reset. data timing constraints must conform same protocol stated previous section. monitor will echo each byte input after 1-bit time delay following byte entry must least times after transmission echoed byte. After eight bytes have been received, monitor sends break signal. received bytes match eight bytes FLASH, commands then sent processing. received bytes match those FLASH, monitor mode will continue, access FLASH
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Freescale Semiconductor, Inc. Application Note
denied. this case, attempt reference data FLASH will return indeterminate data, attempt execute from FLASH will result illegal address reset.
NOTE:
another security code sequence, remember power down then power microcontroller before sending data string.
Program Algorithm
Freescale Semiconductor, Inc.
program included this applications note loaded into, executed from, RAM. used fully partially erase FLASH then reprogram device while device running monitor mode. This monitor mode program from same program user mode program described Programming MC68HC908GP20 User Mode. assembled with MONMODE assembler directive signal that certain code specific monitor mode programming assembled. modes this program similar these respects: They both adhere same programming erasing constraints defined Program Algorithm. They both same modules, assembler directives, variables, constants. utilization almost identical programs. They both same message format described Programming MC68HC908GP20 User Mode.
primary differences are: Port used bidirectional communication monitor mode program instead SCI, both program loading well subsequent data downloading device memory dumps/acknowledgments. monitor mode program, course, conforms communication protocol dictated monitor, rather than direct message passing used user mode program.
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Application Note Host Program
monitor mode program assumes internal frequency 2.45 generate 9600 baud communication rate. frequency different from this, then baud rate will proportionately different. monitor mode program does contain module PLL, user mode program does, because built-in capability monitor turn Instead load routine residing FLASH copying necessary modules execution, monitor mode programs load program into from host with command available monitor mode. program first compiled S-record file generated which host program parses downloading proper addresses RAM.
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Host Program
host program monitor mode programming used this application note same that used user mode programming, that Windows-based program executed only difference that host into alternate mode which communicates with target device conformance with monitor mode protocol requirements. basic functions suitable host program, including used this application note, are: Allows entry eight security bytes sends them GP20 accordance with monitor mode timing requirements. Downloads file (FP4.S19) containing program that GP20 will utilize receive serial data, program FLASH, dump memory. This done with series indexed write instructions. Initiates execution program configuring data stack then issuing command.
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Freescale Semiconductor, Inc. Application Note
Loads S-record file with which program device. Alternatively, specifying data programmed from within program environment also supported. Provides control logic allow operator specify range FLASH programmed erased communicate program data GP20 conforming message protocol that program expects. Additionally, host should able provide verification data that programmed echoed back
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Conclusion
This application note describes method performing in-circuit serial programming FLASH memory MC68HC908GP20. same general approach followed initial device programming, when monitor mode must used, when re-programming device user mode. both situations, program loaded into, executed from, which facilitates serial communication data commands from host. There are, course, other ways implementing FLASH programming. often-asked question "How many wires does take program device?" Unfortunately, answer this question absolute, depends user's target system configured. best scenario, takes only three wires communicate with target program FLASH. This pre-supposes several existing configurable conditions: internal clock adequate generate acceptable data rate match host's. internal clock high enough create charge pump frequency close MHz. Programming voltage generated on-board applied when necessary (when block protection when reset vectors $00).
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Application Note Conclusion
Communication data levels ground potentials RS-232 level translation implemented on-board. initial (blank-part) programming reprogramming monitor mode, monitor mode requirements met.
these conditions cannot met, then off-board circuitry, usually form interface board, required number connections target board increases.
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This application note assumes that above conditions that available which serve host programmer. this case, then nothing else needed in-circuit serial programming.
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Freescale Semiconductor, Inc. Application Note
START MONITOR MODE USER MODE
INITIALIZE PORTS, DISABLE (MAIN FLASH)
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PORT SET?
CONFIGURE ENABLE (PLLINIT)
CONFIGURE SCI, FDIV MASK (SFINIT)
LOAD PROGRAMMING ROUTINES INTO (LDRAMPR)
RECEIVE DATA BLOCK, START ADDRESS (LDDATA)
PROGRAM DATA INTO FLASH STARTING ADDRESS SPECIFIED (PRGFLSH)
DUMP CURRENT DATA (DUMPROW)
Figure Main Program Flowchart
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Application Note Conclusion
START DECREMENT TRANSFER SIZE (XFERSIZE) BYTE CLEAR PORT
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FIRST ADDRESS REGISTER
XFERSIZE
BYTE SERIAL DATA FROM PTA0 FROM
DATASIZ BYTE
DATA
DATASIZE BYTE $7F?
ADDR ADDR? STORE DATA LOCATION SPECIFIED INCREMENT (DEST. ADDR. COUNTER)
ERASE FLASH
PROGRAM FLASH WITH RECEIVED DATA/ADDRESS (PRGFLSH)
DUMP THIS DATA (DUMPROW)
Figure LDDATA Routine Flowchart
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Freescale Semiconductor, Inc. Application Note
START FDIV BITS ALREADY FLCR; VALID ADDRESS WITHIN THIS RANGE LOADED
READ BLOCK PROTECTION REGISTER
STORE SIZE DATA ARRAY(DOWNLOADED) COUNTER BYTE
WRITE ANYTHING LOCATION WITHIN ERASED
Freescale Semiconductor, Inc.
LOAD DATA FIRST/NEXT ADDRESS
HVEN FLCR
DELAY TERA TIME ADDRESS ERASED? CLEAR HVEN FLCR
DELAY TKILL TIME INCREMENT ADDRESS COUNTER ADDRESS RANGE? CLEAR ERASE FLCR
DELAY THVD TIME
BLK1/BLK0 BITS ERASEAND ERASE FLCR
SUBROUTINE
Figure ERACHK Routine Flowchart
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Application Note Conclusion
START
FDIV MASK
WRITE FLCR WITH FDIV MASK
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PAGE PROGRAMMED ERASED
PAGE ERASED?
ERASE WHICH PAGE PROGRAMMED RESIDES
LOAD 1ST/NEXT BYTES DATA ARRAY INTO PROGRAM BUFFER
CALL PAGE PROGRAMMING ROUTINE (PRGPAGE)
LOAD 1ST/NEXT ADDRESS
PAGES DATA BUFFER PROGRAMMED?
SIGNAL PROGRAMMING VERIFICATION SUCCESS/FAIL
Figure PRGFLSH Routine Flowchart
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Freescale Semiconductor, Inc. Application Note
PRGPAGE PROGRAM PAGE; ADDR
PAGE?
VERIFY
LIMIT REACHED?
NUMBER PROGRAMMING ATTEMPTS
HVEN FLCR BYTES READ? REPROGRAM FLAG ADDRESS FIRST ADDRESS NEXT PAGE VERIFY FLAG STATUS BYTE
Freescale Semiconductor, Inc.
CLEAR REPROGRAM FLAG BYTECOUNT
DELAY TPGM TIME
FDIV BITS FLCR
CLEAR HVEN FLCR DELAY THVTV TIME
MARG FLCR READ FROM BLOCK PROTECT REGISTER
RELOAD WITH FIRST ADDRESS
RETURN
DELAY TVTP TIME
CLEAR MARG FLCR
LOAD BYTE DATA FROM BUFFER
CLEAR FLCR
REPROG FLAG SET? ADJUST ATTEMPT COUNTER COMPARE ATTEMPT LIMIT
WRITE DATA ADDRESS
DELAY THVD TIME
INCREMENT BYTECOUNT CHECK PAGE
READ BYTE DATA FROM PROGRAMMED PAGE COMPARE DATA BUFFER
Figure PRGPAGE Routine Flowchart
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Application Note Source Code FLASH Programming Program
Source Code FLASH Programming Program
LISTING NO.: FILE NAME: FP4.ASM PURPOSE: provide FLASH erase, program verify program TARGET DEVICE: HC908GP20 MEMORY USAGE RAM: 1A0H BYTES ROM: 280H BYTES ASSEMBLER: CASM08 VERSION: 1.02 PROGRAM DESCRIPTION: This program loads routine with instructions/data located FLASH memory that: Receives data over Port Row-erases FLASH block necessary Programs FLASH with received data Dumps specified comm port Bulk erases device upon command program assembler directives able program both user monitor modes. monitor mode, generated S-record file will contain necessary programming routines RAM. will have code that would reside RAM. user mode, load routines incorporated that could contained user's application. load routines load programming routines into from there looks just like routine executed monitor mode. AUTHOR: Grant Whitacre LOCATION: Austin, Texas UPDATE HISTORY: AUTHOR DATE DESCRIPTION CHANGE ============ ======== ===================== GRANT WHITACRE 03/04/98 INITIAL VERSION GRANT WHITACRE 04/15/98 SECOND VERSION (FP2.ASM)* LOADS RTNS INTO RE-ENTRY INTO FLASH NECESSARY. ALLOWS REPROGRAMMING ENTIRE FLASH ARRAY.
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Freescale Semiconductor, Inc. Application Note
GRANT WHITACRE 06/22/98 CONSOLIDATES PROGRAM ALLOW BOTH USER MODE MONITOR MODE PROGRAMMING SELECTABLE ASSEMBLER DIRECTIVES GENERAL CODING NOTES: names labeled with <port name><bit number> used commands that operate individual bits, such BSET BCLR. name followed indicates label that will used form mask. TESTING, ASSEMBLER SWITCH (TESTMOD) KEEP FROM TRIPPING ILLEGAL MEMORY WRITE BREAK DEBUGGER. OTHER SWITCHES INSTALLED EASE TESTING. ASSEMBLER DIRECTIVES (INCLUDES, BASE, MACROS, SETS, CONDITIONS, DEFS, ETC.) BASE ;DEFAULT BASE NUMBER DESIGNATION ;Remember: ACTIVE LOW!!!!!!!!!!!!!!!!!! MONPROG: SET, (NECESSARY) ROUTINES WILL ADDRESSED INITIALLY; THIS ;VERSION WOULD USED RECORD ;FILE THAT DOWNLOADED INTO ;MONITOR MODE FLASH PROGRAMMING sure manually addresses GET_PUT PUT_BYTE TESTMOD set!! TESTMOD: ;SINCE ILLEGAL WRITE ERROR ;USING MMDS WHEN WRITE ;EMULATED MEMORY, TESTMOD CAUSES READ ;FROM FLASH LOCATION INSTEAD WRITE COURSE VERIFY NEVER WORKS ;UNDER THESE CIRCUMSTANCES. TURN ;TEST MODE REAL TARGET EXECUTION. ERSDTST: ;SET FORCE GOOD VERIFICATION ;ERASED STATE
Freescale Semiconductor, Inc.
PORT REGISTER EQUATES PORTA ;I/O PORT PORTB ;I/O PORT PORTC ;I/O PORT PORTD ;I/O PORT PORTE ;I/O PORT ;BIT PORT
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Application Note Source Code FLASH Programming Program
****** DDRA DDRB DDRC DDRD DDRE
DATA DIRECTION
;BIT POSITION
Freescale Semiconductor, Inc.
REGISTERS ;PORT DATA DIRECTION REGISTER ;PORT DATA DIRECTION REGISTER ;PORT DATA DIRECTION REGISTER ;PORT DATA DIRECTION REGISTER ;PORT DATA DIRECTION REGISTER
****** CONFIG CONFIG1 COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC STOP COPD COPRS. LVISTOP. LVIRSTD. LVIPWRD. LVI5OR3. SSREC. STOP. COPD. ****** CONFIG CONFIG2 OSCSTOPEN SCIBDSRC SEC. OSCSTOPEN. SCIBDSRC.
REGISTER $001F ;CONFIG1 REGISTER REGISTER $001E ;CONFIG2 REGISTER ;Security ;Enable Oscillator during ;STOP mode ;SCI baud rate clock source ;BIT POSITION
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Freescale Semiconductor, Inc. Application Note
****** FLASH CONTROL REGISTER FLCR $FE08 ;FLASH CONTROL REGISTER FDIV1 FDIV0 BLK1 BLK0 HVEN VERF ;FOR 908GP20 ONLY MARG ;FOR 908XL36 ONLY ERASE FDIV1. FDIV0. BLK1. BLK0. HVEN. VERF. MARG. ERASE. PGM. ****** BLOCK PROTECTION REGISTER FLBPR $FF80 ;FLASH BLOCK PROTECTION ;REGISTER BPR3 BPR2 BPR1 BPR0 BPR3. BPR2. BPR1. BPR0. ****** REGISTERS SCC1 ;SCI CONTROL REGISTER LOOPS ;BIT ENSCI TXINV WAKE ILTY LOOPS. ;BIT POSITION ENSCI. TXINV. WAKE. ILTY.
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Application Note Source Code FLASH Programming Program
PEN. PTY. SCC2 TCIE ILIE TIE. TCIE. RIE. ILIE. RWU. SBK. SCC3 DMARE DMATE ORIE NEIE FEIE PEIE DMARE. DMATE. ORIE. NEIE. FEIE. PEIE. SCS1 SCTE SCRF IDLE SCTE. SCRF. IDLE.
;SCI CONTROL REGISTER ;Transmit interrupt enable ;Idle line interrupt enable ;Transmit enable ;Receive enable ;Receiver wakeup enable ;Send break
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;SCI CONTROL REGISTER ;Bit receive (for 9-bit characters) ;Bit transmit
;SCI STATUS REGISTER ;BIT
;BIT POSITION
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Freescale Semiconductor, Inc. Application Note
Freescale Semiconductor, Inc.
SCS2 BKF. RPF. SCDR SCBR SCP1 SCP0 SCR2 SCR1 SCR0 SCP1. SCP0. RES. SCR2. SCR1. SCR0.
;SCI STATUS REGISTER ;BIT
;BIT POSITION
;SCI Data ;SCI Receive Data (same SCDR) ;SCI Transmit Data (same SCDR) ;SCI BAUD RATE REGISTER ;SCI prescaler 00=clk/1, ;01=clk/3 ;SCI prescaler 10=clk/4, ;11=clk/13 ;SCI baud rate ;000=/1.111=/128 ;SCI baud rate sel, ;SCI baud rate sel,
APPLICATION-SPECIFIC MEMORY EQUATES VALUE CPUSPD DRIVES FDIV SETTING BAUD RATE PRESCALER SCI. MAKE SURE THAT CPUSPD USED. CPUSPD 2.45 OPER. FREQ. 4.92 MHZ, ABS. ADDRESS MONITOR ROUTINES COMMENTED TEST VERSION GET_PUT $FE97 ;MON BYTE ;PTA0 ECHO BACK
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Application Note Source Code FLASH Programming Program
PUT_BYTE MONRTNS RSTVLOC NXTPAGE STCKSIZ PRGSTRT LASTBYT NXFPAGE RAMPRG
$FEAA $B300 $FFFE $100 $F000 $F0F0 $F100 RAM+$58 $197 PRGSTRT+RAMPRG PRGSTRT+$240 $FFDC
;SEND BYTE PTA0 ;MONITOR ROUTINES INCLUDED ;PROGRAM TESTING ;RESET VECTOR LOCATION ;FIRST ADDRESS RAM, ACTUALLY ;$40 WILL START ;START FLASH PROGRAM ;START ROUTINE ;320 BYTES (MAX)
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RAMPRSZ TESTDAT XFRCODE STUBINT VECSTRT PRGTRIES
;PUT HERE ;SHOULD SAFE ;START USER VECTOR AREA ;MAX. NUMBER PROGRAM TRIES ;FULL ARRAY ;HALF ARRAY ROWS
MASKS ERASE RANGE FARMASK HARMASK RW8MASK ROWMASK
PROGRAMMING TIMES CHANGE THESE VALUES NECESSARY CHANGE TIMES! TIMES MICROSECONDS VTPGM 1000 ;1000 PROGRAM TIME VHLFTER 50000 ;1/2 ERASE TIME VTKILL ;HIGH-VOLTAGE KILL TIME VTHVD ;RETURN READ TIME VTHVTV ;HVEN VERF HIGH TIME VTVTP ;VERF HIGH TIME INTERMEDIATE PROGRAMMING TIMES (CALCULATION PURPOSES ONLY) CTPGM (VTPGM/6) ;DIVIDE HERE NORMALIZE CHLFTER (VHLFTER/6) ;FOR NEXT STEP. PADDED FROM CTKILL (VTKILL/6) COMPENSATE CTHVD (VTHVD/6) ;FREQUENCIES (2.45 4.92 MHZ) CTHVTV (VTHVTV/6) ;AND TRUNCATION. CTVTP (VTVTP/6) SPEED-CORRECTED PROGRAMMING TIMES (TIMES ACTUALLY USED) TPGM (CPUSPD*CTPGM) ;Program time 1000 HLFTERA (CPUSPD*CHLFTER) ;Half Erase time TKILL (CPUSPD*CTKILL) Kill time THVD (CPUSPD*CTHVD) ;Return read time THVTV (CPUSPD*CTHVTV) ;HVEN VERF high time TVTP (CPUSPD*CTVTP) ;VERF high time
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EQUATES PLLCHK
;PLL CHECK PORT ;PLL ;PLL ;PLL ;PLL ;PLL ;PLL Control Register Bandwidth Control Register Multiplier Select Register High Multiplier Select Register Range Select Register Reference Divider Select Register
908GP20 REGISTERS PCTL $0036 PBWC $0037 PMSH $0038 PMSL $0039 PVRS $003A PRDS $003B
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Initial Settings 32.768 crystal clock produce 2.4576 *internal clock ;PLL Prescaler Program Bits (PRE) ;value PCTL (def ;PLL Power-of-Two Range Select Bits ;(VCR) value PCTL (def ;PLL Multiplier Select Bits (MUL) ;value PMSH (def ;PLL Multiplier Select Bits (MUL) ;value PMSL (def ;PLL Range Select Bits (VRS) ;PLL Reference Divider Select Bits ;(RDS) value PRDS (def=1) value ;interpreted AUTO ;Bit PBWC LOCK ;Bit PBWC PLLON ;Bit PCTL ;Bit PCTL VARIABLE DEFINITIONS SPACE USAGE $40-$4F USED BYTES) TRANSFER SIZE BYTE) $51-$52 FIRST ADDRESS PROGRAMMED( BYTES) DATA SIZE (DATASIZ) BYTE) $54-$93 DATA ARRAY BYTES) $94-$A7 VARIABLES BYTES) $A8-$EF PROGRAM BYTES) $F0-$FF STACK BYTES) $100-$23F PROGRAM (320 BYTES) $50-$23F TOTAL (512 BYTES) XFRSIZE FRSTADR DATASIZ DATARAY DATA1 REPROG TEMPH TEMPL TEMP2 ;NUMBER BYTES TRANSFERRED ;FIRST ADDR PROGRAMMED ;NUMBER BYTES PROGRAM ;RESERVE BYTES DATA ;DATA PROGR. PAGE-8 BYTES HERE SIGNALS NEED REPROGRAM ;RAM COUNTER BYTE) ;RAM COUNTER (LOW BYTE) ;TEMP. HOLDING LOC. TRANSFERS/PR ;TRIES
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Application Note Source Code FLASH Programming Program
;FDIV FLCR MASK ;BYTE COUNT USED DURING PAGE PROG. ;INDEX INTO DATA ARRAY ;CURRENT BYTE BEING READ/WRITTEN (0-7) ;STATUS PROGRAM SUCCESS ;BIT FAILED; SUCCEEDED Program Algorithm (User Mode Programming) Initialize variables ports, selected) SCI. Monitor port input block data programmed start address. Load with data array bytes), start address length data array. Transfer following subroutines address RAMPRG LDDATA MAINPRG ERABLK DELNUS PRGPAGE Jump first byte main program (RAMPRG). Execute program MAINPRG then return port monitoring loop RAM. Program Algorithm Monitor Mode Programming Monitor PTA0 input block data programmed start address. Load with data array bytes), start address length data array. Execute program MAINPRG then return PTA0 monitoring loop RAM. START PROGRAM IFNE MONPROG PRGSTRT START PORTA PORTB #$02,DDRB ;USING PTB1 outPUT INIT. #$31,CONFIG1 ;DISABLE BRSET PLLCHK,PORTB,STFDV ;(IF THEN OFF) PLLINIT STFDV SFINIT ;SET FDIV BITS ACCORDING SPEED ;ALSO INITIALIZES LDRAMPR ;LOAD ENTIRE PROGRAM testing code FLASH retain labels, then take following jump. XFRCODE ;LOAD DATA INTO FROM .otherwise jump execute RAMPRG
FDIVMSK BYTECNT ARAYIDX CURRBYT STATBYT
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Freescale Semiconductor, Inc. Application Note
NAME: PLLINIT PURPOSE: INITIALIZES ENTRY CONDITIONS: NONE EXIT CONDITIONS: NONE SUBROUTINES CALLED: EXTERNAL VARIABLES USED: DESCRIPTION: EXECUTED FLASH FOLLOWING INITIALIZES 2.4576 INTERNAL CLOCK BASED 32.768 EXTERNAL CRYSTAL CLOCK CREATE STANDARD BAUD RATE (9600) COMMUNICATION ACCEPTABLE CHARGE PUMP FREQUENCY. PLLINIT: Instruction Setup 32.768 2.4576 bytes total) 2CH, PVRS(L) PCTL ;turn default) BSET 0,PCTL ;set (VPR0=1) BSET 0,PMSH byte) #NLO,PMSL byte) predefined #L,PVRS ;bit default, L=80H BSET PLLON,PCTL BSET AUTO,PBWC ;put auto bandwidth mode BRCLR LOCK,PBWC,* BSET BCS,PCTL TEST CODE SETUP Following tests above settings internal clock desired rate. Internal clock rate frequency sensed port *TESTPLL BSET 1,DDRB ;bit output *BITOFF BCLR 1,PORTB cycles cycles *BITON BSET 1,PORTB cycles BRCLR 0,PORTB,BITOFF CYCLES cycles NAME: SFINIT PURPOSE: INITIALIZES DATA RECEPTION; INITIALIZES FDIV BITS ENTRY CONDITIONS: EXIT CONDITIONS: SUBROUTINES CALLED: EXTERNAL VARIABLES USED: DESCRIPTION: EXECUTED FLASH DATA SHOULD FORM START-BIT, DATA-BITS, STOP-BIT. BAUD RATE 9600, BASED CPUSPD SFINIT BSET SCIBDSRC,CONFIG2 #CPUSPD ;SET FDIV MASK CURRENT SPEED LSLA
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Application Note Source Code FLASH Programming Program
NOT8MH
NOT4MH XSCINIT
LSLA BSET
NOT8MH #$30,SCBR #$C0,FDIVMSK XSCINIT NOT4MH #$03,SCBR #$80,FDIVMSK XSCINIT #$02,SCBR FDIVMSK ENSCI,SCC1 #$0C,SCC2
;fX/64/9600 (SCBR=$30)
;fX/64/9600 (SCBR=$03) ;fB/64/9600 (SCBR=$02) ;TURN ;SET SCCR2 INITIAL VALUE ;TURNS
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NAME: LDRAMPR PURPOSE: LOADS MAIN PROGRAM NEC. SUBROUTINES ENTRY CONDITIONS: NONE EXIT CONDITIONS: NONE SUBROUTINES CALLED: EXTERNAL VARIABLES USED: DESCRIPTION: EXECUTED FLASH LDRAMPR LDHX #RAMPRG ;STORE START LOCATION STHX TEMPH ;WHERE CODE TRANSFERRED LDHX #XFRCODE ;LOAD ADDR FLASH CODE NXTMOVE X+,TEMP2 ;TRANSFER LOCATION PSHH PSHX ;PUSH CURRENT FLASH ADDDR STACK LDHX TEMPH ;LOAD ADDRESSES THAT HOLD DEST. TEMP2,X+ ;TRANSFER DATA FROM TRANSFER LOCATION NEXT STHX TEMPH CPHX #RAMPRG+RAMPRSZ NEXT LOCATION DESTINATION PULX ;POP CURRENT FLASH ADDR FROM STACK PULH XLDRAMP CPHX #LASTBYT ;SEE DESTINATION LAST BYTE NXTMOVE PAGE INCREMENT LDHX #NXFPAGE PSHH ;DEST. REGISTERS (TEMPH-TEMPL) PSHX ;THE VALUE STACK SIZE (STCKSIZ) LDHX TEMPH LDHX #NXTPAGE STHX TEMPH PULX PULH NXTMOVE DONE, CONTINUE XLDRAMP ENDIF
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Freescale Semiconductor, Inc. Application Note
START CODE TRANSFERRED IFNE MONPROG XFRCODE ENDIF
;CURRENTLY $B0A8
START MONITOR PROGRAM WHICH WE'LL IFEQ MONPROG RAMPRG ;CURRENTLY START: ENDIF NAME: LDDATA PURPOSE: LOAD WITH USER'S DATA START ADDRESS SCI; PROGRAMS THEN DUMPS DATA THAT DOWNLOADED; ONLY DUMPS DATA SPECIFIED NUMBER BYTES PROGRAMMED (DATASIZ) ENTRY CONDITIONS: EXIT CONDITIONS: SUBROUTINES CALLED: PRGFLSH, DUMPROW EXTERNAL VARIABLES USED: DESCRIPTION: EXECUTED STRUCTURE DATA RECEIVED FOLLOWS: LOCATION DESCRIPTION LOC. ======== ======== COUNT TOTAL NUMBER BYTES SENT (INCL. THAT BYTE) FIRST ADDRESS WHERE $41-$42 FOLLOWING DATA PROGRAMMED NUMBER BYTES PROGRAMMED 5-68 ARRAY SPACE DATA PROGRAMMED $44-$83 COUNT USED THAT GREATER THAN (PROGRAM LENGTH THEN ROUTINE WILL HANG AFTER LAST PROGRAM BYTE SENT. CONTINUOUSLY LOOPS LOOKING DATA SCI. MUST RESET AFTER LAST DOWNLOAD. DATA ARRAY RECEIVED WITH NUMBER BYTES PROGRAMMED THEN PROGRAM WILL CONSTRUE THIS SIGNAL ERASE ENTIRE ARRAY. THIS MOST CONVENIENT IMPLEMENT BULK ERASE WITHOUT HAVING HAVE COMMAND BYTE DATA STRUCTURE. LDDATA CLRH CLRA #RAM ;POINT START IFEQ MONPROG FDIVMSK ENDIF WAITRX: IFEQ MONPROG ENDIF IFNE MONPROG BRCLR ENDIF AN1770 Rev. More Information This Product, www.freescale.com MOTOROLA SCRF,SCS1,* SCS1 SCDR ;WAIT ;PART ;PART ;READ REGISTER FILL CLEARING SCRF CLEARING SCRF DATA BYTE FROM REGISTER GET_PUT
Freescale Semiconductor, Inc.
Application Note Source Code FLASH Programming Program
CHKCHK
STORNOW
TSTA INCX DBNZ CLRA
#RAM STORNOW WAITRX RAM,WAITRX DATASIZ DUMP JUSTPRG #FARMASK JERASE DUMP PRGFLSH DUMPROW LDDATA
VALUE BYTE ZERO, THEN ;BAD START KEEP LOOPING NON;ZERO FIRST BYTE ;STORE DATA ;MOVE NEXT LOCATION ;DEC. PROG SIZE CNTR (1st BYTE) ENTIRE PROG LODED, CONT. SIZE DATA PROGRAMMED THEN ONLY DUMP THIS ROW.
;ERASEIT
Freescale Semiconductor, Inc.
JUSTPRG DUMP
NAME: DUMPROW PURPOSE: DUMPS ENTIRE 64-BYTE THAT START ADDR ENTRY CONDITIONS: CONTAINS NEXT ADDR PROGRAMMED EXIT CONDITIONS: NONE SUBROUTINES CALLED: ERACHK EXTERNAL VARIABLES USED: DESCRIPTION: EXECUTED DUMPROW LDHX FRSTADR ;PUT FIRST ADDR #$C0 ;PUT BOUNDARY RDBYTE WAITTX IFEQ MONPROG ENDIF IFNE MONPROG BRCLR PSHA PULA ENDIF INCX ;MOVE NEXT ADDRESS #$3F RDBYTE FINISHED, CONTINUE SCTE,SCS1,WAITTX SCS1 SCDR ;SEND EEPROM DATA SERIAL OUTPUT ;WAIT TRANSMIT REG. EMPTY PUT_BYTE ;SEND PTA0
ENDDUMP
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Freescale Semiconductor, Inc. Application Note
FOLLOWING RELOCATABLE, DEPENDING WHERE PAGE BREAK STACK LOCATED. MUST PLACE THAT BRANCH NEXT PAGE LEAST PAST $FF. JERASE ERASEIT ;NEED BRANCH HERE LASTBYTE LASTBYTE+STCKSIZ ;STCKSIZ NEEDS EQUATE NAME: PRGFLSH PURPOSE: ERASES NECESSARY), PROGRAMS DATA DATA ARRAY LOCATION SPECIFIED, THEN VERIFIES. DATA MUST WITHIN BOUNDARY. ENTRY CONDITIONS: NONE EXIT CONDITIONS: NONE SUBROUTINES CALLED: JERACH (ERACHK), JPRGPAG (PRGPAGE) EXTERNAL VARIABLES USED: DESCRIPTION: EXECUTED FLASH PROGRAMMING ALGORITHM LOAD FIRST ADDRESS; CLEAR BYTCNTR ADDRESS PAGE BOUNDARY. NOT, LOAD EXISTING DATA FROM CORRECT LOCATIONS FLASH FILL BEGINNING PAGE. LOAD DATA FROM DATA BUFFER FILL (REST PAGE UNTIL DATA ARRAY REACHED, WHICHEVER COMES FIRST. DATASIZ ENOUGH COMPLETE CURRENT PAGE, THEN LOAD EXISTING DATA FROM CORRECT LOCATIONS FLASH FILL PAGE. INCREMENT BYTECNT ACCORDING MANY BYTES DATA WERE USED CURRENT PAGE. PROGRAM PAGE WITH EIGHT BYTES LOADED DATA. PERFORM VERIFICATION CHECK PAGE PROGRAMMED. NOT, THEN SEND HIGH "VERIFICATION FAILED" PORT RETURN FLASH. CHECK BYTECNT DATASIZ. THEN RETURN FLASH. NOT, THIS ROUTINE CHECKS FIRST ADDRESS DATA PROGRAMMED PAGE BOUNDARY, LAST ADDRESS DATA PROGRAMMED PAGE. SINCE PROGRAM WHOLE PAGES TIME, WE'LL JUST REPROGRAM THOSE BYTES PAGE BEFORE FIRST ADDRESS NECESSARY) THOSE BYTES PAGE AFTER LAST ADDRESS NECESSARY) WITH VALUE THAT ALREADY EXISTS THERE FLASH. PRGFLSH BSET 1,PORTB CLRA FDIVMSK FLCR ERACHK BYTECNT LDHX FRSTADR PSHX PSHH
Freescale Semiconductor, Inc.
AN1770 Rev. More Information This Product, www.freescale.com MOTOROLA
Application Note Source Code FLASH Programming Program
NOSTUFF FOLLOWING LOADS REST NXTLOAD CLRH
BYTES INTO DATA BUFFER ARAYIDX ARAYIDX DATASIZ ;SEE DATA ;ARRAY BEEN LOADED
NOMODAT DATARAY,X ;WHERE CONTAINS INDEX INTO ARRAY ARAYIDX BYTECNT DATA1,X INCX BYTECNT NXTLOAD PULH PULX JPRGPAG PSHX PSHH BYTECNT NXTLOAD NOMODAT PULH PULX NAME: ERACHK PURPOSE: CHECKS RANGE PROGRAMMED NEEDS ERASED FIRST, ERASES NECESSARY. ERASE BITS (BLK0, BLK1) FDIV BITS ALREADY FPCR; VALID ADDRESS THIS RANGE LOADED H:X. THIS ROUTINE DOES VERIFY ERASE, THEN NUMBER ATTEMPTS RE-ERASE. MAYBE LATER ENOUGH ROOM. ENTRY CONDITIONS: NONE EXIT CONDITIONS: NONE SUBROUTINES CALLED: DELNUS EXTERNAL VARIABLES USED: DESCRIPTION: EXECUTED RANGE PROGRAMMED ALREADY ERASED, THIS ROUTINE WILL AUTOMATICALLY ERASE THAT THIS DATA ERACHK DATASIZ,BYTECNT ;WANT KEEP THIS VALUE ;USED COUNTER HERE LDHX FRSTADR ;LOAD FIRST ADDR NXTCHK ;LOAD DATA THIS ADDR IFEQ ERSDTST CLRA ENDIF ERAROW ZERO, THEN ERASE DBNZ BYTECNT,NXTCHK XERACHK ERAROW CLRA #ROWMASK ERASEIT LDHX FRSTADR ;RELOAD ADDRESS CASE ENTRY ERASEIT
Freescale Semiconductor, Inc.
AN1770 Rev. MOTOROLA More Information This Product, www.freescale.com
Freescale Semiconductor, Inc. Application Note
ENDIF IFNE TESTMOD ENDIF LDHX LDHX LDHX LDHX LDHX LDHX LDHX #FLCR #HVEN. #HLFTERA DELNUS #HLFTERA DELNUS #FLCR #HVEN. #TKILL DELNUS #FLCR #ERASE. #THVD DELNUS PRGPAGE ;FOLLOWING SETS HVEN FLCR FDIVMSK #ERASE. FLCR FLBPR
;SET FDIV MASK BASED SPEED
ERABLK IFEQ TESTMOD
Freescale Semiconductor, Inc.
;DELAY TERA ;DELAY TERA ;CLEARS HVEN
;DELAY TKILL ;CLEAR ERASE
;DELAY THVD ;NEEDED STAY RANGE
XERACHK JPRGPAG
NAME: DELNUS PURPOSE: DELAY ENTRY CONDITIONS: CONTAINS TIME DELAY µs.) EXIT CONDITIONS: PRESERVES CONTENTS SUBROUTINES CALLED: NONE EXTERNAL VARIABLES USED: DESCRIPTION: EXECUTED DELNUS PSHA PSHH PULA FOLLOWING LOOP EXECUTES NUMBER TIMES; 99.6% TIME THIS LOOP CYCLES DURATION WHICH D1US TSTX ;(1) NOADEC ;(3) TSTA ;(1) XDELNUS ;(3) DECA ;(1) NOADEC DECX ;(1) D1US ;(3) XDELNUS PULA ;(4) RETURN AFTER WANTED DELAY AN1770 Rev. More Information This Product, www.freescale.com MOTOROLA
Application Note Source Code FLASH Programming Program
NAME: PRGPAGE PURPOSE: PROGRAMS PAGE BYTES) FLASH ENTRY CONDITIONS: REG. LOADED WITH FIRST ADDRESS PROGRAMMED; DATA1-DATA8 BEEN LOADED EXIT CONDITIONS: NONE SUBROUTINES CALLED: DELNUS EXTERNAL VARIABLES USED: DESCRIPTION: EXECUTED PRGPAGE PSHA ;(A) SAVE CONTENTS ACCUMULATOR #PRGTRIES,TEMP2 PRGLOOP REPROG FDIVMSK ;SET FDIV MASK CURRENT SPEED #PGM. ;SET FLCR ;WRITE THIS FLASH CONTROL REG. FLBPR ;READ FROM BLOCK PROT. REG. PSHH ;(B) PSHX ;(C) PUSH BYTE ADDR STACK BYTECNT ;SET BYTE COUNT CLRX LDNOTHR CLRH DATA1,X PULX ;(C') BYTE ADDR BACK INTO PULH ;(B') IFEQ TESTMOD ;READ INSTEAD WRITE DURING TESTING PREVENT ILLEGAL ADDRESS ACCESS ENDIF IFNE TESTMOD ;STORE DATA ADDR SPEC. ENDIF #$01 ;INCREMENT ADDRESS PSHH ;(B) PUSH BYTE ADDR BACK STACK PSHX ;(C) BYTECNT ;INCREMENT BYTE COUNTER BYTECNT ;LOAD WITH BYTE COUNT #$08 LDNOTHR PULX PULH PSHH PSHX LDHX #FLCR ;FOLLOWING SETS HVEN FLCR #HVEN. PSHX ;(D) PUSH FLCR BYTE) STACK PSHH ;(E) PUSH FLCR BYTE) STACK LDHX #TPGM DELNUS ;FOLLOWING CLEARS HVEN PULH ;(E') FLCR BYTE) FROM STACK PULX ;(D') FLCR BYTE) FROM STACK #HVEN.
Freescale Semiconductor, Inc.
AN1770 Rev. MOTOROLA More Information This Product, www.freescale.com
Freescale Semiconductor, Inc. Application Note
PSHX PSHH LDHX ;(D) PUSH FLCR BYTE) STACK ;(E) PUSH FLCR BYTE) STACK #THVTV DELNUS ;DELAY THVTV ;SET MARG ;(E') FLCR BYTE) FROM STACK ;(D') FLCR BYTE) FROM STACK ;(D) PUSH FLCR BYTE) STACK ;(E) PUSH FLCR BYTE) STACK ;DELAY TVTP
Freescale Semiconductor, Inc.
HALFBRA CLRPGM PULH
PULH PULX #MARG. PSHX PSHH LDHX #TVTP DELNUS CLRPGM PRGLOOP PULX LDHX
;CLEAR ;(E') FLCR BYTE) FROM STACK ;(D') FLCR BYTE) FROM STACK #PGM. #THVD DELNUS
;DELAY THVD WITH DATA1-DATA8 ;(C') ADDR (LO-B) STACK ;(B') ADDR (HI-B) STACK ;NOW READ DATA STORE THEM ;DEC THIS ADDR BEFORE PUSHING ;(B) PUSH ADDR (LO-B) STACK ;(C)
READ WHAT'S BEEN PROGRAMMED CHECK BYTECNT ALREADY LEAVE PULX PULH #DATA1+7,CURRBYT RDNOTHR DECX PSHX PSHH CLRH CURRBYT PULH PULX FAILVER CURRBYT DBNZ BYTECNT,RDNOTHR PASSVER FAILVER #$01,REPROG PASSVER INCX PSHH PSHX LDHX #$F8
;(C') ;(B') ADDR (LO-B) STACK ;DECREMENT BYTE COUNTER ;STORE VALUE REPROG SIGNAL ;REPROG PAGE ;PUT ADDR BYTE THIS PAGE ;INTO REGARDLESS FAIL/PASS ;(B) PUSH ADDR (LO-B) STACK ;(C) ;FOLLOWING CLEARS MARG FLCR
#FLCR #MARG. REPROG
AN1770 Rev. More Information This Product, www.freescale.com MOTOROLA
Application Note Source Code FLASH Programming Program
PTPA
PASSED FAILJMP XPRGPAG ENDRAMP
PULX PULH PULX PULH PULA
PASSED TEMP2 HALFBRA FAILJMP ;(C') ADDR (LO-B) STACK ;(B') ADDR (HI-B) STACK ;TRY AGAIN ;(C') ;(B') ;INDEX NEXT PAGE ;(A') RESTORE ACCUM
Freescale Semiconductor, Inc.
IFNE MONPROG INTERRUPT SERVICE ROUTINES STUBINT CLRINT INTERRUPT RESET VECTORS RSTVLOC RSTVEC START ENDIF ;PUT HERE TAKE VECTOR MONPROG FILE
AN1770 Rev. MOTOROLA More Information This Product, www.freescale.com
Freescale Semiconductor, Inc. Application Note
Freescale Semiconductor, Inc.
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
reach USA/EUROPE/Locations Listed: Motorola Literature Distribution, P.O. 5405, Denver, Colorado 80217, 1-800-441-2447 1-303-675-2140. Customer Focus Center, 1-800-521-6274 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 03-5487-8488 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd., Ping Industrial Park, Ting Road, N.T., Hong Kong. 852-26629298 MfaxTM, Motorola Back System: RMFAX0@email.sps.mot.com; http://sps.motorola.com/mfax/; TOUCHTONE, 1-602-244-6609; Canada ONLY, 1-800-774-1848 HOME PAGE: http://motorola.com/sps/
Mfax trademark Motorola, Inc. Motorola, Inc., 1999
AN1770/D More Information This Product, www.freescale.com

AN1770 Freescale Semiconductor, Inc. In-Circuit Programming

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