Application Note Designing Minimal System Gary Milliorn Moto

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Application Note Designing Minimal System Gary Milliorn Moto

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AN1769/D REV. 1/1999
Application Note
Designing Minimal System
Gary Milliorn Motorola RISC Applications risc10@email.sps.mot.com This application note describes design small, high-speed Motorola PowerPCprocessor based system. this document, terms used denote 32-bit microprocessor from architecture family that conforms interface PowerPC PowerPC PowerPC microprocessors, respectively. MPC60x MPC7xx processors implement PowerPC architecture 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types bits, data types bits (single-precision double-precision). This document contains following topics:
Topic Page
Part Part Part System Part Part Part Part
This document contains information product under development Motorola IBM. Motorola reserve right change discontinue this product without notice.
Motorola, Inc., 1999. rights reserved.
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Part Part Part
locate published errata updates this document, refer website
Part Introduction
keep design simple, only most basic features necessary debugger program included. These features follows: PowerPC processor (this includes MPC603e, MPC603ev, MPC604, MPE603e, MPE603ev, MPE604, MPC740 MPC750) Flash storage (start-up code) Read/write memory (downloaded code, program variables) Serial channel (communication) Memory controller Power, clocks reset
While this application note general focus, will also occasionally diverge order describe implementation details actual board, known which implements basic techniques described this application note. details Excimer provide base upon which build design, with general sections describing ways support customization.
Design Philosophy
PowerPC high-performance family (MPC60x MPC7xx) interface appear intimidating presence split address/data tenuring, snooping, multiprocessing support, cache coherency support, other advanced features. Such features used obtain additional performance high-performance systems, purposes small, high-speed embedded controller (particularly with only master), many these complications avoided. Since processor does contain internal memory controller interface, that role traditionally fallen Motorola MPC106 memory/PCI/cache controller. small board such outlined here, MPC106 much more than minimally needed. Indeed, complexity sometimes reduce performance. Cache coherency instructions valuable cycles, allowing access external masters (such cache) requires delaying memory cycles case external device claims cycle. Instead, this design, programmable ASIC used provide necessary controls block RAM, access I/O. controller programmable software instead hardware, memory access cycles tuned provide only necessary signals. With these restrictions goals, typical block diagram resemble that shown Figure
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Power LTC1585
Reset DS1834
Processor Motorola MPC60x, MPC7xx, MPE60x, MPC7xx
Clock Motorola MPC904
(optional)
Memory Controller Lattice 2096V
Main Memory Motorola MCM69P737 512K PBSRAM
Start-up Code Motorola 29F800 Flash
Serial Port Lattice 16550 UART
Port Motorola 74LCX245
Figure Typical Minimal System Block Diagram
Conventions
Various conventions used this document follows: SIGNAL SIGNAL signal signal_L name() Active-high external signal (pin). Active-low external signal (pin). Active-high internal signal (net); used when describing memory controller. Active-low internal signal (net); used when describing memory controller indicates active internal signals). block code implementing function.
Occasionally, name have both forms; example, hardware signal detected fragment code which refers
Part Processor Design
processor member MPC60x MPC7xx family. such devices offer 64-bit modes, MPC603x parts also offer 32-bit interface which make memory design even simpler cost speed. Since only MPC603x parts support this mode, will used this design should kept mind where number parts cost even more important than speed. Since high-performance PowerPC processors very similar interfaces, choice processor based cost performance issues interface costs. simple system with only master, many signals processor ignored wired desired state; refer Table more information.
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Table PowerPC Signal Connections1
Signal APE, CKSTP_OUT, CLKOUT, DPE, HALTED, QREQ, RSRV, TMS, TDI, TDO, VOLTDETGND, CKSTP_IN, DBWO, DBDIS, DRVMOD1, RUN, SHD, SRESET, TBEN, TLBISYNC, XATS L1_TSTCLK, LSSD_MODE ABB, ARTRY, DBB, GBL, L2_TSTCLK,TCK DBG, DRVMOD0, L2_INT Treatment Unused, leave unconnected.
Unused, pullup connect (+3.3V).
Unused, connect directly (+3.3V). Unused, connect pullup (+3.3V). Connect ground. Connect HRESET Connect pulldown ground. Connect (+3.3V) ground speed. Connect pullup (+3.3V) and/or interrupt controller. Connect appropriate voltage level. Connect shown hardware reference manual. Connect reset controller. Connect reset controller, connect pulldown (GND). Connect clock generator. Connect memory controller.
DRTRY QACK INT, MCP, VDD, OVDD AVDD, L2AVDD HRESET2 TRST2 SYSCLK2 AACK, TEA, TBST,
Connect memory devices.
This table combines MPC603x, MPC604x, MPC750 processors. these signals present every device. These signals only ones that need consideration minimal system design. others assigned values safely ignored thereafter.
MPC750 additional signals interfacing with back-side cache L2CE, L2WE, L2CLK_OUTA, L2CLK_OUTB, L2SYNC_OUT, L2SYNC_IN, L2ZZ). Because interface completely separate from system bus, does affect design minimal system way. Refer MPC750 RISC Microprocessor Hardware MPC750 Processor/Cache Module Hardware Manual, further details.
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Part Memory System Design
fairly complicated portion minimal system interface processor data bus. Unlike CISC processors, RISC processors typically perform data (re)alignment, data from each external device must placed proper data lane. attempt 8-bit memory device supply instructions data 64-bit data bus, 8-bidirectional latching transceivers must used move byte correct byte lane 64-bit bus, shown Figure
Latch
Latch
Latch 8-bit Memory Device
MPC60x
Latch
Latch
Latch
Latch
Latch Memory Controller
Figure Byte Lane Redirection
Because processor expects from eight bytes each (non-burst) transfer, memory controller must generate from eight memory cycles 8-bit memory generating address(es), latching resulting data, then presenting processor with signal. This process must reversed when writing memory. This take amounts logic, approach taken MPC106 interface, example. this minimal system, will instead take approach that memory 64-bits wide. using 32-bit pipelined-burst SRAM main memory 16-bit Flash EPROM start-up code, only components will needed, controlling logic will simple inexpensive, bonus SRAM will allow very fast memory access speeds. SRAM main memory become more attractive speed size increases price falls. Currently SRAM devices commodity components their caches PCs; even 100-MHz parts terribly expensive. minimal system block diagram shown Figure
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Space MPC60x
A(0:31)
D(0:63) TSIZ TBST
AACK
16-bit FlashROM (4X)
ADSC
BWE(0:7)
32-bit Pipelined Burst SRAM (2X)
Memory Controller
Figure Minimal System Memory Architecture
system address shown Table
Table Excimer Address
Address Devices Start Fast Slow Flash 0x0000_0000 0x4000_0000 0x8000_0000 0xC000_0000 0x3FFF_FFFF 0x7FFF_FFFF 0xBFFF_FFFF 0xFFFF_FFFF Burstable? Access Cycles 3-1-1-1
only challenging design problem faced handling burst transfers. MPC60x family operate with caches disabled, thus preventing burst transfers, this typically exacts terrible penalty performance that makes additional effort handling them well worthwhile. step designing memory controller (abbreviated code) determine types controls that will needed among proposed memory EPROMs, SRAM general I/O.
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SRAM Memory Controls
SRAM interface centered around controls necessary typical pipelined burst SRAM memory, used MPC750 back-side cache various other cards. Flow-through SRAM memories could also used, timing write operations would change. Since this simple memory controller, will architected only type SRAM. Most SRAM devices have numerous controls which needed, leaving with following: ADSC BWE(a-d) Memory address, including burst transfers critical-word Addresses LSBs used burst transfer addresses. Latches address single-beat burst transfers Increments address burst transfers Active-low byte-write enables; asserted, cycle burst read. Active-low output enable; asserted read operations. Active-low chip enable; asserted operations.
memory controller must generate these signals SRAM transfers, whether single-beat burst transfers. ADSC start cycle latching address into SRAM; these must provided memory controller same time. Since asserted clock after address matches SRAM space, memory controller also asserts ADSC memory cycles. signals corresponding size transfer must asserted cycle write cycle; otherwise, must asserted read data (all byte lanes driven processor selects data from whichever byte lane needed). remaining signal ADV, which must asserted three clock cycles burst transfer selected; otherwise, remains high. Although data rate could throttled with this necessary processor, simplify design, only fast SRAMs will accommodated. remaining portion SRAM controller specify initial access time. Most SRAMs available today decode address within from address strobe (ADSC), there need delay before beginning transfer.
ADSC ADSP
MPC750
MCM69P737
ADSC
ADSC
ADSP
Memory Controller
MCM69P737
Figure Pipelined Burst SRAM Memory Connections
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Note that since allow overlapped address data tenures, know whether next transfer same SRAM page not, cannot stream data (that 3-1-1-1/1-1-1-1/. cycles). This requires much more logic left exercise reader. issue which must handled terminating access. Burst operate streaming data into chip each clock edge after initial setup sequence (ADSC), until instructed stop. While read operations ignored forcing high, write operations cannot similarly controlled, instead cycle must performed after each access. This done asserting ADSC without chip select asserted; when deselected, SRAM will stop reading writing data.
Flash Memory Controls
Flash memory devices traditional signals perform single-beat read write cycles (burst transfers permitted1), whether data width device 8-bits 16-bits. Since PowerPC does care data placed ignored byte lanes during read cycles, will acceptable common ROMs. Write cycles require more care. Requiring processor perform 64-bit writes unacceptable because (that requires unit devices) impossible devices) 64-bit single-beat transfer. Thus, devices must with byte-enables during write cycles. Using standard devices will require following control signals: Active-low byte-write enables; asserted, cycle read. Active-low output enable; asserted read operations. Active-low chip enable; asserted operations.
This gives memory architecture shown Figure
BWE0 BWE2
M29F800 (16-bit)
BYTE
3.3V
M29F800 (16-bit)
BYTE
3.3V Remember: 3.3V Devices ONLY!
BWE4
M29F800 (16-bit)
BYTE
3.3V
BWE6
M29F800 (16-bit)
BYTE
3.3V
Figure Flash Memory Connections
This implies that space non-cacheable; since Flash much slower than SRAM, critical code should copied SRAM, this considered performance limitation.
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Note that 16-bit devices have been used. This helps reduce number components, cost restricting writes bits size. 8-bit writes required, then either 8-bit devices must used, devices which have multiple byte enables. further restriction memory that reading slow (from ns), writing even slower much ms). memory controller delays assertion number cycles access match read time; this handles read access properly gives time device begin program operation (the data does need held throughout write cycle). Software must insure that proper amount time elapsed after write before another read write occurs. This done with simple timing loop, using check RDY/BSY signals, devices which queried reading special addresses.
Controls
Most simple devices such real-time clocks, serial ports, other unique interfaces have fairly simple chip select, output enable, write control. controller then modeled very closely controller; both have simple controls both relatively slow. difference between that most devices perhaps bits, devices must attached particular byte lanes. controller responds size write, data placed byte lane (software responsible positioning retrieving data properly). fairly easy controller allows different times each address decoded, allowing fast slow devices mixed. Note that write strobes/direction control same byte write enables that have been described before. This reuse will allow reduction size complexity controller, also means that software must generate correct address when performing writes devices greater than bits wide. example, Figure 16-bit device attached uses BWE1, access controller, software must issue 32-bit writes aligned with controller will assert BWE1 (all others ignored).
BWE0 XCS0
Remember: 3.3V Devices ONLY!
Device
BWE1 XCS1
Motorola Device
Figure Connections
controller supports both Motorola control signals. addition, these devices attach 3.3-V PowerPC data bus, they must drive over 3.3V. easy solution this 3.3-V buffer between high-speed memory path devices, which side allowing faster memory operation reduced capacitive loading.
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BWE0 XCS0
Device LVT245
XCS1
3.3V Device
Figure Buffered Connections
Collected Controls
previous sections have provided general overview memory controller; this section provides details. Table shows most signals that directly connected memory wired some particular state. controls needed burst SRAM share common byte-write enables; memory controller signals listed Table
Table Memory Controller Signal Handling
Signal TBST AACK ADSC Treatment Examined start cycle Examined type cycle Examined cycle destination (RAM, ROM, I/O) Examined byte lane enables burst transfer Asserted memory transfer Asserted per-beat each memory transfer Asserted each unsupported memory transfer Asserted writes individual byte lane(s) Asserted SRAM accesses Asserted SRAM read accesses Asserted burst SRAM accesses before cycle Asserted burst SRAM accesses during cycles Asserted Flash accesses Asserted Flash read accesses Asserted accesses Asserted read accesses Applies SRAM, SRAM SRAM SRAM SRAM
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other signals either wired necessary state unused described Table example, since PowerPC parked permanently, detecting ABB, unnecessary. memory controller interface then requires total signals, well within capacity modern FPGA, leaving lots additional functions.
Memory Controller Details
remainder Part System describes internal operations memory controller used Excimer reference board. code based upon synthesizable VHDL code, could easily adapted Verilog, several variants that exist Actel, Altera, Lattice, Xilinx Figure shows internal architecture memory controller module.
chipsel()
start()
CLAIM_L DOERR_L
ADSC
WE_L
TBST
bytedec()
AACK
cycler()
Figure Memory Controller Architecture
3.5.1 Start Detection Module
Upon receiving memory controller must examine signals determine type cycle that will performed. possible permutations, only those found Table interest:
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Table Encoding
Transaction Write-with-kill Read Read-with-intent-to-modify Memory Controller Action Single-beat burst write Burst write Single-beat burst read Burst read
remaining codes either address-only cycles (which needed), caused instructions needed single-processor environments (for example, eciwx, ecowx, dcbz, lwarx, stcwx instructions), reserved values. These possible because there need snoop processor maintain cache coherency.
While software should generate such cycles, reliable memory controller simply ignore them. memory controller, sole target transactions, must terminate unacceptable cycles with TEA; otherwise, processor will wait forever (ignored) cycle complete. When transfer begins, module must either assert signal cause appropriate actions conclude transfer cycle (which handled state machine general architecture shown Figure
AACK start() ttdec() WE_L CLAIM_L DOERR_L
Figure Start Detector Module
signals change during address tenure, whether burst single-beat, outputs remain valid until memory controller asserts AACK. module provides global CLAIM_L signal, used other modules detect whether cycle in-progress, DOERR_L signal, used terminate unclaimed cycles, write signal (WE_L) determine that cycle write cycle. These signals used exclusively other modules, remain valid until memory controller completes cycle asserting AACK. VHDL code this module
TTDEC.VHD TTDEC() monitors determines whether interest not. signal provided start, tt_we_L reflects read/write status. NOTE: TTDEC must optimized errors will occur when hierarchical -optimization performed (TT1 will optimized away, making -impossible connect TTDEC this ViewSynthesis). -Recommended procedure dissolve TTDEC into it's parent level
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-before optimization. ViewSynthesis doesn't seem care about -input pins that level. Copyright 1998, Motorola Inc. rights reserved. Author: Gary Milliorn Revision: Date: 6/10/98 Notes: -All logic active when appended with "_L". -Passed speedwave check 6/16/98. -library ieee; ieee.std_logic_1164.all; ieee.std_logic_arith.all; ieee.std_logic_unsigned.all; TTDEC -ENTITY TTDEC PORT( std_logic_vector( current transfer type. tt_take buffer std_logic; asserted when matches types. tt_we_L buffer std_logic; asserted when cycle write. monitor buffer std_logic ViewSynthesis useful. end; -PORT DEFINITION ENTITY -ARCHITECTURE BEHAVIOR TTDEC SIGNAL wflush, wkill, read, rwim BEGIN Detect only following types. "tt_take" will asserted cycles will claim. -wflush WHEN (tt(0) tt(1) tt(2) tt(3) tt(4) '0') ELSE '0'; wkill WHEN (tt(0) tt(1) tt(2) tt(3) tt(4) '0') ELSE '0'; read WHEN (tt(0) tt(1) tt(2) tt(3) tt(4) '0') ELSE '0'; rwim WHEN (tt(0) tt(1) tt(2) tt(3) tt(4) '0') ELSE '0'; tt_take (wflush wkill read rwim); tt_we_L (wflush wkill); Needed ViewSynthesis bug: optimizes away, then complains about their absence. monitor read; BEHAVIOR; START.VHD START() portion memory controller which decodes incoming transfers decides whether they should claimed controller terminated with error condition. Copyright 1998, Motorola Inc. rights reserved. Author: Gary Milliorn Revision: Date: 9/23/98 Notes: -All logic active when appended with "_L". -Passed speedwave check 6/16/98. -Moved ADSC* assertion state machine. -library ieee; ieee.std_logic_1164.all; std_logic;
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ieee.std_logic_arith.all; ieee.std_logic_unsigned.all; START -ENTITY START PORT( tt_take std_logic; asserted good selection. tt_we_L std_logic; asserted good write. ts_L std_logic; transfer start strobe. aack_L std_logic; asserted transfer complete. std_logic; clock. rst_L std_logic; system reset. claim_L buffer std_logic; asserted when cycle claimed. doerr_L buffer std_logic; asserted when cycle claimed. we_L buffer std_logic byte lane write selects. end; -PORT DEFINITION ENTITY -ARCHITECTURE BEHAVIOR START BEGIN Derive flop maintain selected status. register must globally clocked well Lattice 2xxx FPGA architecture, where clocks resets global expensive). monitor PROCESS( clk, rst_L BEGIN (rst_L '0') THEN we_L '1'; claim_L '1'; doerr_L '1'; ELSIF (clk'EVENT '1') THEN (ts_L tt_take '1') (claim_L aack_L '1')) THEN claim_L '0'; we_L tt_we_L; ELSE claim_L '1'; we_L '1'; (ts_L tt_take '0') (doerr_L aack_L '1')) THEN doerr_L '0'; ELSE doerr_L '1'; PROCESS; something want. claimed, AACK'd else AACK no-claim
something dont' want. errored, AACK'd else AACK claim
BEHAVIOR;
3.5.2 Byte Write Enable
next group signals generate byte lane write enables These signals generated using transfer size signals along with lower address signals determine which byte lanes should active.
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TBST we_L bytedec()
Figure Byte Write Enable Module
Note that module examines decoded write status (WE_L) CLAIM, byte lane enables asserted write cycles regardless activity CLAIM signal. This acceptable long corresponding chip-select signals disable attached memory devices, which true devices used. VHDL code module lengthy straightforward. values directly derived from data alignment tables processor user manuals, example Table Table MPC750 RISC Microprocessor Manual. Burst transfers enable byte lanes, while other transfers enable only byte lanes based upon address transfer size.
BYTEDEC.VHD BYTEDEC() portion which provides individual byte write enabled each byte lane, depending upon size address transfer. cycle read cycle, outputs asserted all. Copyright 1998, Motorola Inc. rights reserved. Author: Gary Milliorn Revision: Date: 6/10/98 Notes: -All logic active when appended with "_L". -Passed speedwave check 6/10/98. -library ieee; ieee.std_logic_1164.all; ieee.std_logic_arith.all; ieee.std_logic_unsigned.all; -ENTITY BYTEDEC PORT( std_logic_vector( stable address tsiz std_logic_vector( current transfer size. tbst_L std_logic; asserted transfer burst. we_L std_logic; asserted transfer write. bwe_L buffer std_logic_vector( byte lane write selects. end; -PORT DEFINITION ENTITY -ARCHITECTURE BEHAVIOR BYTEDEC SIGNAL be_L std_logic_vector( BEGIN Convert transfer size address into byte lane enables. Write masking occurs later. be_L(0) WHEN (tsiz (tsiz (tsiz (tsiz (tsiz "001" "010" "100" "000" "011" "000") "000") "000") "000") "000") -byte half-word word double-word three-byte byte lane enables (read write).
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(tbst_L '0') ELSE '1'; be_L(1) WHEN (tsiz (tsiz (tsiz (tsiz (tsiz (tsiz (tbst_L ELSE '1'; WHEN (tsiz (tsiz (tsiz (tsiz (tsiz (tsiz (tsiz (tbst_L ELSE '1'; WHEN (tsiz (tsiz (tsiz (tsiz (tsiz (tsiz (tsiz (tbst_L ELSE '1'; WHEN (tsiz (tsiz (tsiz (tsiz (tsiz (tsiz (tsiz (tbst_L ELSE '1'; WHEN (tsiz (tsiz (tsiz (tsiz (tsiz (tsiz (tsiz (tbst_L ELSE '1'; WHEN (tsiz (tsiz (tsiz (tsiz (tsiz (tsiz (tbst_L ELSE '1'; WHEN (tsiz (tsiz (tsiz (tsiz (tsiz (tbst_L ELSE '1'; "001" "010" "100" "000" "011" "011" '0') "001") "000") "000") "000") "000") "001") burst
byte half-word word double-word three-byte three-byte burst
be_L(2)
"001" "010" "100" "000" "011" "011" "011" '0')
"010") "010") "000") "000") "000") "001") "010")
byte half-word word double-word three-byte three-byte three-byte burst
be_L(3)
"001" "010" "100" "000" "011" "011" "011" '0')
"011") "010") "000") "000") "001") "010") "011")
byte half-word word double-word three-byte three-byte three-byte burst
be_L(4)
"001" "010" "100" "000" "011" "011" "011" '0')
"100") "100") "100") "000") "010") "011") "100")
byte half-word word double-word three-byte three-byte three-byte burst
be_L(5)
"001" "010" "100" "000" "011" "011" "011" '0')
"101") "100") "100") "000") "011") "100") "101")
byte half-word word double-word three-byte three-byte three-byte burst
be_L(6)
"001" "010" "100" "000" "011" "011" '0')
"110") "110") "100") "000") "100") "101")
byte half-word word double-word three-byte three-byte burst
be_L(7)
"001" "010" "100" "000" "011" '0')
"111") "110") "100") "000") "101")
byte half-word word double-word three-byte burst
mask byte lanes with write signal. bwe_L(0) (be_L(0) we_L); bwe_L(1) (be_L(1) we_L); bwe_L(2) (be_L(2) we_L);
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bwe_L(3) bwe_L(4) bwe_L(5) bwe_L(6) bwe_L(7) (be_L(3) (be_L(4) (be_L(5) (be_L(6) (be_L(7) we_L); we_L); we_L); we_L); we_L);
BEHAVIOR;
three-byte cycles arise from need handle misaligned transfers breaking them into separate cycles; refer MPC603e EC603e RISC Microprocessor Manual MPC750 RISC Microprocessor Manual details this process. These cycles occur unaligned transfers occur. Since many compilers generate such code, lines three-byte handling deleted simplify controller reduce gate count.
3.5.3 Chip Select
chip-select module, shown Figure generates four chip-select signals selects proper time delay accesses memory (this information used module).
chipsel() WE_L CLAIM_L
Figure Chip Select Module
Table shows chip-select actions based upon address.
Table Chip Select Encodings
Area High-speed SRAM array High-speed Slow-speed Flash boot Time MHz) Clock Count Timer Value
timer values Table have constant overhead three subtracted from expected timer values. This constant overhead start delay, assertion, clock needed detect zerocount timer. best performance, actual timer values offset (-3). examining chipsel(), SRAM chip select found fairly straightforward; other chip selects differ that 4-bit timer value generated delay assertion
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code this module
CHIPSEL.VHD CHIPSEL() portion which decodes addresses provides corresponding chip select outputs, along with clock timer value which determines rate memory accesses. Copyright 1998, Motorola Inc. rights reserved. Author: Gary Milliorn Revision: Date: 6/10/98 Notes: -All logic active when appended with "_L". -Passed speedwave check 6/16/98. -library ieee; ieee.std_logic_1164.all; ieee.std_logic_arith.all; ieee.std_logic_unsigned.all; CHIPSEL -ENTITY CHIPSEL PORT( std_logic_vector( stable address claim_L std_logic; asserted active cycles. we_L std_logic; asserted write cycles. scs_L, soe_L buffer std_logic; SRAM chip-selects enables. fcs_L, foe_L buffer std_logic; Flash chip-selects enables. xcs_L buffer std_logic_vector( chip selects. xoe_L buffer std_logic; output enable. ctime buffer std_logic_vector( downto 4-bit time value. end; -PORT DEFINITION ENTITY -ARCHITECTURE BEHAVIOR CHIPSEL BEGIN Assert chip select cycle claimed scs_L WHEN "00" claim_L ELSE xcs_L(0) WHEN "01" claim_L ELSE xcs_L(1) WHEN "10" claim_L ELSE fcs_L WHEN "11" claim_L ELSE corresponding address presented. cycle claimed we_L we_L we_L we_L
Assert corresponding output enables (OE_L) write cycle. soe_L WHEN "00" claim_L ELSE xoe_L WHEN "01" claim_L "10" claim_L ELSE foe_L WHEN "11" claim_L ELSE
Provide corresponding timer value. Note that SRAM timer controlled, value used. these values should changed frequency changed. clock rate increased, system fail. lowered, clock cycles will wasted.
Note: there three clock overhead setup termination timed cycles (one entry, during AACK/TA*, exiting when timer zero). Therefore, timing constants offset (-3). SET_TIMER PROCESS( fcs_L, xcs_L(0) BEGIN (fcs_L THEN ctime "0011"; Flash:
15ns clocks MHz) clocks.
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ELSIF (xcs_L(0) THEN ctime "1001"; ELSE ctime "0001"; PROCESS SET_TIMER; Slow I/O: 15ns clocks MHz) clocks. Fast I/O: 15ns clocks MHz) clocks.
BEHAVIOR;
chipsel() module asynchronous because relies synchronous signal, claim_L, relies stability address write select (we_L) signals. These latter signals guaranteed stable until asserted because cycler() module also delays assertion AACK until last chip-select module easily adapted different device speeds, different maps (within PowerPC architecture limitations). also provide access internal register increase number chip selects, within limitations FPGA chosen.
3.5.4 Cycler State Machine
cycler() state machine module controls remainder transaction claimed memory controller. optimal performance, four selected. follows: SRAM single beat transfer SRAM burst transfer Programmed-length transfer (I/O Flash) Error transactions
optimize speed SRAM accesses, which typically majority code data accesses; latter handled more programmed method. Fortunately, streamlined nature burst transfers keeps cycler() module from becoming complicated. Cycler() non-error transaction asserting AACK (one four times, based upon type cycle). When AACK generated, cycle been completed begin next clock cycle. pipelining nature SRAM, actually takes beats read cycle, those clock cycles already been provided before cycler() leave IDLE state synchronous start() detector. Figure shows end-cycle module.
AACK cycler SCS_L TBST ADSC
CLAIM_L DOERR_L
Figure End-Cycle Module
VHDL code cycler() generated state-machine program, code uncommented somewhat follow; refer instead Figure details.
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CYCLER.DIA Cycler Milliorn 98SEP25
!RST_L
DESEL
IDLE
!CLAIM_L !SCS_L !TBST_I
!DOERR_L
!CLAIM_L SCS_L TBST_ COUNT TIMER CTIME;
!CLAIM_L !SCS_L TBST_
BURST
ERROR BEAT1
SINGLE TIMER "0000" COUNT TIMER TIMER WE_L
!WE_L
BEAT2
TIMER "0000" BEAT3
Moore Machine State Outputs AACK_L (BEAT4 ERROR) ADSC_L (IDLE !SCS_L !CLAIM_L) DESEL) BAA_L (BURST BEAT1 BEAT2) (BEAT4 !WE_L !TBST_L) TA_L (BEAT1 BEAT2 BEAT3 BEAT4) (!TBST_L !WE_L) (BURST !WE_L)
BEAT4
TEA_L ERROR Vector Declarations CTIME[] TIMER[]
Figure Cycler() State Flow
state machine switches from IDLE state BEAT1 state detection claimed burst cycle (TBST_L CLAIM_L asserted, which only allowed SRAM). This begins four-beat burst transfer with four clock cycles (the state machine clocks frequency, proceeds from BEAT1 BEAT4 automatically). states BEAT1 through BEAT3, signal asserted cause burst SRAM devices increment address. This produces SRAM access rate 2-1-1-1 (excluding TS). Alternately, CLAIM_L asserted TBST, cycle SRAM (SCS_L asserted), then this single-beat access SRAM. While this could have been handled timer (say presetting 0001), overhead checking timer costs additional cycles. detecting SRAM single-beats separately, fast access SRAM guaranteed (two clocks). Otherwise, cycle either error single-beat access Flash I/O. latter cases, only clock needed, lengthy delay needed give peripheral device time complete access. such devices, within cycler() state-machine internal timer which continually reloaded while IDLE state; other state, counts downward. When timer reaches zero
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state COUNT, state machine switches BEAT4 state terminate cycle with AACK. cycles which cannot handled memory controller, DOERR_L will asserted. This caused either address-only cycles specialized data transfer instructions (lwarx, etc.); such cycles, state machine will assert AACK. behavior PowerPC processors does specify what happens when asserted during address-only cycles; however, since this minimal system environment disallows such cycles, resulting behavior allowable (either cycles silently ignored processing resumes, processor takes exception). these cases, AACK asserted until last only) asserted, releasing address tenure well data tenure. re-assertion delay inherent before asserted guarantees one-clock cycle recovery time data bus. VHDL code this module
VHDL code created Visual Software Solution's StateCAD Version 16:16:39 1998 -This VHDL code (for with Workview Office) generated using: one-hot state assignment with boolean code format. Minimization enabled, implied else enabled, outputs manually optimized.
-LIBRARY LAT_VHD; -USE LAT_VHD.VHD_PKG.ALL; LIBRARY ieee; ieee.std_logic_1164.all; LIBRARY synth; synth.vhdlsynth.all; ENTITY SHELL_CYCLER PORT WE_L: std_logic; AACK_L,ADSC_L,BAA_L,TA_L,TEA_L std_logic); SIGNAL TIMER0,TIMER1,TIMER2,TIMER3: std_logic; END; ARCHITECTURE BEHAVIOR SHELL_CYCLER State variables machine sreg SIGNAL BEAT1, next_BEAT1, BEAT2, next_BEAT2, BEAT3, next_BEAT3, BEAT4, next_BEAT4, BURST, next_BURST, CLOCK, next_CLOCK, COUNT, next_COUNT, DESEL, next_DESEL, ERROR, next_ERROR, IDLE, next_IDLE, SINGLE, next_SINGLE std_logic; SIGNAL std_logic; SIGNAL TIMER std_logic_vector DOWNTO ATTRIBUTE PERMEABILITY BEHAVIOR: ARCHITECTURE TRUE; BEGIN PROCESS (CLK, RST_L, next_BEAT1, next_BEAT2, next_BEAT3, next_BEAT4, next_BURST, next_CLOCK, next_COUNT, next_DESEL, next_ERROR, next_IDLE, next_SINGLE, next_TIMER3, next_TIMER2, next_TIMER1, next_TIMER0) BEGIN RST_L='0' THEN BEAT1 '0'; BEAT2 '0'; BEAT3 '0'; BEAT4 '0'; BURST '0'; CLOCK '0'; COUNT '0'; DESEL '0'; ERROR '0'; IDLE '1'; SINGLE '0'; TIMER3 '0'; TIMER2 '0'; TIMER1 '0'; TIMER0 '0'; ELSIF CLK='1' CLK'event THEN BEAT1 next_BEAT1;
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BEAT2 next_BEAT2; BEAT3 next_BEAT3; BEAT4 next_BEAT4; BURST next_BURST; CLOCK next_CLOCK; COUNT next_COUNT; DESEL next_DESEL; ERROR next_ERROR; IDLE next_IDLE; SINGLE next_SINGLE; TIMER3 next_TIMER3; TIMER2 next_TIMER2; TIMER1 next_TIMER1; TIMER0 next_TIMER0; PROCESS; PROCESS TIMER2,TIMER3,WE_L,TIMER) BEGIN (BURST='1'))) THEN next_BEAT1<='1'; ELSE next_BEAT1<='0'; WE_L='1' (BEAT1='1'))) THEN next_BEAT2<='1'; ELSE next_BEAT2<='0'; (BEAT2='1'))) THEN next_BEAT3<='1'; ELSE next_BEAT3<='0'; WE_L='0' (BEAT1='1')) (BEAT3='1')) TIMER0='0' TIMER1='0' TIMER2='0' TIMER3='0' (CLOCK='1')) (SINGLE='1') THEN next_BEAT4<='1'; ELSE next_BEAT4<='0'; DOERR_L='1' TBST_L='0' CLAIM_L='0' SCS_L='0' (IDLE='1'))) THEN next_BURST<='1'; ELSE next_BURST<='0'; TIMER0='1' (CLOCK='1')) TIMER1='1' (CLOCK='1')) TIMER2='1' (CLOCK='1')) TIMER3='1' (CLOCK='1')) (COUNT='1'))) THEN next_CLOCK<='1'; ELSE next_CLOCK<='0'; DOERR_L='1' SCS_L='1' CLAIM_L='0' TBST_L='1' (IDLE='1'))) THEN next_COUNT<='1'; ELSE next_COUNT<='0'; (BEAT4='1'))) THEN next_DESEL<='1'; ELSE next_DESEL<='0'; DOERR_L='0' (IDLE='1'))) THEN next_ERROR<='1'; ELSE next_ERROR<='0'; (DESEL='1')) (ERROR='1')) DOERR_L='1' SCS_L='1' TBST_L='0' (IDLE='1')) DOERR_L='1' CLAIM_L='1' (IDLE='1')) THEN next_IDLE<='1'; ELSE next_IDLE<='0'; DOERR_L='1' CLAIM_L='0' SCS_L='0' TBST_L='1' (IDLE='1'))) THEN next_SINGLE<='1'; ELSE next_SINGLE<='0'; TIMER<= BEAT1& BEAT1& BEAT1& BEAT1)) WE_L& WE_L& WE_L& WE_L)) ("0000") BEAT1& BEAT1& BEAT1& BEAT1)) WE_L& WE_L& WE_L& WE_L)) ("0000") BEAT2& BEAT2& BEAT2& BEAT2)) ("1111") ("0000") BEAT3& BEAT3& BEAT3& BEAT3)) ("1111") ("0000") BEAT4& BEAT4& BEAT4& BEAT4)) ("1111") ("0000") BURST& BURST& BURST& BURST)) ("1111") ("0000")
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CLOCK& CLOCK& CLOCK& CLOCK)) TIMER3& TIMER3& TIMER3& TIMER3)) TIMER2& TIMER2& TIMER2& TIMER2)) TIMER1& TIMER1& TIMER1& TIMER1)) TIMER0& TIMER0& TIMER0& TIMER0)) (TIMER3 &TIMER2 &TIMER1 &TIMER0)) ("0001") COUNT& COUNT& COUNT& COUNT)) ("1111") (TIMER3 &TIMER2 &TIMER1 &TIMER0)) ("0001") CLOCK& CLOCK& CLOCK& CLOCK)) TIMER0& TIMER0& TIMER0& TIMER0)AND TIMER1& TIMER1& TIMER1& TIMER1)AND TIMER2& TIMER2& TIMER2& TIMER2)AND TIMER3& TIMER3& TIMER3& TIMER3)) ("0000") IDLE& IDLE& IDLE& IDLE) DOERR_L& DOERR_L& DOERR_L& DOERR_L)AND SCS_L& SCS_L& SCS_L& SCS_L)AND CLAIM_L& CLAIM_L& CLAIM_L& CLAIM_L)AND TBST_L TBST_L& TBST_L& TBST_L)) (CTIME3 &CTIME2 &CTIME1 &CTIME0)) DESEL& DESEL& DESEL& DESEL)) ("1111") ("0000") ERROR& ERROR& ERROR& ERROR)) ("1111") ("0000") IDLE& IDLE& IDLE& IDLE)) DOERR_L& DOERR_L& DOERR_L& DOERR_L)) ("0000") IDLE& IDLE& IDLE& IDLE DOERR_L& DOERR_L& DOERR_L& DOERR_L)AND CLAIM_L& CLAIM_L& CLAIM_L& CLAIM_L)AND SCS_L& SCS_L& SCS_L& SCS_L)AND TBST_L& TBST_L& TBST_L& TBST_L)) ("0000") IDLE& IDLE& IDLE& IDLE)) DOERR_L& DOERR_L& DOERR_L& DOERR_L)AND TBST_L& TBST_L& TBST_L& TBST_L)AND CLAIM_L& CLAIM_L& CLAIM_L& CLAIM_L)AND SCS_L& SCS_L& SCS_L& SCS_L)) ("0000") IDLE& IDLE& IDLE& IDLE)) DOERR_L& DOERR_L& DOERR_L& DOERR_L)AND CLAIM_L& CLAIM_L& CLAIM_L& CLAIM_L) DOERR_L& DOERR_L& DOERR_L& DOERR_L)AND SCS_L& SCS_L& SCS_L& SCS_L)AND TBST_L& TBST_L& TBST_L& TBST_L)) ("0000") SINGLE& SINGLE& SINGLE& SINGLE)) ("1111") ("0000") next_TIMER3 next_TIMER2 next_TIMER1 next_TIMER0 PROCESS; TIMER(3); TIMER(2); TIMER(1); TIMER(0);
PROCESS (BEAT4,ERROR) BEGIN (BEAT4='0')AND (ERROR='0'))) THEN AACK_L<='1'; ELSE AACK_L<='0'; PROCESS; PROCESS (CLAIM_L,DESEL,IDLE,SCS_L) BEGIN CLAIM_L='1' (DESEL='0')) SCS_L='1' (DESEL='0')) (IDLE='0')AND (DESEL='0'))) THEN ADSC_L<='1'; ELSE ADSC_L<='0'; PROCESS; PROCESS BEGIN (BURST='0')AND (BEAT1='0')AND (BEAT2='0')AND (BEAT4='0')) (BURST='0')AND (BEAT1='0')AND (BEAT2='0')AND WE_L='1' (BURST='0') (BEAT1='0')AND (BEAT2='0')AND TBST_L='1' THEN BAA_L<='1'; ELSE BAA_L<='0'; PROCESS; PROCESS BEGIN (BEAT1='0')AND (BEAT2='0')AND (BEAT3='0')AND (BEAT4='0')AND TBST_L='1' (BURST='0')) (BEAT1='0')AND (BEAT2='0')AND (BEAT3='0' )AND (BEAT4='0')AND WE_L='1' THEN TA_L<='1'; ELSE TA_L<='0'; PROCESS; PROCESS (ERROR) BEGIN (ERROR='0'))) THEN TEA_L<='1'; ELSE TEA_L<='0'; PROCESS; BEHAVIOR; -LIBRARY LAT_VHD; -USE LAT_VHD.VHD_PKG.ALL; LIBRARY ieee; ieee.std_logic_1164.all; LIBRARY synth;
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synth.vhdlsynth.all; ENTITY CYCLER PORT (CTIME std_logic_vector DOWNTO std_logic; AACK_L,ADSC_L,BAA_L,TA_L,TEA_L std_logic); END; ARCHITECTURE BEHAVIOR CYCLER COMPONENT SHELL_CYCLER PORT WE_L: std_logic; AACK_L,ADSC_L,BAA_L,TA_L,TEA_L std_logic); COMPONENT; BEGIN SHELL1_CYCLER SHELL_CYCLER PORT BEHAVIOR; CONFIGURATION SHELL2_CYCLER CYCLER BEHAVIOR FOR; SHELL2_CYCLER;
preceeding code produced state machine compiler, there comments very readable. code uses encoding (one register encodes each state), each clock cycle registers reloaded with encoded next state calculations typical Moore machine fashion. remainder code computes next state, provides encoded output. code calculating timing value (TIME) looks complicated because four bits calculated statement.
3.5.5 Memory Controller Module
module memory controller itself, which simply interconnects previous modules, shown previously Figure VHDL code this module
MC.VHD FPGA which implements simple fast PowerPC 60X/7XX family processors. controller described detail Application Note AN17XX, minimal PowerPC System Design". Most just top-level interconnect lower-level modules: -start checks asserts CLAIM DOERR depending whether -transfer will handled not. -ttdec uses bits separate cycles into handled non-handled types. -chipsel provides chip select output enables devices depending -upon current address. Provides timing values cycler -use. Speculatively asserts ADSC*. -bytedec provides byte-write enables SRAM Flash. -cycler handles timing assertion AACK* TA*, AACK* TEA*, -depending CLAIM DOERR status. Handles burst, single-beat -with various timings. -int simple interrupt merge. Copyright 1998, Motorola Inc. rights reserved. Author: Gary Milliorn Revision: Date: 6/21/98 Notes: -All logic active when appended with "_L" -library ieee; ieee.std_logic_1164.all; ieee.std_logic_arith.all;
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ieee.std_logic_unsigned.all; -ENTITY PORT( clk, rst_L std_logic; general controls. a_high a_low ts_L tsiz tbst_L altrst_L cophrst_L bwe_L scs_L, soe_L fcs_L, foe_L xcs_L xoe_L ta_L, tea_L aack_L adsc_L baa_L int_L hreset_L mreset fcsled, scsled xcsled probe1 monitor1 buffer buffer buffer buffer buffer buffer buffer buffer buffer buffer std_logic_vector( std_logic_vector( std_logic; std_logic_vector( std_logic_vector( std_logic; std_logic_vector( std_logic; std_logic; upper address lower address transfer start. transfer type. transfer size. asserted transfer burst. interrupt inputs. alternate reset input. port HRESET input. byte lane write selects. SRAM chip-selects enable. Flash chip-selects enable. chip selects. output enable. -normal error acks. address acks. SRAM address latch. SRAM burst address advance. interrupt output. HRESET* output. Misc active-high reset output. output drivers.
std_logic_vector( std_logic; std_logic; std_logic_vector( std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic_vector(
data input. internal monitors. ViewSynthesis bug.
buffer std_logic; buffer std_logic
end; -PORT DEFINITION ENTITY -ARCHITECTURE BEHAVIOR COMPONENT BYTEDEC PORT( tsiz tbst_L claim_L we_L bwe_L COMPONENT; COMPONENT CHIPSEL PORT( claim_L we_L scs_L, soe_L fcs_L, foe_L xcs_L xoe_L ctime COMPONENT; COMPONENT PORT( int_L COMPONENT; buffer std_logic_vector( stable address std_logic_vector( current transfer size. std_logic; asserted transfer burst. std_logic; asserted transfer claimed. std_logic; asserted transfer write. std_logic_vector( byte lane write selects.
buffer buffer buffer buffer buffer
std_logic_vector( std_logic; std_logic; std_logic; std_logic; std_logic_vector( std_logic; std_logic_vector( downto
stable address asserted active cycles. asserted write cycles. SRAM chip-selects enable. Flash chip-selects enable. chip selects. output enable. 4-bit time value.
std_logic_vector( buffer std_logic
interupt inputs (var. polarity) interrupt output.
COMPONENT CYCLER PORT( CTIME std_logic_vector DOWNTO CLK,CLAIM_L,DOERR_L, RST_L,SCS_L,TBST_L std_logic; AACK_L,ADSC_L,BAA_L, TA_L,TEA_L std_logic
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COMPONENT; COMPONENT START PORT( tt_take tt_we_L ts_L aack_L rst_L claim_L doerr_L we_L COMPONENT; COMPONENT TTDEC PORT( tt_take tt_we_L monitor COMPONENT; buffer buffer buffer std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic -asserted good selection. asserted good write. transfer start strobe. asserted transfer complete. clock. system reset. asserted when cycle claimed. asserted when cycle claimed. byte lane write selects.
buffer buffer buffer
std_logic_vector( std_logic; std_logic; std_logic
current transfer type. asserted when matches types. asserted when cycle write. unneeded, ViewSynthesis bug.
SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL
tt_take tt_we_L we_L claim_L doerr_L ctime aack_internal_L
std_logic; std_logic; std_logic; std_logic; std_logic; std_logic_vector( downto std_logic;
asserted matches. asserted match writes. asserted write cycles. asserted cycles process. asserted cycles TEA* selected cycle time. internal copy.
-BEGIN TTDEC_1 TTDEC PORT tt_take tt_take, tt_we_L tt_we_L, monitor monitor1 START PORT tt_take tt_take, tt_we_L tt_we_L, ts_L ts_L, aack_L aack_internal_L, clk, rst_L rst_L, claim_L claim_L, doerr_L doerr_L, we_L we_L CHIPSEL PORT a_high, claim_L claim_L, we_L we_L, scs_L scs_L, soe_L soe_L, fcs_L fcs_L, foe_L foe_L, xcs_L xcs_L, xoe_L xoe_L, ctime ctime
START_1
CHIPSEL_1
BYTEDEC_1 BYTEDEC PORT a_low, tsiz tsiz, tbst_L tbst_L, claim_L claim_L, we_L we_L, bwe_L bwe_L CYCLER_1 CYCLER PORT CTIME ctime, clk, CLAIM_L claim_L, DOERR_L doerr_L, RST_L rst_L, SCS_L scs_L, TBST_L tbst_L, AACK_L aack_internal_L, ADSC_L adsc_L, BAA_L baa_L, TA_L ta_L, TEA_L tea_L Copy internal aack external aack, since VHDL fussy about connecting OUT's BUFFER's. aack_L WHEN (aack_internal_L '0') ELSE '1'; databus port otherwise errors probe1 WHEN ELSE currently used; logic maintain existance, will generated unused ports. "11111111") '1';
Sideband modules that part memory controller needed Excimer project include interrupt controller, reset drivers monitors. Extremely simple interrupt controller databus wired ready accept more complicated version, desired.
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INT_1 PORT irq, int_L int_L
Assert HRESET when general reset asserted when resets active high RESET only asserted general reset, COP. hreset_L mreset WHEN ELSE WHEN ELSE (altrst_L cophrst_L '0') '1'; (hreset_L '0') '0';
monitor outputs when action occurs. While could chip selects, LEDs need some current best keep them isolated. fcsled WHEN ELSE scsled WHEN ELSE xcsled WHEN ELSE (fcs_L '0') '0'; (scs_L '0') '0'; (xcs_L(0) xcs_L(1) '0') '0';
BEHAVIOR;
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Waveforms
This section shows several timing waveforms. Figure shows single-beat access SRAM, which similar Flash, except that timer used keep performance high. this waveform, data available second clock after signal asserted.
TSIZ0 TSIZ1
TSIZ2 TBST_L TS_L AACK_L TA_L TEA_L ADSC_L BAA_L SCS_L SOE_L BWE_L0 BWE_L1 BWE_L2 BWE_L3 BWE_L4 BWE_L5 BWE_L6 BWE_L7 RST_L
T(CLK)
Time (Seconds)
Figure Pipelined Burst Read/Write
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Figure shows pipelined burst SRAMs that need ADSC asserted start, then asserted burst four beats data. After beat, asserted increment address next location. each transfer, ADSC strobed deselect SRAM.
A_HIGH0 A_HIGH1 A_LOW29 A_LOW30 A_LOW31 TSIZ0
TSIZ1 TSIZ2 TBST_L TS_L AACK_L TA_L TEA_L ADSC_L BAA_L SCS_L SOE_L BWE_L0 BWE_L1 BWE_L2 BWE_L3 BWE_L4 BWE_L5 BWE_L6 BWE_L7 RST_L HRESET_L !RESET COPHRST_L MRESET
T(CLK)
Time (Seconds)
Figure Pipelined Burst Read/Write
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Figure shows that Flash access controlled timed values, this case value provided chipsel() module) which produces 6-clock access time.
A_HIGH0 A_HIGH1 A_LOW29 A_LOW30 A_LOW31 TSIZ0
TSIZ1 TSIZ2 TBST_L TS_L AACK_L TA_L TEA_L SOE_L FCS_L FOE_L BWE_L0 BWE_L1 BWE_L2 BWE_L3 BWE_L4 BWE_L5 BWE_L6 BWE_L7 RST_L T(CLK)
Time (Seconds)
Figure Flash Read/Write
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Figure shows back-to-back accesses, space, second space.
A_HIGH0 A_HIGH1 A_LOW29 A_LOW30 A_LOW31 TSIZ0 TSIZ1
TSIZ2 TBST_L TS_L AACK_L TA_L TEA_L XCS_L0 XCS_L1 XOE_L BWE_L0 BWE_L1 BWE_L2 BWE_L3 BWE_L4 BWE_L5 BWE_L6 BWE_L7 RST_L
T(CLK)
Time (Seconds)
Figure Read/Write
Software
When writing software using this simple memory controller, sure consider effects restrictions have placed environment. example, because Flash areas support burst transfers, they cannot made cacheable. either instruction data cache enabled PowerPC processor, burst transfers will always occur unless memory management unit (via BATs PTEs) used mark addresses non-cacheable.
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Part Clock
Unlike some systems, clock circuitry minimal system quite simple. processor, memory controller SRAM memories need separate clock (anywhere from MHz1) have point-to-point skew allowance. simplest this connect crystal oscillator device four loads shown This generally achievable with most clock oscillators.
3.3V Oscillator
equal-length traces each device
SRAM
SRAM
Memory Controller FPGA
PowerPC
Figure Simplest Clock Connection
clock generator must have very output impedance order drive four loads from output, unacceptable unless clock traces kept very short order so). this possible, alternative employ inexpensive low-skew clock generator such Motorola MPC904 shown Figure Using crystal oscillator with this device, each component have dedicated clock signal. This make board routing much easier, other devices Motorola MPC9xx family provide other clocks that needed along with primary system needs, increasing integration.
MPC904
equal-length traces each device
SRAM SRAM
SRAM
Memory Controller FPGA
PowerPC
Figure MPC904 Clock Connection
Note: MPC604-class devices fully static have minimum clock frequencies. MPC603- MPC750-class devices fully static. Refer respective hardware reference datasheets details.
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Part Reset
order properly condition PowerPC processor, HRESET signal must asserted whenever system initially powers whenever processor power supply supplies) fall below nominal voltage described hardware JTAG TRST signal must asserted reset well, initialize scan chain known state. addition, initial power-up sequence requires that HRESET signal asserted minimum clocks order properly initialize clock initialize hardware signals. simplest achieve these goals many inexpensive devices available drive reset lines proper time. Called supervisory these devices typically very inexpensive (less than US$0.50), have small footprints (SOT23 SO8), widely available from Texas Instruments, Maxim Semiconductor, others. Figure shows example using these types circuits.
+3.3V Supervisory Circuit Dallas DS1834 3.08V TRST Open Drain Digital Reset Input (optional)
+3.3V
PowerPC
HRESET TRST
Figure Reset Using Supervisory Controller
reliability power supply assured, power supply provides failure output, then reset controller reduced simple network, shown Figure
+3.3V Power Supply with open-drain Power Failure Output
PowerPC
POWERFAIL
HRESET
Figure Simple Reset Controller
Because drain HRESET signal negligible, simple equation calculate necessary values. above values shown give reset, which speeds faster than MHz.
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Part Power
order increase speeds without excessive heat loss, newest, fastest PowerPC processors have cores which operate voltages. remain compatible with external devices, cells have remained 3.3V. This increases complexity system somewhat requiring multiple voltages levels. Furthermore, transistor counts rise processors, static transient current demands power supplies rise well. Consequently, well-designed, quiet responsive power supply critical step well-designed PowerPC-based system. There many ways derive power, ranging from batteries radioisotope-thermocoupled generators. most popular methods linear supplies switching supplies, which considered further detail sections 6.2.
Linear Regulators
Linear regulators operate dissipating unwanted energy form heat. With proper thermal management, linear regulators very easy design, inexpensive, provide quiet, stable outputs. disadvantages heat inability generate higher voltages. Figure shows example linear 2.5-V power supply, similar that used Excimer board.
+5.0V
Linear Tech LT1584CT
+2.5V
0.1µF
0.1µF
Figure Excimer Linear Power Supply
Switchmode Regulators
alternate method providing other voltages switching power supply. These devices convert high-voltage, low-current energy into low-voltage, high-current energy storing magnetically inductor. Switching power supplies require more complicated logic careful design, rewards that high that thermal dissipation little issue. Because switchers work basically periodically dumping energy into low-impedance load, clocking noise transient effects make noisy supply unless components carefully selected. Figure shows example switching power supply.
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2.5µH +5.0V 1200µF MOSFET 1.3µH Raytheon/ Fairchild RC5050 Voltage Encoding Inputs +2.5V 1500µF
NOTE: details have been shown.
Figure Simple Switching Power Supply
This switcher 5-bit digital input which allows output voltage 0.1/0.05V increments ranges between 1.2V 3.6V. This allows single power supply easily programmed meet current future PowerPC processor requirements. addition, digital settings match those used PowerPC processor/cache module (interposer), which allows processor automatically select desired voltage.
Power Supply Sequencing
Once consequence multiple power supplies that when power initially applied, voltage rails will ramp different rates depending upon nature power supply, type load each, manner which different voltages derived. This present problem because power supplies PowerPC processor have following restrictions: must exceed OVDD more than 0.3V time including(requirement during power-on reset. OVDD must exceed VDD/AVDD more than 1.2V time including(requirement during power-on reset. VDD/AVDD must exceed OVDD more than 0.4V time including(requirement during power-on reset.
most PowerPC processors, OVDD (+3.3V I/O) load typically less than that (+2.5V core) power, cells three-stated during reset, 3.3-V power supply ramp faster than core voltage. Alternately, with more devices operating 3.3V, including bus, that power rail loaded (from system perspective) that power will stabilize more quickly. Figure shows example possible power sequencing waveforms.
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3.3V 2.5V HAZARD Minimal Load 3.3V Ramp (requirement
3.3V 2.5V HAZARD Maximum Load 3.3V Ramp (requirement
Figure Power Supply Sequencing
virtually impossible insure that voltages ramp their steady state identical rate identical time. either requirement requirement will violated depending only load 3.3-V power supply. Because such tracking achieve, PowerPC processors subjected differential voltage between OVDD power signals power supplies cannot track within limits within this period, other means must employed correct problem; otherwise, long term reliability processor affected failure internal protection circuitry. means keeping supplies synchronized so-called diode between power rails. example shown
Main Power MUR420 MUR420 Core Power
3.3V (OVDD)
2.5V (VDD)
Figure Bootstrap Diodes
bootstrap diodes selected such that nominal will sourced from OVDD power supply until power supply becomes active. above example, pair MUR420 Schottky barrier diodes connected series; each forward voltage (VF) 0.6V high currents, provides 1.2V drop, maintaining 2.5V power line 2.1V. Once core power supply stable 2.5V, then bootstrap diode(s) will reverse biased only nanoamperes leakage current will NOTE: essential that forward voltage effective current levels needed processor; amps depending PowerPC device. Many diodes have only nominal which falls nothing high current; such devices acceptable.
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Bypassing
well-designed power supply will quickly undermined poor bypassing system used. Attention bypassing essential eliminate poor ground-return paths through help quell transient noise voltage drooping switching consideration. High-frequency bypassing provided numerous ceramic capacitors located near each power pin. Only surface mount devices used, preferably smallest package possible (0805 with power connections side). Each capacitor should have direct power ground plane, with short connection power pin. PowerPC devices packages, solder pads connecting power pins (balls) should connected directly power ground plane with via. Since there pins, bypass capacitors should surround device bottom layer board. placing components bottom board allowed, next most preferable placement surround part close possible escape pattern. addition, good design will include several storage capacitors distributed around connected OVDD power planes. These capacitors provide local energy storage quick recharging smaller bypass capacitors, bulk capacitors should have equivalent series resistance (ESR) rating ensure quick response time necessary. Each bulk capacitor should least there should device every high-frequency capacitors (more they cannot placed relatively close).
Part Interrupts
PowerPC processor standard interrupt signal (INT) that connected external interrupt source needed. This keeping with RISC philosophy which software manages (optional) highly complex details hardware aims fast. long interrupting device levelsensitive, wired directly input (perhaps with inverter, necessary). extra interrupts needed, simplest manner merge level-sensitive interrupts with logic gate shown Figure
PowerPC INT0
Level Sensitive Interrupts
INT1 INT2
Figure Simple Interrupt Merging
Software must poll potential interrupting devices determine which more) caused interrupt clear This approach does allow priority among interrupts, interrupt masked unless interrupting device provides means quickly identify different interrupts assign them each interrupt vector reusing special-purpose interrupts MCP, shown Figure
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Level Sensitive Interrupts
INT0 INT1 INT2
PowerPC
Edge Sensitive Interrupts
Figure Interrupt Reuse
This approach does have several limitations interrupt; particular, HID0[EMCP] MSR[ME] enable bits must properly set, interrupt remains edge-sensitive unless additional external hardware used.
systems needing more traditional interrupt controller, many FPGA vendors offer cores which implement PC-style programmable interrupt controllers (PIC). There resources most FPGAs include with memory controller adding additional controls, 8-bit data bus, output, interrupt inputs. Such interrupt controller include other advanced features such edge-sensitive level-sensitive conversion, interrupt prioritizing masking. Excimer uses very simple interrupt merging system, though provisions place programmable interrupt masking. VHDL code Excimer interrupt controller
INT.VHD INT() small interrupt controller Excimer project which fits some available gates Memory Controller (MC). Copyright 1998, Motorola Inc. rights reserved. Author: Gary Milliorn Revision: Date: 6/30/98 Notes: -All logic active when appended with "_L". -Passed speedwave check 6/30/98. -library ieee; ieee.std_logic_1164.all; ieee.std_logic_arith.all; ieee.std_logic_unsigned.all; -ENTITY PORT( std_logic_vector( interupt inputs (variable polarity) int_L buffer std_logic interrupt output. end; -PORT DEFINITION ENTITY -ARCHITECTURE BEHAVIOR BEGIN int_L WHEN (irq(0) '1') (irq(1) '1') (irq(2) '0') (irq(3) '0')) ELSE '1'; active high interrupts active interrupts.
BEHAVIOR;
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Part
common on-chip processor (COP) function PowerPC processors allows remote computer system (typically with dedicated hardware debugging software) access control internal operations processor. While adding connection PowerPC system adds little cost, does many watchpoints, register memory other standard debugger features possible through this interface. interface standard header connection target system, based 0.025" squarepost 0.100" centered header assembly (often called header). connector typically removed connector key, shown Figure
RUN/STOP
CKSTPO
HRESET
SRESET
VIEW
Pins no-connects. physically present
Ground
PRESENT
Figure Connector Diagram
NOTE: There standardized number these headers; consequently, many different numbers have been observed variety schematics. Some numbered top-to-bottom then left-to-right, while others left-to-right then top-to-bottom, while still others number pins clockwise from with IC). Regardless local standardization, when adding port system, insure that signal placement follows that Figure when viewed from above connector. interface connects primarily through JTAG port processor, with some additional status monitoring signals. Table shows
Table Definitions
Pins Signal QACK TRST Connection QACK TRST Applicable Processor 603e, 603ev, 740, pulldown ground. Must merged with on-board TRST, any. Leave no-connect other processors. pullup VDD. section 8.2. Special
RUN/STOP VDD_SENSE
604, 604e
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VDD_SENSE
QACK
TRST
Table Definitions (Continued)
Pins Signal PRESENT Connection Optional Applicable Processor pullup VDD. used separate JTAG scan chains; section 8.2. Special
SRESET HRESET CKSTPO Ground
SRESET
Merge with on-board SRESET, any.
HRESET
Merge with on-board HRESET. location; should removed. pullup VDD.
CKSTPO Digital Ground
603e, 603ev, 740,
Merging Reset Signals
port requires ability independently assert HRESET TRST order fully control processor. target system independent reset sources, such voltage monitors, watchdog timers, power supply failures, push-button switches, then reset signals must merged into these signals with logic. possible just wire reset signals together, damage system target system occur. arrangement shown Figure allows independently assert HRESET TRST, while insuring that target drive HRESET well. pull-down resistor TRST insures that JTAG scan chain initialized during power-on attached; responsible driving TRST when needed.
PowerPC
From Target Board Reset Sources
HRESET
HRESET TRST
Header
Figure Reset Merging
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Multiple Scan Chains
JTAG scan chains typically consist numerous devices perform in-circuit testing printed circuit boards. Since some existing controller software able control processor other device present scan chain, often necessary provide isolation PowerPC JTAG port. Multiple scan chains common complex boards, this nothing new; however, small systems more desirable provide isolation capability that only created when debugging desired, while mass production. This isolation shown Figure done with logic, manually with removable jumper zero-ohm resistor even easily trace).
Method Method Method
resistor
Jumper Block
LVT08 Logic
PRESENT Port TRST MPC60x Other JTAG other devices Isolation Method
Figure Isolation
required IEEE 1189.1 (JTAG) standard, even though will active when commands issued, chain rest system will high, causing only IDLE commands issued other JTAG devices. NOTE: emulators assert present signal. logic-controlled method, used separate scan chain, insure that chosen emulator will provide PRESENT signal.
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Part Physical Layout
Figure shows example minimal system called Excimer; size shown approximation actual size.
Serial Port
RS232
FPGA In-Circuit Program
Serial Port
RPak RPak
RS232
RS232
RS232
DIN5 POWER
LT1584
Expansion Connector
ispLSI2064V
PowerPC
SOCKET CLEARANCE
PC16552
21MHz
66MHz
MPC603
PBSRAM
PBSRAM
LT1584
STAT
POWER CORE
Flash 512K Flash 512K
Flash 512K Flash 512K
Figure Excimer Minimal System Board
This design uses standard 255-pin pattern allow MPC603x MPC604x device populated. MPC750 design could easily created expanding size additional PBSRAM devices. area allows interfaces attached. Miscellaneous discrete components shown.
Part Conclusion
PowerPC design easily implemented with small amount hardware following examples listed this paper. resulting system will exhibit fast memory access times will allow benchmarking various processors. desired, design enhanced with following features: Stream accesses same page SRAM Handle SRAM deselect parallel with other accesses (even SRAM) eliminate dead-time. Support burst memory Move cycle recognition into state machine; this eliminates clock latency memory cycles Allow address-only cycles
possibilities unlimited.
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10.1 Reference Materials
Table lists several documents which learning design PowerPC system type.
Table Reference Documentation
Document MPC603EUM/AD Rev. MPC604EUM/AD Name MPC603e EC603e RISC Microprocessor Manual MPC604e RISC Microprocessor Manual MPC750 RISC Microprocessor Manual MPC106 Bridge/Memory Controller Manual Processor Cache Module Hardware Details MPC603, MPC603e, MPE603e interface. Details MPC604/MPC604e interface.
MPC750UM/AD
Details MPC750 MPC740 interface. Details back-side cache interface. Details interface, general information memory controller design. Details power supply encoding socket (optional).
MPC106UM/AD
MPCPCMEC/D
10.2 Resources
Table lists many resources that available help understand design PowerPC systems.
Table Resources
What Excimer Reference Design Implementation this application note; VHDL code schematics. Examples MPC60x systems modules. High speed design details Where http://www.mot.com/SPS/PowerPC/ http://www.mot.com/SPS/PowerPC/ http://www.mot.com/SPS/PowerPC/ http://www.mot.com/SPS/PowerPC/
Yellowknife Reference Designs Application Notes
PowerPMC750 Schematics
Example interrupt controller.
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Mfax trademark Motorola, Inc. PowerPC name, PowerPC logotype, PowerPC 603e, PowerPC 604e trademarks International Business Machines Corporation used Motorola under license from International Business Machines Corporation.
Information this document provided solely enable system software implementers PowerPC microprocessors. There express implied copyright licenses granted hereunder design fabricate PowerPC integrated circuits integrated circuits based information this document. Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, disclaims liability, including without limitation consequential incidental damages. parameters vary different applications. operating parameters, including must validated each customer application technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola employees, subsidiaries, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Action Employer.
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Application Note Designing Minimal System Gary Milliorn Moto

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