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Communications Advanced Consumer Technologies Group
AN1766
Application Note
Using SDRAM Controller MCF5307 Integrated Microprocessor
Freescale Semiconductor, Inc.
Dave Lapham Applications Engineering, Imaging Entertainment Solutions Austin, Texas
INTRODUCTION
type memory becoming very popular systems designs. called synchronous DRAM (SDRAM), specifically supports high-speed designs required fully utilize current highperformance microprocessors. MCF5307 integrated microprocessor first ColdFire Family contain Version clock-doubled core. MCF5307 SDRAM controller interface with over 2,000 MBytes DRAM supports bursting page-mode operations. addition, SDRAM controller connect both extended-data-out DRAMs synchronous DRAMs. Running synchronously with system clock rather than responding traditional asynchronous control signals, SDRAM (after initial latency period) read written every clock cycle. 5-1-1-1 burst rate typical MHz. support interleaving, many SDRAM devices contain multiple banks banks have open page time. DRAMs multiplexed address which processor provides address cycles. most significant portion address transmitted first (the row), followed lower
portion (the column). Gated system clock, column latched DRAM together form complete address required identify requested data. multiplexing reduces count packages well number connections chip, lowers memory cost. trade-off this count memory reduction slower performance because mandates additional cycle transmit address. Memory designers have developed interfaces reduce impact this trade-off. example pagemode operation. Page mode sends address portion only once multiple accesses within memory region page). newest concept SDRAM, which accept column addresses every system clock cycle and, after initial pipeline latency period, deliver receive data same rate. SDRAM controllers require higher level sophistication than asynchronous DRAM controllers. only must addresses data managed, SDRAM chips also need special sent from controller initialize memory well instruct memory which operations occur. These commands include instructions precharge, read, write, burst, auto-refresh, various
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combinations these functions. good controller necessary unburden from overhead these tasks. MCF5307 ColdFire synchronous/asynchronous DRAM controller (SADRAMC) performs these functions variety DRAMs through internal configuration registers. These registers programmers controller according specific memory system requirements. SDRAMs operate different fashion than asynchronous DRAMs. commands initiate special actions particularly unique, data pipelines. Commands issued memory using specific encoding address control pins. first operations after system reset must configure SDRAM operating parameters issuing command SDRAM mode register. Using MCF5307 SADRAMC, this only accomplished after setting MCF5307 SDRAM Controller Control Register (DCR), DRAM Address Control Register(s) (DACRx) DRAM Mask Register(s) (DAMRx) appropriately. These registers address space operating parameters controller. Once MCF5307 DRAM controller time begin initialization sequence SDRAM itself. First, (PALL) command sent SDRAM. this, write (bit DACRx register access memory space preferred SDRAM bank. Next, enable refresh writing DACR0 DACR1 then wait until least eight refresh cycles have occurred. this time, Mode Register (MRS) command issued. Writing mode register simply involves setting IMRS DACRx registers then writing SDRAM. address that contains proper information lower bits also upper address bits that access falls established SDRAM space previously programmed into DACRx DMRx registers. This step further detailed Example
MCF5307 SADRAMC SIGNALS
MCF5307 SADRAMC interfaces SDRAMs through following signals: Synchronous Address Strobe (SRAS) indicates valid address present latched SDRAM. Synchronous Column Address Strobe (SCAS) indicates valid column address present latched SDRAM. DRAM Read/Write (DRAMW) asserted (active-low) when write operation performed. will negated (high) read operations. Synchronous DRAM Clock Enable (SCKE). This active-high output registered route directly (clock enable) signal external DRAMs when MCF5307 SDRAM controller operating synchronous mode. signal enables disables clock internal memory chips. When low, memory into power-down mode. Operations suspended, memories enter self-refresh mode. Clock Output (called BCLKO MCF5307) connects input SDRAMs. BCLKO represents clock, such unique SDRAM controller used other purposes throughout system well. Another signal included SDRAM controller EDGESEL, which provide extra hold time signals memory. This signal monitor clock input SDRAM, cause data, address,
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control outputs remain active additional time after BCLKO transitions. more detailed explanation provided MCF5307 Manual. Additionally, CAS[3:0] signals serve output qualifiers masks select specific bytes. These referred SDRAM signals. timing these fixed design industrystandard SDRAMS programmable. When reading from SDRAM, lines must valid clocks prior availability data which they apply. When writing SDRAM, signals will valid coincidentally with data being written. CAS0 affects least significant byte while CAS3 operates most significant byte. Finally, RAS[1:0] MCF5307 used enable either SDRAM banks that controller support. They typically connected chip-select pins SDRAM. table described connection scheme. That because completely applicable only symmetrical memory devices. memory chips that have unequal numbers column addresses some adjustments needed. Both examples included herein will further illustrate this statement. Additional information presented Special Considerations section this document. GENERIC ADDRESS CONNECTION SCHEME
SDRAM SDRAM NOTES RELATING PORT SIZES COLUMN 32-bit port only* 16-bit port only* 8-bit port only 16-bit ports
Freescale Semiconductor, Inc.
MCF5307
GENERAL OPERATION
controller MCF5307 manages interface SDRAM subsystem through control signals RAS, CAS, DRAMW well multiplexing address signals. controller also provides termination access cycle. exact operation these signals configuration on-chip control registers explained manual, will repeated here. However, physical connection from MCF5307 particular SDRAM chip will vary depending exact memory device chosen, first order business determine address signals should routed memory. This Application Note includes examples; however, first worthwhile examine generic address connection scheme used SADRAMC. following table shows physical connections needed operate 16-, 32-bit-wide memory systems. Note that this
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*See Asymmetrical Memory Devices Special Considerations section this document.
This table details column address signals driven physical address pins
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MCF5307. Some differences exist each three possible port sizes. Note that only 8bit ports address from MCF5307. Because 32-bit ports will issue either words longwords when accessed, they MCF5307 signal. Likewise, configuration 32-bit ports uses neither This presents slight problem SDRAM address signal issued physical MCF5307 along with SDRAM address signal A17. While used larger ports, still needed. MCF5307 SDRAM controller provides this changing column address that appears physical processor whenever 8-bit port selected. This determined settings Port Size bits (bits MCF5307 SADRAMC DACRx registers. 8-bit ports, MCF5307 physical will drive logical address during cycle. When 32-bit ports sizes programmed, cycle will drive logical address A16, indicated generic connection scheme. notes generic address connection scheme table identify which physical pins MCF5307 used various port sizes. While Generic Address Connection Scheme table only lists physical MCF5307 pins from fact SDRAM addresses will appear pins MCF5307. Column addresses however, limited pins shown (A17 A25). This permits larger memories future. Complete data sheets this otherMicron memory devices found http://
D[31:16] CAS0 DRAMW RAS0 SRAS SCAS BCLKO EDGESEL SCKE
DATA
D[31:24] DQ[7:0]
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MCF5307
D[23:16]
A[10:0] MT48LC2M8A-10 DQ[7:0]
CAS1
MCF5307 Bank configured Words bits
EXAMPLE
MICRON TECHNOLOGY MT48LC2M8A-10 This part rated speeds MHz. latency clocks with setup hold times. organized MByte 8-bits banks. this example, assume 16-bit- wide port using memory chips. This will give megawords SDRAM.
Connecting physical address lines. create 16-bit port with depth megawords, address signals needed. That address range would from zero 0x1FFFFF. These made addresses, column addresses, bank select line. Because access width bits, used (bytes individually accessed address lines). Starting with which physically MCF5307, combined number address lines needed access megawords row/column muxing MCF5307 SADRAMC would therefore look like this:
EXAMPLE ADDRESS CONNECTIONS SDRAM MCF5307 SDRAM SDRAM COLUMN
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MT48LC2M8A-10
A[9:16,18:20]
ADDRESS
A[10:0]
SDRAM SDRAM COLUMN
SDRAM INITIALIZATION physical connections between processor SDRAM established. Before memory used however, must initialized. After power applied memory clock running stable, msec delay required before SDRAM accepts commands. During this time, MCF5307 DCR, DACRx, DCMRx registers initialized (but enable refresh this time). DRAM Control Register (DCR) this example should loaded with value 0x822B. This value sets controller synchronous operation, enables address multiplexing, programs SCKE clock enable. This value also initiate refresh. Refresh timing (required delay following issue refresh command before activate command given) clocks. This determined spec SDRAM. Finally, Refresh Count (RC) field loaded with value 0x2B (decimal 43). This value programs frequency refresh operations. determine correct field value, divide number clocks allowed between refreshes This result minus gives number load into field. Micron SDRAM spec states maximum time period refresh commands 15.5 msec. This equates 697.5 clocks MHz. convert this field value, perform these calculations: clocks Field 697.5 clocks Field 697.5/16 Field (697.5/16) Field 42.6 Field This result indicates maximum delay between refreshes. value decimal should used hexadecimal).
SDRAM
MCF5307
Freescale Semiconductor, Inc.
This row/column muxing provides necessary address signals (21:01) access 16-bitwide port. mentioned earlier, address signal used. Notice that MCF5307 address signal skipped. generic connection table identifies this used only 32-bit ports. When SADRAMC configured 8bit ports, drives address column address 32-bit ports MCF5307 drives address column address A16. Because this example based 16-bit port, MCF5307 physical address used supply address signal column address, along with address MCF5307 therefore used favor next pin, which A18. This (A18) supplies missing address signal address, also continues addressing sequence providing SDRAM address A18. Because SDRAM column addresses have been accounted for, final task connect additional pins provide remaining addresses. MCF5307 address pins used this task, along with SDRAM Bank Select signal.
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Before issuing commands SDRAM, load appropriate values into DACRx DCMRx registers establish preferred location system memory SDRAM. Again, initiate refresh yet. After this step necessary msec delay been completed, issue (PALL) command setting (bit DACRx register one, then accessing memory location associated SDRAM. Next, enable refresh setting MCF5307 DACRx register (bit one. Micron Technology data sheet specifies delay following PALL command allow banks precharge. This operation places SDRAM idle state. After observing appropriate delay (this good time other peripherals MCF5307) allow memory enter idle state, issue AUTO REFRESH commands. After these commands finished, program SDRAM mode register, normal memory operation begin.
WRITE BURST MODE BURST TYPE BURST LENGTH
latency, while bits define mode operation. establishes write burst mode, while bits 10-11 reserved should programmed with zeroes. mode register setting (binary) 0010 0010 0000 (hex equivalent 0x220) causes SDRAM operate following manner: Burst Length Burst Type Sequential Latency Clocks Operating Mode Standard Operation Write Burst Mode Single Location Access Before SDRAM mode register programmed, must first back examine physical connections. SDRAM will take values presented address lines during mode register load transfer them into mode register. MCF5307 manual states that address lines multiplexed during this operation. Furthermore, because port size bits this example some physical pins used MCF5307. This must also taken into consideration. program SDRAM mode register with value 0x220, look these connections determine individual bits must routed SDRAM. Because SDRAM controller does multiplex address lines while loading SDRAM mode register, individual bits must placed appropriately. write value 0x220 SDRAM address lines, logic must presented SDRAM pins while other pins held logic zero. Therefore MCF5307 should access location 0xnn08 0800. This causes MCF5307 address pins high. These physically connected SDRAM pins which correspond bits SDRAM mode register wish set. data driven will ignored. program this information into SDRAM mode register, IMRS (bit DRAM Address Control register MCF5307 SADRAMC, immediately issue
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RESRV
MODE
LATENCY
MT48LC2M8A1TG-10 Mode Register
Issuing commands SDRAM involves little planning. Because commands issued address lines, commands dispatched simply accessing specific address SDRAM address range that corresponds desired pattern command being given. instance, mode register Micron Technology MT48LC2M8A-10 SDRAM memory chip, first order business determine what information send. mode register SDRAM bits. Bits determine burst length. identifies burst type. Bits
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write address 0xnn08 0800 where upper address bits selected force access occur SDRAM space previously established initializing DACRx DCMRx registers). lower portion address value selected cause proper programming SDRAM mode register. MCF5307 SADRAMC will then command cycle load SDRAM mode register with proper pattern. some instances address used program SDRAM mode register fall outside memory SDRAM. When this happens, write cycle program mode register will cause SDRAM access occur, register will programmed. this case base address SDRAM must temporarily changed DACRx DMRx registers force required address SDRAM space. After mode register successfully programmed, base address desired value. interface from MCF5307 SDRAM uses pins mentioned previously. Because port size bits wide, starting address MCF5307 A15. combined number address signals plus column).
EXAMPLE ADDRESS CONNECTIONS. SDRAM SDRAM COLUMN
SDRAM
MCF5307
Freescale Semiconductor, Inc.
EXAMPLE
TEXAS INSTRUMENTS TMS664814-10 part also operate bus, will easily satisfy timing requirements MCF5307. organized MBytes 8-bits each four banks. Fourteen address pins (named which multiplexed with column addressing capability. Address pins used bankselect pins. this example, assume 32-bitwide port using four memory chips. This will give longwords SDRAM, MBytes. important concept distinguish between physical banks supported MCF5307 SDRAM controller multiple banks that exist SDRAM chips. banks allowed SADRAMC permit different speeds and/or port sizes overall memory system.
Notice that address signals appear row/column address tables. Bytes words directly accessible address signals. This level granularity controlled SDRAM signals. Initialization SDRAM will similar what described first example. There Bank Select signals because Texas Instruments device four banks each SDRAM chip. naming convention these BS1. These perform same fashion signal Micron Technologies part. Micron device just banks chip therefore required only single signal bank selection.
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Freescale Semiconductor, Inc. SPECIAL CONSIDERATIONS
important aware design assumptions that built controller. part design process, certain parameters must constrained order produce efficient reliable controller. These determine controller will operate specific circumstances. Some these conditions listed below: RESET State Following reset MCF5307 processor SADRAMC disabled. must initialized before operation begin. Fixed Page Size controller MCF5307 hard-configured 512-byte page (column) size. Should memories with larger page sizes used, controller will treat access outside 512-byte boundary page. such, will current page issue address page. Mixed Memory Types default (out RESET) mode operation MCF5307 assumes asynchronous DRAMs. This default changed setting (bit DRAM Control Register MCF5307. Once synchronous operation set, cannot reversed except resetting MCF5307. Both banks will operate selected mode. Mixing asynchronous synchronous DRAMs allowed. Each bank contain unique configuration SDRAM. That speeds, port widths, etc. different each banks. External Master Multiplexing While MCF5307 SADRAMC will respond SDRAM accesses alternate masters, will drive address lines provide address multiplexing when this occurs. controller will drive appropriate control signals only. Addresses must, this case, externally multiplexed required.
Bursting Many SDRAMS burst data various amounts; however, controller MCF5307 does support this feature. controller will instead conduct accesses directly controlling address lines. Therefore, variable-length bursting available chosen SDRAM, burst option must enabled, burst length must one. This done setting Mode Register first example. EDGESEL synchronous edge-select input MCF5307 provide additional output hold time SDRAM control signals. usual mode operation buffer that slightly delays BCLKO signal. This delayed signal then routed SDRAM back EDGESEL MCF5307. This will have effect holding signals SDRAM amount buffer line delay, which helps ensure that data held beyond falling edge SDRAM clock input signal. This useful feature with regard meeting memory system timing requirements high-frequency buses. Asymmetrical Memory Devices When asymmetrical memory devices used (i.e. memory chips have more addresses than column addresses), additional addresses will connected using sequential MCF5307 pins until done. That physical pins will skipped. Additionally, ports with only eight column addresses, 8-bit ports with just nine columns, MCF5307 used provide SDRAM address even though noted 16-bit port only. Likewise 16-bit ports with eight column address signals, MCF5307 address used provide SDRAM address more information MCF5307 ColdFire integrated microprocessor,
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Revision History: Rev. Initial Release Corrected maximum size accessible memory. Moved note, expanded form, from bottom Generic Address Connection Scheme table page three text Special Considerations section. Corrected calculation Field value SDRAM Initialization section. Heavily revised description mode register load procedure correct errors 1.0. Fixed miscellaneous typos.
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