AN1755 Freescale Semiconductor, Inc. Interfacing MC68HC705C8

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AN1755 Freescale Semiconductor, Inc. Interfacing MC68HC705C8

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AN1755
Freescale Semiconductor, Inc.
Interfacing MC68HC705C8A DS2430A 256-Bit 1-WireEEPROM
Mark Glenewinkel Field Applications Engineering Consumer Systems Group Austin, Texas
Introduction
This application note describes interface between MC68HC705C8A (C8A) DS2430A 1-Wire 256-bit EEPROM from Dallas Semiconductor. 1-Wire interface reduces overhead control, data, address, power pins found with other EEPROM devices. DS2430A combines these functions. More embedded applications today demanding non-volatile memory storage. instance, some applications which EEPROM technology required are: Reprogrammable calibration data test/measurement equipment Power down information storage consumer electronics like VCRs Identification number storage remote addressing security Storage telecommunication information such phone number recall speed dialing
1-Wire trademark Dallas Semiconductor.
Motorola, Inc., 1998
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Freescale Semiconductor, Inc. Application Note
Circuitry example code provided Code Listing demonstrate interface between parts.
Features
DS2430A provides these features: 256-bit EEPROM (electrically erasable programmable read-only memory) plus 64-bit one-time programmable (OTP) application register EEPROM organized page bytes random access Unique factory-lasered 64-bit registration number ensures absolute identity because devices alike. Reduces control, address, data, power single data Directly connects single port microcontroller Communicates 16.3 Kbits second cost TO-92 6-pin TSOC package Reads writes over wide voltage range volts volts from
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Description
DS2430A bits EEPROM that addressed bytes memory. interface device based proprietary 1-Wire interface. DS2430A four main data components. These are: 64-bit lasered 256-bit EEPROM memory with 256-bit scratchpad (randomaccess memory) 64-bit EEPROM application register with 64-bit scratchpad 8-bit status register
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Application Note DS2430A Hardware Interface
scratchpad acts buffer when writing EEPROM. Eight memory functions give user ability write, read, check status DS2430A. DS2430A unique 64-bit lasered ROM. first eight bits signify 1-Wire Family member being addressed. next bits unique each DS2430A device, allowing more than trillion different devices field. last eight bits (cyclic redundancy check) first bits. 64-bit allows multiple DS2430As bus. Once code matched, memory functions become accessible master issue eight memory commands. data transceived between master DS2430A read written least significant (LSB) first.
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DS2430A Hardware Interface
Pinout Descriptions
bidirectional DATA only interface microcontroller (MCU). Parasitic power derived from required pullup resistor DATA pin. other power input needed DS2430A.
DS2430A
Figure DS2430A TO-92 Pinout
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DATA
Freescale Semiconductor, Inc. Application Note
Block Diagram
PARASITIC POWER
1-WIRE DATA
1-WIRE FUNCTION CONTROL
64-BIT LASERED
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MEMORY FUNCTION CONTROL
STATUS MEMORY BYTE
256-BIT MEMORY SCRATCHPAD
64-BIT REGISTER SCRATCHPAD
DATA MEMORY 256-BIT EEPROM BYTES
64-BIT APPLICATION REGISTER
Figure DS2430A Block Diagram 1-Wire Interface Figure shows hardware interface 1-Wire bus. single master more slave devices. cases, DS2430A slave. important that each device able drive appropriate time. Thus, each device must have open drain three-state outputs. maximum rate allowed 16.3 Kbits second. idle state high. reason transaction suspended, must left idle state transaction resume later time. held more than more slave devices could reset. pullup resistor required ensure proper idling provide parasitic power DS2430A.
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Application Note DS2430A Hardware Interface
MASTER DATA DS2430A 1-WIRE PORT
PORT DIRECTION
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Figure 1-Wire Interface
1-Wire Timing
1-Wire protocol divided into types transactions. These are: Reset presence pulse Write read data
When device idling high state, master starts communicating DS2430A issuing reset pulse. master must drive least After this time, master turns port into high impedance input allows pullup resistor bring back high. Over next master reads looking low. DS2430A active ready communicate, will drive low. master does receive presence pulse, further communication cannot occur. Figure shows reset presence pulse timing.
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Freescale Semiconductor, Inc. Application Note
MASTER VPullup VPullup tRSTL
RESISTOR DS2430A
RESISTOR tRSTH
tPDL
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tPDH tRSTL tRSTH INFINITE, INCLUDES RECOVERY TIME tPDH tPDL
Figure Reset Presence Pulse Timing After presence pulse received, data communicated between master slave. transceived specific time slots that initiated master sending falling edge sync pulse. sync pulse defines start time slot that least long. After this time slot finished, recovery time least required give DS2430A time respond next being transmitted. time slot recovery time together which define maximum communication speed 16.3 Kbits second. Three different time slots generated. They are: Write-one time slot Write-zero time slot Read data time slot
timing diagrams these time slots shown Figure Figure Figure
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Application Note DS2430A Hardware Interface
MASTER VPullup VPullup tSlot tLOW1 tREC INFINITE tLOW1
RESISTOR
DS2430A SAMPLING
tSlot
tREC
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Figure Write-One Time Slot
MASTER VPullup VPullup tLOW0 tSlot tLOW0 tSlot tREC INFINITE DS2430A SAMPLING
RESISTOR
tREC
Figure Write-Zero Time Slot
MASTER VPullup VPullup tSlot tLOWR tRelease tREC INFINITE tRDV tLOWR
RESISTOR DS2430A
RESISTOR
MASTER SAMPLING
tRDV tSlot
tRelease tREC
Figure Read Data Time Slot
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Freescale Semiconductor, Inc. Application Note
step-by-step example protocol needed read DS2430A's status register master transmits reset pulse. master waits presence pulse from DS2430A. Once detected, step master sends skip command DS2430A. Since DS2430A only device bus, match address command needed. code skip %11001100 sent first. Write-zero times Write-one times Write-zero times
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Write-one times After function been sent, DS2430A ready memory function command. code read status register %01100110. Write-zero Write-one times Write-zero times
Write-one times Write-zero DS2430A ready send status register contents bus. master sends eight read data time slots read each store them memory. transaction complete. issue another command, DS2430A must reset again.
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Application Note DS2430A Software Interface
DS2430A Software Interface
transaction sequence access DS2430A over 1-Wire illustrated Figure
1-WIRE INITIALIZATION
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1-WIRE FUNCTION READ MATCH SEARCH SKIP
DS2430A SPECIFIC MEMORY COMMANDS WRITE SCRATCHPAD READ SCRATCHPAD COPY SCRATCHPAD READ MEMORY READ STATUS WRITE APPLICATION REGISTER READ APPLICATION REGISTER COPY LOCK APPLICATION REGISTER
TRANSACTION/DATA
Figure DS2430A Transaction Sequence Initialization transactions start with device initialization routine. This accomplished master sending reset pulse then reading presence pulse from DS2430A.
Function Commands Read
Once master detected presence pulse, commands issued. functions eight bits long. This command allows master read DS2430A's unique 64-bit code. This command used only there single DS2430A bus. Otherwise, data collision will occur. 1-Wire devices have this 64-bit lasered ROM. first eight bits signify
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Freescale Semiconductor, Inc. Application Note
1-Wire Family. next bits unique DS2430A. last eight bits (cyclic redundancy check) first bits. Consult DS2430A data sheet more detail 64-bit ROM. Match more than DS2430A bus, this command allows master address specific DS2430A. Only that matches will communicate with master. other devices will inactive until reset pulse sent. When system many devices bus, master know number devices bus. This command allows master determine contents devices bus. Consult DS2430A data sheet more detail this command. This command save access time only device bus. 64-bit code needed access memory function commands. more than device this command issued, data collision will occur. This application note demonstrates this command access DS2430A.
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Search
Skip
Memory Function Commands Write Scratchpad
After device been addressed correctly with commands, DS2430A ready execute memory functions. This command will write data data memory's scratchpad RAM. command followed address byte then subsequent data. address incremented after each data byte written. Once address hits location $1F, wraps around $00. This command will read data from data memory's scratchpad. command followed address byte subsequent data read. address incremented after each data byte read. Once address hits location $1F, wraps around $00. After data memory scratchpad verified, then transferred data memory EEPROM. After this command
Read Scratchpad
Copy Scratchpad
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Application Note DS2430A Software Interface
validation sent device, bits written EEPROM array. only bytes written EEPROM, scratchpad should contain copy latest EEPROM data before write copy scratchpad commands executed. After copy scratchpad command issued, data line must held high ensure proper programming EEPROM array. Read Memory This command used read data memory EEPROM array. After command issued, whole EEPROM array transferred data memory scratchpad RAM. After read memory command, starting address sent. Data then read byte time. address incremented after each data byte read. Once address hits location $1F, wraps around $00. user wants only copy EEPROM array scratchpad RAM, issue reset pulse DS2430A after read memory command issued. This command will write data application register's scratchpad RAM. command followed address byte then subsequent data. address incremented after each data byte written. Once address hits location $07, wraps around $00. This command used long application register locked. application register already been locked, data written scratchpad will lost. status register used determine application register been programmed locked. validation must sent before status register read. register reads $FF, application register unlocked. register reads $FC, application register locked. This command will read data from application register's scratchpad RAM. application register locked, data read will come directly from EEPROM memory. command followed address byte subsequent data read. address incremented after reading data byte. Once address hits location $07, wraps around $00.
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Write Application Register
Read Status Register
Read Application Register
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Freescale Semiconductor, Inc. Application Note
Copy Lock Application Register After application register's scratchpad verified, then transferred application register EEPROM. After this command vailidation sent device, bits written EEPROM array. application register locked. Additional write accesses will denied. This command used only once. After copy lock application register command issued, data line must held high ensure proper programming EEPROM array.
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Memory
DS2430A's memory comprised three sections called status register, data memory, application register, shown Figure status register indicates application register locked. long application register unprogrammed, status register reads $FF. When application register been programmed locked, status register reads $FC. data memory consists 256-bit EEPROM array 256-bit scratchpad array. arrays addressed 8-bit sections from $1F. scratchpad acts buffer when writing device. application register consists 64-bit EEPROM array 64-bit scratchpad array. bits addressed eight 8-bit sections from $07. Like data memory, scratchpad acts buffer when writing device.
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Application Note MC68HC705C8A Hardware Interface
256-BIT DATA MEMORY
256-BIT EEPROM
64-BIT APPLICATION REGISTER
64-BIT EEPROM
Freescale Semiconductor, Inc.
STATUS REGISTER
8-BIT
Figure DS2430A Memory
MC68HC705C8A Hardware Interface
MC68HC705C8A (C8A) most popular members HC05 Family. total 7744 bytes EPROM bytes RAM. part includes total pins seven input-only pins. Peripherals include serial peripheral interface (SPI) bus, serial communications interface (SCI), 16-bit capture/compare timer. schematic used testing C8A-to-DS2430A interface MMEVS development system shown Figure port used transmit receive data DATA DS2430A. further information C8A, consult MC68HC705C8A Technical Data, Motorola document order number MC68HC705C8A/D.
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Freescale Semiconductor, Inc. Application Note
DS2430A DATA
MMEVS INTERFACE
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Figure C8A-to-DS2430A Interface Test Circuit
MC68HC705C8A Software Interface
driving manipulation process toggling pins with software instructions create certain hardware peripheral. HC05 provides special instructions specifically manipulate single pins. serial transmission driver been into three subroutines: RESET_PULSE RESET_PULSE routine sends reset pulse DS2430A waits presence pulse. presence pulse found, routine goes into error loop. routine takes byte data creates eight time slots either write-one write-zero depending being transmitted. routine transmits eight read data time slots. Each read shifted into byte RAM.
flowcharts DS2430A serial drivers shown Figure Figure Figure Figure shows flowcharts main test routine.
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Application Note MC68HC705C8A Software Interface
Follow this step-by-step sequence tests. Each memory command preceded reset pulse skip command. Read memory. This will transfer contents EEPROM array into scratchpad RAM. Write scratch memory. Starting address $06, write $55. Read scratch memory. Starting address $06, read contents scratchpad RAM.
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Verify that value read from scratchpad location $55. not, error loop. Copy scratchpad. Follow this command with validation $A5. This will copy contents scratchpad array EEPROM array. Hold DATA high allow proper programming EEPROM. Read memory. This will transfer contents EEPROM array into scratchpad RAM. Read scratch memory. Starting address $06, read contents scratchpad RAM. Verify that value read from scratchpad location $55. not, error loop. This routine demonstrates interface software needed communicate with DS2430A. Although used, HC05 Family device could utilize this interface code. Minor adjustments port pins memory maps might necessary. assembly code test routine provided Code Listing.
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Freescale Semiconductor, Inc. Application Note Development Tools
interface created tested using these development tools: M68MMPFB0508 Motorola MMEVS platform board X68EM05C9A Motorola series emulation module Version 1.02 Editor, assembler, debugger Microcomputer Systems
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Application Note Flowcharts Serial Drivers
Flowcharts Serial Drivers
RESET_PULSE
DATA START RESET PULSE
WAIT LOOP,
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MAKE DATA INPUT
CLEAR TEST AccA LOOP
DATA DELAY LOOP
PRESENCE PULSE DETECTED TEST
DECREMENT ACCA
AccA
DS2430A DEAD TEST YES, DS2430A ALIVE DATA MAKE DATA OUTPUT ERROR LOOP
RETURN FROM
Figure RESET_PULSE Subroutine Flowchart
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Freescale Semiconductor, Inc. Application Note
COUNTER 8-BIT TRANSMIT
DATA START TIME SLOT
SHIFT RIGHT EEPROM_WRITE CARRY EEPROM_WRITE
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CARRY DATA
DATA
DRIVE DATA
DATA
DECREMENT
YES, TRANSMISSION DONE RETURN FROM
Figure Subroutine Flowchart
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Application Note Flowcharts Serial Drivers
COUNTER 8-BIT TRANSMIT
DATA START TIME SLOT
MAKE DATA INPUT
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WAIT DS2430A DRIVING DATA
DATA CARRY DATA
ROTATE RIGHT EEPROM_READ PUTS CARRY INTO EEPROM_READ
WAIT COMPLETE TIME SLOT
DATA MAKE DATA OUTPUT
DECREMENT
YES, RECEIVED 8-BIT DATA RETURN FROM
Figure Subroutine Flowchart
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Freescale Semiconductor, Inc. Application Note
START
INITIALIZE PORT DATA DIRECTION PORT
TRANSMIT RESET_PULSE
SKIP_ROM
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READ_MEM COPIES EEPROM SCRATCHPAD
TRANSMIT RESET_PULSE
SKIP_ROM
WRITE_SCRATCH
STARTING ADDRESS SCRATCH WRITE
TEST_DATA WRITE TEST_DATA
TRANSMIT RESET_PULSE
SKIP_ROM
Figure Flowchart Main Test Routine (Sheet
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Application Note Flowcharts Serial Drivers
READ_SCRATCH
STARTING ADDRESS SCRATCH READ
DATA READ EEPROM_READ
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EEPROM_READ TEST_DATA $55?
ERROR FLAG
YES, WRITE SCRATCHPAD VERIFIED TRANSMIT RESET_PULSE
SKIP_ROM
COPY_SCRATCH $A5, VALIDATION COPIES SCRATCHPAD EEPROM
HOLD DATA HIGH WAIT EEPROM WRITE
TRANSMIT RESET_PULSE
SKIP_ROM
Figure Flowchart Main Test Routine (Sheet
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Freescale Semiconductor, Inc. Application Note
READ_MEM COPIES EEPROM SCRATCHPAD
STARTING ADDRESS SCRATCH READ
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DATA READ EEPROM_READ
TRANSMIT RESET_PULSE
EEPROM_READ TEST_DATA $55?
ERROR FLAG
YES, WRITE EEPROM VERIFIED INFINITE LOOP
Figure Flowchart Main Test Routine (Sheet
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Application Note Code Listing
Code Listing
File name: DS2430A.ASM Example Code MC68HC705C8A Interface Dallas DS2430A 1-Wire 256-Bit EEPROM Ver: Date: June 1998 Author: Mark Glenewinkel Motorola Field Applications Consumer Systems Group Assembler: 1.02 code explanation flow charts, please consult Motorola Application Note "Interfacing MC68HC705C8A DS2430A 1-Wire 256-bit EEPROM" Literature AN1755/D NOTE: timing functions based 2-MHz internal clock SYSTEM DEFINITIONS EQUATES Internal Register Definitions PORTA ;PortA DDRA ;data direction PortA Application Specific Definitions DATA DATA_DIR Function Commands READ_ROM MATCH_ROM SKIP_ROM SEARCH_ROM Memory Function Commands WRITE_SCRATCH READ_SCRATCH COPY_SCRATCH READ_MEM WRITE_APP READ_STATUS READ_APP COPY_LOCK Memory Definitions EPROM $160 RESET $1FFE
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;PORTA, data signal ;PortA Data DATA signal
;read ;match ;skip ;search
;write scratchpad memory ;read from scratchpad memory ;copy scratchpad EEPROM array ;read from EEPROM memory ;write application ;read from status ;read from application ;copy lock application
;start EPROM ;start ;vector reset
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Freescale Semiconductor, Inc. Application Note
VARIABLES EEPROM_WRITE ;storage EEPROM write EEPROM_READ ;storage EEPROM read TEST ;test result presence TEST_DATA ;test data EEPROM testing
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MAIN ROUTINE EPROM ;start begining EPROM Intialize Ports START #$01 ;init PORTA PORTA #$01 ;config outputs PORTA DDRA Issue "SKIP ROM" command RESET_PULSE #SKIP_ROM EEPROM_WRITE
;send reset DS2430A
;send Skip
"Read Memory" Command, copies EEPROM scratchpad memory #READ_MEM EEPROM_WRITE ;send Read Memory Issue "SKIP ROM" command RESET_PULSE #SKIP_ROM EEPROM_WRITE
;send reset DS2430A
;send Skip
Issue "WRITE SCRATCHPAD" command, start location Write byte info TEST_DATA #WRITE_SCRATCH EEPROM_WRITE ;send Write Sratch memory #$06 EEPROM_WRITE ;send address TEST_DATA EEPROM_WRITE ;send TEST_DATA Issue "SKIP ROM" command RESET_PULSE #SKIP_ROM EEPROM_WRITE
;send reset DS2430A
;send Skip
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Application Note Code Listing
"Read Scratchpad" Command, start address $06, read byte equal TEST_DATA? #READ_SCRATCH EEPROM_WRITE ;send Read Scratch memory #$06 EEPROM_WRITE ;send address ;receive data from addr EEPROM_READ TEST_DATA PASS ERROR1 ;does data read TEST_DATA? ;bad read, stay here
ERROR1 PASS
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Issue "SKIP ROM" command RESET_PULSE #SKIP_ROM EEPROM_WRITE
;send reset DS2430A ;send Skip
Issue "Copy Scratchpad" command with validation #COPY_SCRATCH EEPROM_WRITE ;send Copy Scratch memory #$A5 EEPROM_WRITE ;send validation Hold DATA=1 wait 100ms, EEPROM being programmed bset DATA,PORTA ;hold DATA NV_WAIT ;wait routine 100ms Issue "SKIP ROM" command RESET_PULSE #SKIP_ROM EEPROM_WRITE ;send reset DS2430A ;send Skip
Issue "READ MEMORY" command, copies EEPROM scratchpad memory Start address #READ_MEM EEPROM_WRITE ;send Read Memory #$06 EEPROM_WRITE ;send addr Read byte, verify against TEST_DATA ;receive data from addr RESET_PULSE ;send reset DS2430A EEPROM_READ TEST_DATA DUMMY ERROR2 DUMMY ;does data read TEST_DATA? ;bad read, stay here ;test sequence over
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Freescale Semiconductor, Inc. Application Note
SUBROUTINES Routine creates reset pulse then checks presence pulse from DS2430A presence pulse, goto error loop
Create greater than 480usec reset pulse RESET_PULSE bclr DATA,PORTA #160T wait 481usec deca bclr DATA,DDRA ;DATA input Wait greater than 480usec, look presence pulse, TEST will equal presence detected TEST #69T ;wait 483usec brset DATA,PORTA,J3 DATA=1? bset 0,TEST DATA=0, presence detected TEST deca branch same time decrement Acca done?
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Check TEST, TEST=$01, then TEST=$00, then goto error routine brset 0,TEST,J5 ERROR3 ERROR3 bset DATA,PORTA bset DATA,DDRA
;TEST ;presence pulse detected, error ;TEST passed, DATA=1 ;DATA output
Routine takes contents EEPROM_WRITE transmits serially serially DS2430A, first ;set counter Drive DATA=0 9usec WRITE bclr DATA,PORTA bset bclr EEPROM_WRIT DATA,PORTA DATA,PORTA
DATA=0, start time slot Carry DQ=1 branch clock_it ;5DQ=0 ;3evens
this point, 10.5usec expired either being transmitted DATA must wait least 49.5usec, routine below 52usec #17T deca
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Application Note Code Listing
Make sure DATA=1, then wait more than 1usec recovery time bset DATA,PORTA DATA=1 decx WRITE bits transmitted? ;return from
Routine clocks DS2430A read data from DATA, first contents EEPROM_READ ;set counter Drive DATA=0 1usec, READ bclr DATA,PORTA bclr DATA,DDRA Wait usec, then sample DATA deca read data wait 50µsec brclr DATA,PORTA,J10 EEPROM_READ
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DATA=0, start time slot make DATA input
carry DATA carry into EEPROM_READ
this point, 15.5µsec expired since time slot started must wait least 44.5µsec, routine below 46µsec #15T deca Make sure DATA=1, then wait more than 1usec recovery time bset DATA,PORTA DATA=1 bset DATA,DDRA make DATA output decx READ bits received? ;return from
Routine creates ~100ms routine with 2MHz internal memory correctly NV_WAIT #132T #255T deca decx
VECTOR TABLE RESET START
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Freescale Semiconductor, Inc. Application Note
References
MC68HC705C8A Technical Data, MC68HC705C8A/D, Motorola, 1996. M68HC05 Applications Guide, M68HC05AG/AD, Motorola, 1996. DS2430A Datasheet, Dallas Semiconductor, 1997.
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Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
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AN1755 Freescale Semiconductor, Inc. Interfacing MC68HC705C8

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