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AN1753 Freescale Semiconductor, Inc. Implementing FLASH Memo


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AN1753
Freescale Semiconductor, Inc.
Implementing FLASH Memory System MC68HC711E9 Design
Haas Applications Engineering Body Electronics Strategic Industrial Division Austin, Texas
Introduction
FLASH technology offers several advantages M68HC11 microcontroller design. Field updates, lower-power consumption, increased memory densities potential benefits incorporating external FLASH memory firmware/data media. However, several drawbacks provide significant obstacles implementation M68HC11 system. Most difficulties with FLASH memory implementation derive from fact that FLASH requires algorithm program data. Many FLASH devices cannot perform read operations during programming cycle, algorithm must maintained memory device physically separated from FLASH programmed. Thus, additional memory device needed hold programming algorithm. Typically, this device will occupy upper slot M68HC11 memory maintain interrupt vectors. This necessitates need jump table route these static interrupt vectors which increases interrupt response latency. interrupts that desired programming algorithm also must subjected arbitration
Motorola, Inc., 1998
AN1753
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Freescale Semiconductor, Inc. Application Note
mechanism which adds both latency documentation overhead firmware development maintenence. Bootstrap mode M68HC11 Family could used upload FLASH programming algorithm, this also several drawbacks. example: limited size, cannot hold algorithm complexity. External available, depending design. external non-volitile, temporary program space could corrupt previously stored data. Bootstrap mode requires special data sequence which compatible with manual download from terminal thus requires special boot loader running host system. Depending crystal frequency, bootstrap serial communication parameters specify serial data rate which isn't supported standard boot loader.
Freescale Semiconductor, Inc.
most applications, these difficulties, much less them, could easily eliminate possiblity implementing FLASH device. This application note describes single board computer (SBC) design which uses FLASH device main program/data storage media. emphasis hardware firmware techniques used implement FLASH programming system well impact firmware development. Also, example retrofit design included illustrate these techniques modified convert existing EPROM-based design FLASH.
AN1753 More Information This Product, www.freescale.com MOTOROLA
Application Note System Requirements
System Requirements
While many aspects design presented here varied needs particular application, there some features that must present support FLASH system described here. Typically, FLASH data originates from host system (for instance, which necessitates need programming host connector. host port connector must bring MODA/MODB pins, well (serial communications interface) pins (PD0/PD1), ~XIRQ (optional), RESET. FLASH device used that requires external source, this signal also required host port. This requirement depends system design. source placed target system, will represent fixed cost final design that will erode per-unit cost margins. Moving this source target onto host programming interface reduce overall costs number target systems significantly higher than number programming systems. Finally, small segment (four bytes) EEPROM must reserved programming firmware. Providing ~XIRQ signal host system optional. Doing will allow in-circuit factory programming 68HC711E9 EPROM. same host system used both FLASH EPROM programming operations which support factory environment where virgin FLASH devices placed target circuit board in-circuit programming part test procedure. this case, special considerations should given ~XIRQ circuit, used target design, this signal subjected voltage levels excess volts during EPROM programming operations.
Freescale Semiconductor, Inc.
Host Interface Description
Figure shows schematic system used this example. host port connector implemented with 10-pin dual connector (P1) which connects programming interface card. Most signal connections straightforward except (PD0) signal. Here, resistor used passively switch signal when programming interface connected. This allows target system share serial port between FLASH programming host another target resource.
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Freescale Semiconductor, Inc.
Application Note
+12V
fA[18.13]
fA18
68HC711E9 8.00M
XTAL
EXTAL R/~W
2.7K
34164
22uF
rst1
~reset
R/~W
RESET
~irq ~xirq
~RESET ~IRQ ~XIRQ
74HC573
DATA ADDR
~reset ~IRQ
68HC24FN
34064
MODA/LIR MODB/VSTBY
rst1
MODE TEST
~reset ~irq
MISO MOSI ~SEL
~RTS/DIR
MODA
fA13 fA14 fA15 fA16 fA17
D0(11) D1(12) D2(13) D3(15) D4(16) D5(17) D6(18) D7(19)
(10)A0 (9)A1 (8)A2 (7)A3 (6)A4 (5)A5 (4)A6 (3)A7 (25)A8 (24)A9 (21)A10 (23)A11 (2)A12 (26)A13 (27)A14 (1)A15
stra strb
stra strb
~fcs ~R/W
M29F040-150P
(20)/E (22)/G
PGM/test ~CTS
~fcs also window $2000-3FFF fA[18.13] bank select port resides @$0200-03FF. because window logic, fA[] sigs used general purpose outputs. rA[18.13] bank select port resides @$0400-05FF rA[] used general purpose outputs.
$4000-5FFF $6000-7FFF $0600-07FF $0A00-0BFF $0C00-0DFF $OE00-0FFF
~rcs ~acs ~rec ~iocs0 ~iocs1 ~R/W fA[18.13]
fA13 fA14 fA15 fA16 fA17 fA18
10uF
~Ren
10uF
More Information This Product, www.freescale.com
10uF
10uF
MAX232
rA13 rA14 rA15 rA16 rA17 rA18
*$8000-FFFF
~fcs
i/o0 Vcc1 Vcc2 i/o16 i/o1 i/o17 i/o2 i/o18 i/o3 i/o19 i/o4 i/o20 i/o5 i/o21 i/o6 i/o22 i/o7 i/o23 i/o8 Mach215 i/o24 i/o9 i/o25 i/o10 i/o26 i/o11 i/o27 i/o12 i/o28 i/o13 i/o29 i/o14 i/o30 i/o15 i/o31 clk0/i2 clk1/i5
R/~W
MEZ11.PDS file design source code, MEZ11.JED holds jedec programming data.
Drawn Date Des. chk'd Rel. date
D36J95
4/12/98 01/03/97 01/03/97
TITLE:
mez11.schem
Page size
comTX comRX
MEZ-11
PT#:
AN1753
MOTOROLA
Figure Schematic
Application Note System Requirements
With programming module removed, signal passes from target RS-232 receiver (U9) (U1) resistor only consideration keep resistor value enough that will interact with input capacitance form pass filter while providing enough impedance that driver contention eliminated. eliminate filter effects, following must satisfied: 1/(23fc)
Freescale Semiconductor, Inc.
Where value ohms, maximum desired baud rate (bits second), total capacitance farads (input stray capacitance). used here account third order harmonics which significant component square wave signal. Kbaud, this value calculates approximately practice, values recomended. only difficulty with this mechanism involves nature target resource; must able tolerate serial traffic that present during programming without producing unknown undesirable results.
NOTE:
FLASH programming baud rate usually related target resource baud rate. This compound difficulty fact that baud rate mismatch cause known data streams baud rate appear pseudo-random data streams another. situations where this problem, more involved switching mechanism required.
mentioned earlier, specialized programming interface card offer convenient cost-effective host interface. programming interface card used this design shown Figure features RS-232 transceiver, loop-back switch, voltage converter, reset controller. reset controller implemented with MC68HC705K1 microcontroller which contains simple program that interprets control switches manipulates target signals appropriately.
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Freescale Semiconductor, Inc.
Application Note
+12V
CONT
4066
HOST RS232
SHORT
MAX232
SHDN
4066
10uF
CONT
CONT
4066
OPEN
CONT
4066
10uF
10uF
C1GND
c210
10uF
10uF
MAX662A
MODB MODA
~Vppen
4049
test
68HC705K1P
3.3K
mode
reset osc1 osc2
3.3K
2.00M
MODA 2N2222A
~MODled
~Vppen
pb1/osc3
4049
mode
OPEN
~MODled
0.1uF
MODB 2N2222A
4049
OPEN
SHORT
mode
monitor
4049
target reset
+12V
More Information This Product, www.freescale.com
Reset state: ~Vppen MODA/B hi-z SHORT OPEN
Drawn Date Des. chk'd Rel. date
LM78L05
4049
5/28/98
TITLE: Page size
0.1uF
4049
10uF
FLASH host adapter
PT#:
AN1753
MOTOROLA
Figure Host Programming Adapter Schematic
Application Note System Requirements
following describes button functions: Target RESET (SW1) Connected target reset (input/output) signal. When activated boot mode, target signals briefly "shorted" loop-back activity. normal mode, target system simply reset loop-back). MONITOR (SW2) When normal mode, this function toggles host source between target signals. third state connects host RXD/TXD target PD0/PD1 (respectively). This function active bootstrap mode. MODE (SW3) This toggles target system between normal mode boot mode. MODA/MODB control output high-Z normal mode bootstrap mode. (SW4) bootstrap mode, allows source toggled off. This function active normal mode.
Freescale Semiconductor, Inc.
monitor function uses module's loop-back switch selectively route target signals (MCU PD0/1) host serial port when target normal mode. This allows host easily trace serial data from either side target system's interface which useful system level debugging tool. Program Listings Host Interface Reset Controller Listing shows reset controller assembly source code. code structure relatively straightforward, consisting initialization, main loop, ~IRQ service routine. Initialization begins ENTRY label consists setting port port DDRs (data direction register) initializing port outputs. main loop begins label which continuously polls push button inputs. button push detected, firmware loops until released. Switch edges debounced 20-ms timer help prevent false signals switch noise. After switch release detected, firmware processes selected button's function.
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Freescale Semiconductor, Inc. Application Note
interrupt routine IRQI traps falling edges reset button. Since reset button also connected target reset signal, resets originating with target system will trapped also. This way, reset sequence handled properly, matter what reset source.
System Memory
Freescale Semiconductor, Inc.
Figure illustrates memory that being demonstrated this application note. addition normal resources (on-chip RAM, registers, EEPROM), there FLASH memory device, external RAMs, some external registers. FLASH slots contain devices Mbit (512 Since this exceeds 64-K addressing space M68HC11, bank switching scheme used page through large density devices using signals resolve upper physical address signals. While device(s) simply direct replacement resolve upper address signals, paging scheme FLASH device more complicated. First, desire fixed portion FLASH memory visible upper portion memory ($8000 through $FFFF). This will hold interrupt vectors well Kbytes kernal ROM, which intended hold core operating system. Intuitively, this window should reside FLASH physical address space where banked address signals A[18:15] [1111]. This forces access addresses range $8000 $FFFF access FLASH memory physical addresses $78000 through $7FFFF regardless current bank setting. addition kernal window $8000-$FFFF, separate 8-Kbyte window used access remainder FLASH device addresses $2000 through $3FFF (referred "mirroring"). Addresses this range will access full physical device from $00000 $7FFFF, depending combination A[12:0] bank selects. A[18:13] vector mirror window determined only value bank register.
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Application Note System Requirements
$FFFF $E000 FLASH KERNAL $C000 $B7FF $B600 $A000 EEPROM
$FFFF $E000 EPROM
$C000 $B7FF $B600 $A000 BOOTROM EEPROM
$8000
$8000 DEVICE DEVICE $6000 BANK BANK $4000
Freescale Semiconductor, Inc.
$6000
$4000
$2000
FLASH WINDOW REGISTERS EXTERNAL REGISTERS NORMAL MODE
$2000
FLASH WINDOW REGISTERS EXTERNAL REGISTERS EXPANDED BOOT MODE HPRIO
$0000
$0000
Figure Target System Memory logic circuit used combine address signals bank select signals into physical address vector that connected FLASH device. This logic circuit needs force physical address[18:15] [1111] $8000-$FFFF pass bank selects physical address [18:13] accesses $2000-$3FFF. Since kernal window takes upper half memory map, signal used force physical address source. Since resulting physical address connected exclusively FLASH device, only needed switch between FLASH windows. Since logic required implement this project relatively simple, behavioral level schematic sketched using off-the-shelf logic
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Freescale Semiconductor, Inc. Application Note
devices. schematic's sum-of-products representations were then extracted manually shown Table Table Memory System Logic Equations
fA[18:15] ~(~lat[5:2] ~A15) lat[5:2] fA[14:13] ~(~(lat[1:0] ~A15) ~(A[14:13] A15)) ((lat[1:0] ~A15) (A[14:13] A15))
Freescale Semiconductor, Inc.
~fcs
~(~(~(~A15 ~A14 A13) ~A15) ~(A[15] ~A[15] ~A[14] A[13]
~rcs ~acs ~ref ~rer
~A15 ~A13) ~A15 A13) ~A15 ~A14 ~A13 ~A12 ~A10 ~R/W ~(~A15 ~A14 ~A13 ~A12 ~A10 R/W) ~A15 ~A14 ~A13 ~A12 ~R/W ~(~A15 ~A14 ~A13 ~A12 R/W)
Table forms basis (hardware definition language) file used generate JEDEC (Joint Electron Device Engineering Council) fuse FPGA (field programmable gate array). (The complete design file appears Program Listings FPGA Listing Listing fA[18:13] vector represents physical FLASH address. (A[12:0] obtained directly from MCU.) FPGA required, offers many advantages over discrete logic implementation. seen Table several logic devices would required implement logic functions shown. This greatly increases component count board space required implement design, problems which eliminated using appropriate FPGA.
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Application Note Programmer Core
Programmer Core
With aspects target design frozen, consider techniques needed FLASH programming system. FLASH system described here lies some subtleties 68HC711's bootstrap mode. bootstrap mode features interest are:
Freescale Semiconductor, Inc.
When reset bootstrap mode, EPROM forced temporarily. While waiting download begin, serial break ASCII NULL character received will force instruction fetch jump EEPROM $B600 begin executing code there. When reset boot mode, sends break SCI.
this application, FLASH programming firmware placed EPROM, which normal mode, allowing programming firmware "hidden" from target application. application firmware developer, system looks like 68HC711 expanded mode, with extended array memory resources. only necessary that developer concerned with these FLASH system requirements: EEPROM locations $B600-$B605 reserved FLASH (holds jump EPROM three FLASH personality data bytes). FLASH uses during programming mode.
latter important only system must battery maintenance non-volatile storage. Since there sufficient resources ample external NVRAM, this should issue most designs.
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Freescale Semiconductor, Inc. Application Note
FLASH Operation first step initiating FLASH program mode connect programming interface place system programming mode. This will reset target bootstrap mode loop-back switch MCU. When reset bootstrap, M68HC11 Family will issue break subsystem. looping back serial break that originates from 68HC711E9, forced jump $B600 (the start EEPROM). pre-placed instruction $B600 (programmed along with EPROM) allows system automatically execute EPROM code with host intervention. timer reset controller switches loop-back feed-through that commands data exchanged between host target systems after reset sequence complete. This topology provides scenario getting execute code bootstrap reset. code must manipulate some additional resources system into mode which will allow FLASH programming occur. code must: FLASH command processor Turn EPROM Turn expanded mode (set HPRIO)
Freescale Semiconductor, Inc.
While bootstrap mode, expanded mode cannot enabled until EPROM turned which requires subsequent reset take effect. This step could performed automatically EPROM code probably best left host command function. illustrate why, consider that EPROM must turned completion FLASH programming session. programming session consist several data upload operations, depending many devices programmed their data segmented. This make difficult target system determine when host actually finished. best scenario host explicitly command target turn EPROM, with same being true EPROM full reset sequence programming session would then proceed this way: Reset bootstrap mode Host commands EPROM
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Application Note Programmer Core
Reset again (still bootstrap mode) Perform programming operations Host commands EPROM Reset normal mode
FLASH Algorithm
Freescale Semiconductor, Inc.
bulk FLASH algorithm derived from simple command line-based EPROM programmer written M68HC11 (reference This code uses command parameter parsing system perform device selection, programming operations, status, download upload protocols, etc. original device selection topology kept such that each device memory appears separate selectable device algorithm. command lines gathered interrupt mode, which buffers incoming characters until <cr> ($0D) received. system flag then which signals command parser examine buffer valid command/parameter combinations. <XON>/<XOFF> handshaking also supported control ASCII upload/download transfers. Handshaking important because programming sequence take several milliseconds buffer must frozen that time ensure data integrity until data been transferred target device. heart data transfer system adapted from BUFFALO S-record transfer code. This code been modified support buffered data, well xmodem transfer protocol. xmodem transfer protocol (aka Christiensen Protocol) transfers Motorola S-record data 128-byte blocks features flow control error detection with retries. While S-records feature line-by-line checksum which used validate data integrity line, typical ASCII transfer protocols provide error detection retries only recourse checksum error target discard entire line continue next line which requires another pass fully program device. checksum error xmodem protocol causes data block resent pre-determined maximum retry count). this way,
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Freescale Semiconductor, Inc. Application Note
system only detect errors, also recover from them. original data error free, there measure assurance that xmodem will transfer data that received entirety. subroutines used access target devices: REDbyt PGMbyt
Freescale Semiconductor, Inc.
These routines index register bank register point physical device address which provided with upload data from host using Motorola record formats. BANK command allows manual selection 64-K segments that Motorola format used. REDbyt PGMbyt call address parser subroutine addrFLA resolve bank select address bits selected device present them accordingly. index register then converted logical address which points desired physical address. Once this procedure complete, present indexed read/write sequences target device perform desired operation. personality system used which allows device defined programming algorithm. This important because algorithm must distinguish between FLASH, NVRAM, shadowRAM, EEPROM technologies. While most devices allow data simply read programming mode, some require pre-command before data presented device. accomplish this, each device system read/write subroutine which handles required command sequences.
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Application Note Retrofit Example
Retrofit Example
CONTROL LOGIC CMOS LOGIC
SYSTEM MEMORY
ADDR[14:0]
Freescale Semiconductor, Inc.
68HC711E9
ADDR[9:0]
DATA[7:0]
RS-232 XCVR
SERIAL
SYSTEM MEMORY: ROM1 ROM2 WINDOW) RAM1 8Kx8 RAM2 2Kx8 I/O: EXTERNAL
PORTS BITS) BITS)
Figure EPROM-Based Design Example Figure illustrates block diagram MCU-based system that uses EPROM memories code data storage. desired that this system converted that FLASH devices used, only minimal hardware modifications allowed cost constraints.
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Freescale Semiconductor, Inc. Application Note
EPROM (U3) primary code memory located memory shown Figure EPROM (U4) used hold secondary code data application. Since these devices would exceed available address space, bank switched 16-K window with provisions allow expansion device. Since only three bank select lines required, they derived directly from pins.
$FFFF
$FFFF EPROM KERNAL ($8000-$FFFF) $E000 EPROM
Freescale Semiconductor, Inc.
$E000
$C000 $B7FF $B600 $A000 EEPROM
$C000 $B7FF $B600 $A000 BOOTROM EEPROM
$8000
$8000
$6000
DATA EPROM WINDOW
$6000
$4000 NVRAM REGISTERS EXTERNAL NORMAL MODE
$4000
$2000
$2000 REGISTERS EXTERNAL EXPANDED BOOT MODE
$0000
$0000
Figure Retrofit Example System Memory primary difference between this system presented earlier lies fact kernal memory only accessible single window memory map. Furthermore, several resources also occupy this memory space during bootstrap mode, including EPROM, which provides serious hurdles implementing FLASH system.
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Application Note Retrofit Example
Freescale Semiconductor, Inc.
bootROM EEPROM conflicts addressed firmware. EEPROM, this part FLASH array will never accessible anyway, system code data will ever need written this area. reliability reasons, necessary write those FLASH locations during FLASH pre-erase cycle. Since EEPROM cannot turned without reset, only choice firmware blind write these locations. This accomplished because M68HC11 Family drives external address data during writes internal resources. This allows FLASH programming commands written device, prevents reads from FLASH because internal resource takes priority. While optimal, this will least serve improve reliability reducing over-erase stress these memory cells. Since bootROM overlaps memory that accessible MCU's normal mode, desirable that system able read/write/verify these memory locations. This done briefly turning bootROM using RBOOT HPRIO register. important suspend interrupts this process that ~XIRQ must enabled. This because bootROM holds interrupt vectors bootstrap mode interrupt which occurs while bootROM will result false vector fetch, causing unrecoverable system disruption. Since FLASH algorithm used here depends interrupts, they disabled entirely, instead must disabled only during time that bootROM off. EPROM conflict more difficult overcome EPROM cannot turned like bootROM reset required). Since covers large important area memory map, also ignored, blind programming acceptable there ensure data integrity without overstressing FLASH core. only viable alternative external (U5) hold FLASH algorithm that EPROM turned off. Normally, this would offer another difficulty fact that NVRAM holds vital system data that would have saved restored host system. this case, however, shadow which means that this device keeps non-volatile data shadow EEPROM array separate from SRAM array (all
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Freescale Semiconductor, Inc. Application Note
same die). Special read sequences initiate store-and-retrieval operations which copy data between SRAM EEPROM. This means that FLASH algorithm copied into SRAM array without disturbing shadow EEPROM data which eliminates need host save restore data. When programming operation complete, original data restored automatically system power-up. Because FLASH algorithm must copied SRAM, additional step required reset sequence.
Freescale Semiconductor, Inc.
Reset bootstrap mode Host commands EPROM (set ROMON CONFIG) Reset again (still bootstrap mode) Copy algorithm Turn EPROM off; clear ROMON CONFIG Reset again (still bootstrap mode) Perform programming operations Reset normal mode (cycle target system power restore data)
this point, system behaves same described under system. host read, write, erase devices needed using commands provided FLASH algorithm operating RAM.
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Application Note Retrofit Example
Retrofit Hardware Changes
required target hardware changes retrofit system are: Expand sockets pins connect signals. programming mode connector. This system already external serial port connection, mode connector only requires MODA/B, RESET, signals. also added support programming mode interface.)
Freescale Semiconductor, Inc.
readily apparent, hardware changes minimal. costs associated with these changes will focus minimal engineering effort modify layout re-tooling costs from vendor. this case, increased component costs less than percent finished product cost. While modifications target system relatively small part overall product cost, addition programming adapter results noticeable cost increase. Even these costs minimized design Figure illustrates. This simple example host interface card which uses simple toggle switch select mode enable inexpensive DC-DC converter develop FLASH voltage.
NOTE:
serial loop-back switch present this module. Since cost issue, loop-back switch omitted, which requires host send break signal ASCII-NULL after each reset.
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Freescale Semiconductor, Inc.
Application Note
PROG
MODE
SHDN
NORM
C1GND
~reset
MAX662A
MODA
MODB
Target
RESET 2.4K
100mA self-resetting fuse
More Information This Product, www.freescale.com
2N2222
Drawn Date Des. chk'd Rel. date
6/30/95 6/30/95 6/30/95
TITLE:
Page size
Host Module
PT#:
AN1753
MOTOROLA
Figure Simplified Host Programming Adapter Schematic
Application Note Conclusion
Freescale Semiconductor, Inc.
While this retrofit example illustrates means implementing FLASH existing design with minimal hardware changes, some compromises necessary meet that end. Some systems have array available temporary algorithm storage. those that feasible shadow because these devices available only from limited number suppliers. these situations, necessary implement techniques described design which would require additional hardware modifications. These trade-offs must examined system designer determine best most cost-effective route upgrade their system.
Conclusion
systems techniques described this application note demonstrate feasibility implementing external FLASH memory system M68HC11 design with minimal hardware/firmware overhead. Since FLASH support virtually transparent normal mode, requires minimum effort part firmware designers avoid resource conflicts. addition, firmware data updates straightforward accomplished using simple terminal program running host
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Freescale Semiconductor, Inc. Application Note Program Listings
Host Interface Reset Controller Listing
PROC "6805"
flash mode controller FFlash programming system. Using buttons, this system controls reset, moda/b, vpp, communications switching. RESET(PA3/~IRQ): when target reset sensed: ;NORM: action ;PGM: after ~reset released,close SHORT connection feed back break signal. ~irq detect falling edge ~reset. VPP(PA0): PGM: This switch toggles ~vppen signal (PB1). NORM: switch effect. MODE(PA1): Toggles MODA/B signal (PB0) between logic hi-z. activity this input also disables Vpp. MODA/B mode.MODA/B hi-z NORM mode. MONITOR(PA2): PGM: this switch effect NORM: This switch cycles through three states: mode SHORT OPEN I/O: reset: mode: (same I/O) normal communications with target. monitors info originating FROM target. monitors info directed target. state status saved that after entering mode returning NORM mode, state setting restored last selected. POR:
Freescale Semiconductor, Inc.
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Application Note Program Listings
Freescale Semiconductor, Inc.
power-up, port initialization follows: inputno pull-downs pulldown input input input input ;Thu, 1996, 11:14 INCLUDE 0200 0201 0203 0205 0207 0209 020B 020D 020F 0211 0213 0215 0217 0219 021B 021D 021F 0221 0222 0225 0227 0229 022B 022D 022F ENTRY A608 B710 A601 B711 A602 B701 B705 A660 B700 B7E2 A6F0 B704 A603 B708 A682 B70A "a.equ"
LEVEL|LVIE|SWAIT ;mask option register settings reset stack pull-downs
#restarg PDRA #modab PDRB #vppen IDRB IDDRB #OPEN|txm IDRA MONREG #rxm|OPEN|txm|SHORT IDDRA #RT1|RT0 TSCR #IRQE|IRQR ISCR
DDRs
init monitor register
timer, 65.5ms, enable enable ints
01050C BRCLR AD52 2408 B601 A802 A4FE B701
MODAB,IDDRB,:01 VPPSW IDRB #vppen #~modab IDRB
skip normal mode switch toggle always leave this
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Freescale Semiconductor, Inc. Application Note
0231 0233 0235 0237 0239 023B 023D 023F 0242 0244 0246 0248 0248 024A 024C 024D 024E 024F 0250 0251 0252 0254 0256 0259 025B 025D 025F 0261 0265 0267 0269 026B 026D 026F 0271 AD57 2421 A602 B701 B605 A801 B705 000506 B6E2 B700 200E BRSET MODSW #vppen IDRB IDDRB #modab IDDRB MODAB,IDDRB,dopgmrst MONREG IDRA
mode switch disable toggle mode
;skip restore mode restore monitor setting
Freescale Semiconductor, Inc.
dopgmrst 1700 BCLR 1604 BSET A660 B700 0005C9 BRSET AD3E 24C5 B600 A4F0 A160 A610 200A A110 2604 A640 2002 not1 not2
RESTARG,IDRA RESTARG,IDDRA
force retarg .autotrip target reset
#txm|OPEN IDRA MODAB,IDDRB,TOP MONSW IDRA #txm|OPEN|SHORT|rxm #txm|OPEN #rxm doall #rxm not2 #txm doall
mode skip mode monitor switch?
state
state state
0271 0273 0275 0277
#txm state not3 A660 #txm|OPEN state B700 doall IDRA B7E2 MONREG 20A9 xxxSW routines test switch closure (with debounce). return, switch switch cycled. 01000C AD2A VPPSW BRCLR vPPON,IDRA,:04 dly20ms AN1753
0279 027C
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MOTOROLA
Application Note Program Listings
027E 0281 0284 0286 0287 0288 0289 028A 028D 028F 0292 0295 0297 0298 0299 029C 029E 02A1 02A4 02A6 02A7
010007 0000FD AD22 0300FB AD19 0300F6 0200FD AD11 0500EC AD0A 0500E7 0400FD AD02
BRCLR vPPON,IDRA,:04 BRSET vPPON,IDRA,:03 dly20ms BRCLR BRCLR BRSET BRCLR BRCLR BRSET dly1ms does MODE,IDRA,:04 dly20ms MODE,IDRA,:04 MODE,IDRA,:05 dly20ms
MODSW
Freescale Semiconductor, Inc.
MONSW
MONITOR,IDRA,:04 dly20ms MONITOR,IDRA,:04 MONITOR,IDRA,:06 dly20ms
simple loop delay 20ms
02A8 02AA 02AC 02AD 02AF 02B0 02B2 02B3 02B4
A614 AD04 26FB AEA6 2046
dly20ms dly1ms DECA dly1ms #166 count (@2mhz) delay count patch ms1val
newdly1
02B6 02B7 02B9
26F9
DECX RTII does timer. TSCR #RTIFR TSCR prescaler
02BA 02BC 02BE 02C0
B608 AA04 B708 3AE0
RTII
reset flag
AN1753 MOTOROLA More Information This Product, www.freescale.com
Freescale Semiconductor, Inc. Application Note
02C2 02C4 02C6 02C8 02CA 02CC 02CD 02CF 260B A60F B7E0 B6E1 2703 B7E1 #psval prescaler TIMER1 DECA TIMER1 operate reset detect BRCLR MODAB,IDDRB,:11 #SHORT|txm IDRA dly20ms BCLR RESTARG,IDDRA BRCLR RESTARG,IDRA,:12 BRCLR MODAB,IDDRB,nopgm TEMP dly20ms TEMP #OPEN|txm IDRA dly20ms #IRQE|IRQR ISCR yet,
value decrement, timer value
alg. skip reset normal mode
Freescale Semiconductor, Inc.
02D0 02D3 02D5 02D7 02DA 02DC 02DF 02E2 02E4 02E6 02E9 02EB 02ED 02EF 02F1 02F4 02F6 02F8
010504 A6C0 B700 CD02A8 1704 0700FD 01050F A61E B7E3 CD02A8 3AE3 26F9 A660 B700 CD02A8 A682 B70A
IRQI
force reset input skip reset normal mode delay 600ms
nopgm
AN1753 More Information This Product, www.freescale.com MOTOROLA
Application Note Program Listings
FPGA Listing Listing
TITLE 'HC11 bank expander PATTERN indexer.PDS REVISION AUTHOR Haas COMPANY DATE November 1996 DATE November 1996 Creation Tue, 1996, 14:42 Removed fLAT.SETF fLAT.RSTF equations (were invalid) changed lefck active design verified in-circuit logic analyzer
Freescale Semiconductor, Inc.
CHIP
bank_logic11
MACH215
;PIN D[5.0] PAIR fLAT[5.0] A[11] COMB A[10] COMB ;PIN A[9] COMB A[15] COMB A[14] COMB A[13] COMB A[12] COMB 21.16 rA[18.13] ;PIN ;PIN /rcs COMB /acs COMB COMB /rec COMB /iocs0 COMB /iocs1 COMB COMB /RWO COMB COMB COMB ;PIN lefck COMB COMB 42.37 fA[18.13] COMB /fcs COMB ;PIN NODE fLAT[5.0] NODE COMB EQUATIONS AN1753 MOTOROLA More Information This Product, www.freescale.com
Freescale Semiconductor, Inc. Application Note
RWO.TRST WR.TRST D[5.0] (/A[15] /A[14] /A[13] /A[12] /A[11] /A[10] A[9] fLAT[5.0] (/A[15] /A[14] /A[13] /A[12] /A[11] A[10] /A[9] rA[18.13] (/A[15] /A[14] /A[13] /A[12] /A[11] /A[10] A[9]) (/A[15] /A[14] /A[13] /A[12] /A[11] A[10] /A[9]) D[5.0].TRST
Freescale Semiconductor, Inc.
fLAT[5.0] D[5.0] fLAT[5.0].CLKF lefck /A[15] /A[14] /A[13] /A[12] /A[11] /A[10] A[9] lef.TRST fA[18.15] A[15] fLAT[5.2] fA[14] (A[14] A[15]) (/A[15] fLAT[1]) fA[13] (A[13] A[15]) (/A[15] fLAT[0]) fA[18.13].TRST A[15] /A[15] /A[14] A[13] fcs.TRST rA[18.13] D[5.0] rA[18.13].CLKF /A[15] /A[14] /A[13] /A[12] /A[11] A[10] /A[9] rA[18.13].SETF rA[18.13].RSTF rA[18.13].TRST /A[15] A[14] /A[13] rcs.TRST /A[15] A[14] A[13] acs.TRST iocs0 /A[15] /A[14] /A[13] /A[12] A[11] A[10] /A[9] iocs1 /A[15] /A[14] /A[13] /A[12] A[11] A[10] A[9] iocs0.TRST iocs1.TRST /A[15] /A[14] /A[13] /A[12] /A[11] A[10] A[9] /A[15] /A[14] /A[13] /A[12] A[11] /A[10] /A[9]* lea.TRST rec.TRST
AN1753 More Information This Product, www.freescale.com MOTOROLA
Application Note Program Listings
FLASH Algorithm Listing Listing
PROC "68HC11" development trap
Freescale Semiconductor, Inc.
1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463
FFFF
ROMON
FF-FLASH programmer firmware 68HC711E9 Written Joseph Haas Originated Feb-05-93 Revision MEZ-11 Retrofit Jun-30-95 ;**** Revision History **** ;added BANK command allow access multi-megabit device banks. ;u3hilim stores a18.12. references deal ;with a18.16 ;eflas handles multi-megabit devices.technically ;abandoned u3hi u5hi ;added COPON/OFF commands REVISION HISTORY Last release date: Fri, 1995, 16:05 REDbyt gets byte from addr target device D742 D742 D743 D745 D748 D74A D74B REDbyt 8D07 BDD81D E600 PSHX bytSET addr adrFLA LDAB EPROM PULX bytSET sets bank addr bits current device bytSET D639 C160 260C 9C17 2302 LDAB CMPB bytSU4CPX byter DEVwin #U4win bytSU HiLim+1 hilim address limit test yes, address check devtyp
D74C D74C D74E D750 D752
1464 D754 1465 D756 1466 D757 1467
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Freescale Semiconductor, Inc. Application Note
1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 D758 D75A D75C D75D D75E D75E D75F D761 D763 D764 D766 D767 D768 D769 D76A D76B D76D D76F D770 D772 D775 D776 D777 D778 D779 D77A D77B D77C D77D D77E D780 D782 D784 D785 D787 D78A D78B D78C D78D C120 2716 84E0 D62F C4F8 972F B70400 8407 D62F C438 972F B70200 9C14 25FA LoLim+1 byter flash? yes,
bytSU PSHX CMPB XGDX ANDA LSRA LSRA LSRA LSRA LSRA LDAB ANDB STAA STAA XGDX PULX
SPBNK bits unused entry #U3win #%11100000 yes, MEZ-11 BANKS -mask addrs
Freescale Semiconductor, Inc.
FBANK #%11111000 FBANK rbank
XGDX MEZ-11 BANKS -ROLA ROLA ROLA ROLA ANDA #%00000111 mask addrs LDAB FBANK ANDB #%00111000 STAA FBANK STAA fbank XGDX PULX ;PGMbyt programs, verifies byte device addr PSHX adrFLA #flaPV
D78E D78F D792 D794 D796
BDD81D C6C0 E700 183C
Verif1 LDAB STAB PSHY
flash verify send data target
AN1753 More Information This Product, www.freescale.com MOTOROLA
Application Note Program Listings
1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568
D798 D79A D79B D79C D79D D79E D7A0 D7A1 D7A2
1838 E600
PULY LDAB PULX
~=5+6+(2*4)=17 8.5uS data compare device orig
Freescale Semiconductor, Inc.
D7A3 D7A4 12288004 D7A8 81FF D7AA 272A D7AC D7AD D7AD 8D9D D7AF 2408 D7B1 142720 D7B4 BDD9F3 D7B7 201C D7B9 D7B9 C619 D7BB D721 D7BD D639 D7BF C120 D7C1 2704 D7C3 C601 D7C5 D721 D7C7 8D10 D7C9 D7CA 2709 D7CC 7A0021 D7CF 26F6 D7D1 D7D1 D7D2 D7D3 D7D4 D7D5 D7D5 D7D5 D7D5 D7D6 D7D7 D7D8
PGMbyt BRSET CMPA PSHB BOOTOF BSET
FLAG2,FFSKIQ,:66 skip allowed #$FF skip? FFskip yes, turn bootrom test addr address error flash error
bytSET PGMER,DAE FLASHon PGMqq
STAA LDAB STAB LDAB CMPB LDAB STAB PGMerr PULB
TMP2 DEVwin #U3win TMP2 Prog1 TMP2 BOOTON
write byte cycle count yes, others cycle prog pulse verify byte next cycle done, turn bootrom
byte
PGMqq BOOTON PULB FFskipCLC turn bootrom exit
AN1753 MOTOROLA More Information This Product, www.freescale.com
Freescale Semiconductor, Inc. Application Note
1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 Prog1 writes current device D7D9 D7DC D7DE D7E0 D7E2 D7E4 D7E5 D7E7 140020 D639 C120 2603 8D11 8D01 Prog1 BSET ProgX LDAB CMPB FLAG,ms1 DEVwin #U3win wrFLA
Freescale Semiconductor, Inc.
wrRAM U4/5 wr?? collection routines that handle programming operations supported devices. devices that subscribe multi pulse programming will return single write devices (ie., rams) return read pgm'd byte (for verify). A=data, X=addr save addr write address send data target clear
D7E8 D7E9 D7EB D7ED D7EF D7F1 D7F3 D7F4
8D32 A700 D600 D647 E600
wrRAM PSHX STAA LDAB LDAB LDAB PULX
adrFLA
read data verify restore addr
D7F5 D7F6 D7F8 D7FA D7FC D7FD D7FF D801 D802 D804 D806 D808 D80A D80C D80D D80E D80F D810 D812 D813
8D25 C640 E700 E700 C609 26FD C6C0 E700 183C 1838 E600
wrFLA PSHX LDAB STAB STAB LDAB DECB LDAB STAB PSHY PULY LDAB PULX
adrFLA #flaPG #flaPV
save addr write address flash send data target
send data target delay 12us
flash verify send data target
~=5+6+(2*4)=17 8.5uS data restore addr
AN1753 More Information This Product, www.freescale.com MOTOROLA
Application Note Program Listings
Freescale Semiconductor, Inc.
1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642
D814 D815 D817 D819 D81B D81C
8D06 C600 E700
FLwrRM PSHX adrFLA phys address LDAB #flaRM read mode STAB send data target PULX adrFLA moves addr window selected device: $2000-3FFF %00100000 U3win $6000-7FFF %01100000 U4win $4000-5FFF %01000000 U5win files that program these devices must start $0000 proceed $FFFF. adrFLA PSHA XGDX ANDA ORAA XGDX PULA
D81D D81E D81F D821 D823 D824 D825
841F 9A39
#%00011111 DEVwin
mask addrs combine window mask back
AN1753 MOTOROLA More Information This Product, www.freescale.com
Freescale Semiconductor, Inc. Application Note References
Motorola's HC05/08 Website:
Freescale Semiconductor, Inc.
AN1753 More Information This Product, www.freescale.com MOTOROLA
Application Note References
Freescale Semiconductor, Inc.
AN1753 MOTOROLA More Information This Product, www.freescale.com
Freescale Semiconductor, Inc. Application Note
Freescale Semiconductor, Inc.
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
reach USA/EUROPE/Locations Listed: Motorola Literature Distribution, P.O. 5405, Denver, Colorado 80217, 1-800-441-2447 1-303-675-2140. Customer Focus Center, 1-800-521-6274 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 03-5487-8488 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd., Ping Industrial Park, Ting Road, N.T., Hong Kong. 852-26629298 MfaxTM, Motorola Back System: RMFAX0@email.sps.mot.com; http://sps.motorola.com/mfax/; TOUCHTONE, 1-602-244-6609; Canada ONLY, 1-800-774-1848 HOME PAGE: http://motorola.com/sps/
Mfax trademark Motorola, Inc. Motorola, Inc., 1998
AN1753/D More Information This Product, www.freescale.com

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