Enhanced Memory Systems SM3603 SM3604 HighSpeed SDRAM (HSDRAM) devices

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Enhanced Memory Systems SM3603 SM3604 HighSpeed SDRAM (HSDRAM) devices

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64Mbit High Speed SDRAM (150 MHz) 8Mx8, 4Mx16 HSDRAM Description
Enhanced Memory Systems SM3603 SM3604 HighSpeed SDRAM (HSDRAM) devices high performance versions proposed JEDEC PC-133 SDRAM. While compatible with standard SDRAM, they provide faster clock access time (4.5 ns), shorter random access latency (31.2 ns), fast bank cycle time (53.3 needed improve system stability, capacity, performance systems operating speed. HSDRAM ideal high performance system including PCs, workstations, servers, communications switches, systems, graphics, embedded computers.
JEDEC Standard PC-133 SDRAM Fast Clock Access Time Latency Operation (3:2:2 MHz) Latency Delay Precharge Delay Fast Random Access Time (31.2 Fast Random Cycle time (53.3 Programmable Burst length full page) Programmable Latency Power suspend, Self Refresh, Power Down Modes Supported Refresh Single 3.3V 0.3V Power Supply 54-pin TSOP-II (0.8mm pitch)
Block Diagram (4Mx16 shown)
ADDRESS BUFFERS
DECODER
A(11:0)
BANK rows bits
BANK rows bits
BANK rows bits
BANK rows bits
SENSE AMPLIFIERS COLUMN DECODER
SENSE AMPLIFIERS COLUMN DECODER
SENSE AMPLIFIERS COLUMN DECODER
SENSE AMPLIFIERS COLUMN DECODER
Data Buffers
/RAS /CAS UDQM, LDQM
DQ(15:0)
COMMAND DECODER TIMING GENERATOR
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
1999 Enhanced Memory Systems. rights reserved. information contained herein subject change without notice.
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64Mbit High Speed SDRAM (150 MHz) 8Mx8, 4Mx16 HSDRAM Assignments (Top View)
8Mx8 4Mx16
/CAS /RAS LDQM /CAS /RAS DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
TSOP-II mils pitch
UDQM
A10/AP A10/AP
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
1999 Enhanced Memory Systems. rights reserved. information contained herein subject change without notice.
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64Mbit High Speed SDRAM (150 MHz) 8Mx8, 4Mx16 HSDRAM
Descriptions
Symbol Type Input Input Function Clocks: SDRAM input signals sampled positive edge CLK. Clock Enable: activate (high) deactivate (low) signals. Deactivating clock initiates Power-Down Self-Refresh operations (all banks idle), Clock Suspend operation. synchronous until device enters Power-Down SelfRefresh modes where asynchronous until mode exited. Chip Select: enables (low) disables (high) command decoder. When command decoder disabled, commands ignored previous operations continue. Command Inputs: Sampled rising edge CLK, these inputs define command executed. Bank Addresses: These inputs define which banks given command being applied. Address Inputs: A0-A11 define address during Bank Activate command. A0A8 define column address during Read Write commands. A10/AP invokes Auto-precharge operation. During manual Precharge commands, A10/AP specifies single bank precharge while A10/AP high precharges banks. address inputs also used program Mode Register. Data I/O: Data inputs outputs. Write cycles, input data applied these pins must set-up held relative rising edge clock. Read cycles, device drives output data these pins after latency satisfied. Data Mask Inputs: inputs mask write data (zero latency) acts synchronous output enable (2-cycle latency) read data. Power Supply: +3.3 Ground connect open pin.
Input
RAS#, CAS#, BA1, (A12, A13) A0-A11
Input Input Input
DQ0-DQ15
Input/ Output
DQM, UDQM, LDQM
Input
Supply Supply
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
1999 Enhanced Memory Systems. rights reserved. information contained herein subject change without notice.
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64Mbit High Speed SDRAM (150 MHz) 8Mx8, 4Mx16 HSDRAM Electrical Characteristics
Absolute Maximum Ratings Description Power Supply Voltage Voltage with Respect Ground Operating Temperature (ambient) Storage Temperature Power Dissipation Output Current (I/O pins) Symbol VIN, VOUT Tstg IOUT
Value +4.6V -0.5V +4.6V +70°C -55°C +125°C 50mA
Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only, functional operation device these, other conditions above those listed operational section specification, implied. Exposure conditions absolute maximum ratings extended periods affect device reliability.
Operating Conditions 70°C) Symbol II(L) IO(L) Supply Voltage Input High Voltage Input Voltage Input Leakage Current Output Leakage Current Output High Voltage (IOUT -4mA) Output Voltage (IOUT +4mA) Parameter -0.3 Typical Units Notes
Capacitance 25°C, 1MHz, 3.3V ±0.3V, 100% tested) Symbol CIn1 CIn2 CI/O Parameter Input Capacitance (BA1, BA0, A0-11) Input Capacitance (all control inputs) Capacitance (DQ0-15) Typical Units Notes
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
1999 Enhanced Memory Systems. rights reserved. information contained herein subject change without notice.
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64Mbit High Speed SDRAM (150 MHz) 8Mx8, 4Mx16 HSDRAM
Characteristics 70°C)
initial pause 200µs required after power-up, then Precharge Banks command must given followed minimum eight Auto (CBR) Refresh cycles before Mode Register operation begin. timing tests have 0.8V 2.0V with timing referenced 1.4V crossover point.
Clock tSETUP Input Output
Output CLOAD 30pF
tHOLD
Output Load Circuit
transition time measured between between VIL). measurements assume 1ns. addition meeting transition rate specification, clock must transition between VIL) monotonic manner.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
1999 Enhanced Memory Systems. rights reserved. information contained herein subject change without notice.
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64Mbit High Speed SDRAM (150 MHz) 8Mx8, 4Mx16 HSDRAM Operating Conditions 70°C)
Symbol Parameter Clock Clock Enable Parameters tCK3 tCK2 tCKH3, tCKL3 tCKH2, tCKL2 tCKES tCKEH tCKSP Clock Cycle Time, Clock Cycle Time, Clock High Times, CL=3 Clock High Times, CL=2 Clock Enable Set-Up Time Clock Enable Hold Time Set-Up Time (Power down mode) Transition Time (Rise Fall) -6.6
Units
Notes
Common Parameters tRCD tRAS tRRD tCCD tMRD
Notes: Assumes clock rise fall times equal 1ns. rise fall time exceeds 1ns, other timing parameters must compensated additional [(trise+tfall)/2-1]
Command Address Set-Up Time Command Address Hold Time Delay Time Bank Cycle Time Bank Active Time Precharge Time Bank Bank Delay Time (Alt. Bank) Delay Time (Same Bank) Mode Register Active Delay
13.2 52.5 13.2
120K 120K
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
1999 Enhanced Memory Systems. rights reserved. information contained herein subject change without notice.
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64Mbit High Speed SDRAM (150 MHz) 8Mx8, 4Mx16 HSDRAM
Symbol
Parameter
-6.6
Units
Notes
Read Write Parameters tAC3 tAC2 tOH3 tOH2 tHZ2 tDQZ tDPL tDAL tDQW Clock Access Time, Clock Access Time, Data Output Hold Time (CL=3) Data Output Hold Time (CL=2) Data Output Low-Z Time Data Output High-Z Time (CL=2, Data Output Disable Time Data Input Set-Up Time Data Input Hold Time Data Input Precharge Data Input ACTV/Refresh Data Write Mask Latency
Refresh Parameters tREF tSREX
Notes: Access time measured 1.4V (LVTTL) clock rate latency specified. Test Load. Access time based clock rise time 1ns. clock rise time longer than 1ns, then (trise/2-0.5) must added access time. Referenced time which output achieves open circuit condition. tDAL equal tDPL tRP. 4096 cycles. time that refresh period been exceeded, minimum Auto-Refresh (CBR) commands must given "wake device. completed until satisfied once Self-Refresh Exit command registered.
Refresh Period Self Refresh Exit Time
2CLK+tRC
Self-Refresh exit synchronous operation begins positive clock edge after returns high. Self-Refresh Exit
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
1999 Enhanced Memory Systems. rights reserved. information contained herein subject change without notice.
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64Mbit High Speed SDRAM (150 MHz) 8Mx8, 4Mx16 HSDRAM Operating Currents 70°C)
Parameter Operating Current (One Bank Active) Standby Current Power Down Mode (DRAM Precharged) Symbol ICC1A ICC2P ICC2PS Standby Current Non-Power Down Mode (DRAM Precharged) Device Deselected (DRAM Active) ICC2N ICC2NS ICC3N ICC3P Burst Operating Current (Both Banks Active) Auto (CBR) Refresh Current Self Refresh Current
Notes:
Test Condition Read Write, VIH(min), min., min. VIL, min., Input Change Every Cycles VIL, Infinity, Input Change VIH, min. VIH, Infinity VIH, min., Input Change Every Cycles VIL, min., Input Change Every Cycles Full Page, 2,3, Read Write, Infinity, min. min., tRC(min). min., 15.625 ,QSXW &KDQJH
Value
Units
Notes
ICC4B ICC5F ICC5D ICC6
3,4,5 3,4,5
specified value obtained with outputs open. specified value obtained when programmed burst length executed completion without interruption subsequent burst read burst write cycle. specified value valid when addresses changed more than once during tCK(min). specified value valid when Operation commands registered every rising clock edge during tRC(min). specified value valid when data inputs (DQs) stable during tRC(min).
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
1999 Enhanced Memory Systems. rights reserved. information contained herein subject change without notice.
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64Mbit High Speed SDRAM (150 MHz) 8Mx8, 4Mx16 HSDRAM
Ordering Information
Maximum Operating Frequency (MHz)
Part Number
Latencies
Width
Type
Package
Power Supply 3.3V 3.3V
SM3603T-6.6 SM3604T-6.6
LVTTL LVTTL
54-pin TSOP 54-pin TSOP
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
1999 Enhanced Memory Systems. rights reserved. information contained herein subject change without notice.
Revision
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Enhanced Memory Systems SM3603 SM3604 HighSpeed SDRAM (HSDRAM) devices

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