FUELING MEGAPROCESSOR DC/DC CONVERTER DESIGN REVIEW FEATURING UC3886 U

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FUELING MEGAPROCESSOR DC/DC CONVERTER DESIGN REVIEW FEATURING UC3886 U

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Larry Spaziani Applications Engineer Unitrode Corporation
FUELING MEGAPROCESSOR DC/DC CONVERTER DESIGN REVIEW FEATURING UC3886 UC3910
UNITRODE CORPORATION
FUELING MEGAPROCESSOR DC/DC CONVERTER DESIGN REVIEW FEATURING UC3886 UC3910
Larry Spaziani Applications Engineer
ABSTRACT
This application note provides detailed account design tradeoffs procedures development Voltage Regulator Module (VRM) Intel Pentium®Pro processor. This voltage regulator features Unitrode's UC3886 Average Current Mode Controller UC3910 4-BIT Voltage Monitor configured Buck Regulator. Test results waveforms provided which show power supply meets stringent requirements imposed Intel.
INTRODUCTION Intel's power system specification demonstrates industry trend operate lower voltages higher currents, with tight regulation fast transient response. Meeting these requirements demands most both power stage control system power supply. Unitrode's UC3886 UC3910 specifically designed optimizing control loop, dynamic response accuracy required Pentium®Pro. power stage inductor capacitors critical well meeting extremely tight voltage regulation during Pentium®Pro load transient. This application note will detail design complete power supply. This design review will detail critical specifications, power supply architecture tradeoffs, power stage design details equations finally design specifics used configure UC3886 UC3910. complete current voltage loops will then closed, performance results power supply will shown. This design review will reveal many advantages using UC3886 UC3910, which include: Pentium®Pro Direct output NMOS drive, eliminating need creating high voltages allowing efficient N-Channel MOSFET. High accuracy negates need voltage trimming insures overall regulation will met. Direct interface with INTEL's PENTIUMPRO programming codes. UC3910's unique voltage monitoring architecture directly replaces discrete components including precision reference, DAC, complicated resistive networks, multiple window comparators Driver. Accurate true "square-knee" current limiting eliminates need over-design power components operation indefinite short circuit. Optimization loop performance large signal changes transient loading effects. Unitrode demonstration shown Figure VRM's schematic shown Figure parts described Table
APPLICATION NOTE
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Figure Unitrode's Demonstration
UDG-96213
Figure Schematic Diagram
APPLICATION NOTE
POWER SUPPLY SPECIFICATIONS requirements DC/DC converter which will provide power Intel Pentium®Pro contained Intel's application note AP-523 [1], Section These power supply requirements consist required specifications, expected specifications design guidelines, some which summarized below. Input Voltages: Output Voltage: 5.00V 12.00V Variable from 2.4V 3.4V programmable INTEL codes, 100mV increments.
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Input Current Rate: ±0.1A/µs maximum during load transient. Power-Good: Open Collector output signal when output voltage within ±10% nominal. Open Collector input signal with state disabling DC/DC converter. 20MHz. above initial setpoint application removal input power. maximum current, minimum current +10°C +60°C, cooling along connector axis. Self shut down when output exceeds nominal. Continuous short circuit modewithout damage overstress unit.
Output Enable:
Ripple/Noise: Overshoot:
Minimum Current: 0.3A Maximum Current: 11.2A Regulation: Including initial tolerance, setpoints, drift, transients ripple/noise. Minimum maximum maximum minimum current rate 30.3A/µs.
Efficiency: Temperature: Over Voltage:
Load Transient:
Short Circuit:
TABLE PENTIUM®PRO DEMONSTRATION BILL MATERIALS
UNITRODE PENTIUM®PRO DEMONSTRATION
REF.DES. DESCRIPTION Unitrode UC3910DP 4-BIT Voltage Monitor Unitrode UC3886DP Controller Unitrode UC3612DP Dual Schottky Diode 0.10µF Ceramic 0.10µF Ceramic Sanyo 6MV1500GX, 1500µF, 6.3V, Aluminum Electrolytic Sanyo 6MV1500GX, 1500µF, 6.3V, Aluminum Electrolytic Sanyo 6MV1500GX, 1500µF, 6.3V, Aluminum Electrolytic Sanyo 6MV1500GX, 1500µF, 6.3V, Aluminum Electrolytic Sanyo 6MV1500GX, 1500µF, 6.3V, Aluminum Electrolytic Sanyo 6MV1500GX, 1500µF, 6.3V, Aluminum Electrolytic Sanyo 6MV1500GX, 1500µF, 6.3V, Aluminum Electrolytic Sprague/Vishay 595D475X0016A2B, 4.7µF Tantalum 0.10µF Ceramic 0.10µF Ceramic 0.10µF Ceramic 0.10µF Ceramic 2700pF Ceramic 1200pF Ceramic 1000pF Ceramic 0.01µF Ceramic 0.10µF Ceramic 100pF Ceramic 0.022uF Ceramic 0.10µF Ceramic 0.10µF Ceramic PACKAGE SOIC-16 SOIC-16 SOIC-8 1206 1206 10x20mm Radial 10x20mm Radial 10x20mm Radial 10x20mm Radial 10x20mm Radial 10x20mm Radial 10x20mm Radial SPRAGUE Size 1206 1206 1206 1206 0603 0603 0603 0603 1206 0603 0603 1206 1206 NOTES
APPLICATION NOTE
TABLE PENTIUM®PRO DEMONSTRATION BILL MATERIALS (cont.) REF.DES. DESCRIPTION PACKAGE 180pF Ceramic 0603 220pF Ceramic 0603 USED 0603 SMD1 180pF Ceramic 0603 1000pF Ceramic 0805 Sprague/Vishay 593D107X9010D2, 100µF, 6.3V Tantalum Size SCR1 Motorola MCR12D, TO-220AB International Rectifier 32CTQ030 30V, Schottky Diode TO-220AB CR1-HS AAVID 577002 TO-220 Heat Sink 1N5401CT, 100V Diode DO-201AD Littlefuse R451010, Fast Blow Square 532956-7 Connector Coilcraft S6030-B, 10µH 20µH Radial Toroid International Rectifier IRL3103, 30V, TO-220AB Q1-HS AAVID 577202 TO-220 Heat Sink Dale/Vishay WSR-2 0.01W Power Package 1.00kW, 1/16 Watt 0603 6.8kW, 1/16 Watt 0603 10W, 1/16 Watt 0603 27W, 1/16 Watt 0603 100W, 1/16 Watt 0603 USED 0603 1.69kW, 1/16 Watt 0603 1.37kW, 1/16 Watt 0603 54.9kW, 1/16 Watt 0603 24W, 1/16 Watt 0603 10W, 1/16 Watt 0603 10kW, 1/16 Watt 0603 15.0kW, 1/16 Watt 0603 3.92kW, 1/16 Watt 0603 100kW, 1/16 Watt 0603 487kW, 1/16 Watt 0603 4.22kW, 1/16 Watt 0603 4.22kW, 1/16 Watt 0603 33.2kW, 1/16 Watt 0603 33.2kW, 1/16 Watt 0603 USED 0603 1.24kW, 1/16 Watt 0603 10.5kW, 1/16 Watt 0603 USED 0603 27W, 1/16 Watt 0603 10W, 1/16 Watt 0603
Notes:
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NOTES
required. These parts used alternative compensation schemes. These parts related overvoltage protection firing circuit. Simulate wire" connection using etch best results. used debug purposes. required production unit. used pull PWRGOOD signal internally required proper operation. used "jumper". used debug purposes. used alternative compensation, shorted production unit. required production unless synchronization used.
APPLICATION NOTE
POWER CONVERSION ARCHITECTURE Topology: Single Switch Buck Regulator Power conversion from either volts volts lower voltages required Pentium®Pro accomplished either linear regulator myriad switching converter topologies. Linear regulation appropriate because inherently poor efficiency. Transformer coupled switching topologies required, desired, because common input output grounding system. Either single switch synchronous rectifier (two switch) buck regulator most appropriate choices this application. Higher efficiency achieved with synchronous rectification, required this application because efficiency goal 80%. added cost complexity second N-MOSFET therefore justified. Input Voltage: Volts Provides Power, Volts provides Bias Drive Either volt volt power used this single switch Buck regulator. Nchannel MOSFET chosen switch because efficiency RDSon N-MOSFETs. volt used drive N-MOSFET input Buck regulator, whereas +12V input Buck regulator would require higher voltage (17-20 volts) provide drive switch. Several other considerations made choosing input voltage, including: +12V input would require larger output inductor given ripple current. input operates higher duty cycles, reducing power freewheeling diode, whereas +12V input operates lower duty cycles, reducing power MOSFET. combined power dissipated freewheeling diode plus MOSFET less with input than with +12V input. typically better power distribution motherboard, within system, even considering higher currents involved when converting power from +5V. input capacitors will same switching current either voltage. dedicated input pins whereas +12V only two. Using input voltage will result fewer amps/pin lower impedance path source. +12V busses often withstand larger voltage deviations loading effects Pentium®Pro. Control Method Average Current Mode Control Using UC3886
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Average Current Mode control, implemented with UC3886, offers advantages optimization control loop, very fast amplifiers fast transient response, accurate current limiting. Application Note U-140 discusses many advantages Average Current Mode control over both Peak Current Mode control Voltage Mode control. Switching Frequency 200kHz Several considerations choosing 200kHz switching frequency are: upper bound frequency derived from gain required UC3886 Average Current Mode control current sense amplifier. This upper bound will shown 312kHz. high switching frequency desired Minimum output inductor size Maximum control loop bandwidth switching frequency desired Keeping switching losses low, although switching losses semiconductors significant factor this application because input voltage (+5V) very low. Reducing noise when using 2-layer printed circuit board. Aluminum Electrolytic capacitors favored both input output capacitors this application because height allowed, their high Capacitance-to-ESR Capacitance-to-ESL ratios their ripple current capabilities. Surveying several suppliers Aluminum Electrolytic capacitors revealed that they have significantly impedance optimal ripple current handling 100kHz 200kHz, where minimal. POWER STAGE COMPONENT SELECTION power stage components consist input output capacitors, switch, freewheeling diode, output inductor sense resistor, chosen leaded devices most part because height allowed this design. semiconductors first chosen meet full load efficiency goal provide reliable operation full load. output inductor then chosen provide output current ripple into capacitors continuous mode operation
APPLICATION NOTE
Buck regulator. output capacitors chosen provide extremely output impedance voltage ripple voltage droop during output load transient. Finally, input capacitors chosen handle high level ripple current demanded Buck regulator heavily filter input voltage from both high load transients. Efficiency/Power Dissipation Budget desired efficiency goal full load operation will govern many power stage components selected. Efficiency goals nominal input voltage +5.00V, output voltage 3.1V, +25°C ambient temperature maximum load current 11.2A. nominal output power power supply equal 3.1V 11.2A 34.72 Watts. From desired efficiency, input power full load 34.72W 43.4 Watts power dissipated 8.68 Watts, full load. example efficiency budget shown Table Power Stage Component Design Details given
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0.0V (RSENSE RLOUT) (ISC RDSon)
0.01 0.012 25°C, full load current 0.35V full load, 0.25 minimum load 12.5A Nominal Short Circuit Current 5.00V Nominal RDSon 0.025 110°C 3.10V Nominal Then typical duty cycles will approximately: Operating: Full load, 25°C minimum load, 25°C Short Circuit: maximum operating power dissipation diode's maximum operating junction temperature 110°C given Given RSENSE RLOUT PDmax IOmax Dmax) 0.35V 11.2A 0.73) 1.06W power dissipation under short circuit conditions, however, substantially larger PDsc Dsc) 0.35V 1.12A 0.73) 1.06W TJmax 115°C under operating conditions 150°C under short circuit conditions (Rated TJmax device) governing formulas defining heat sink requirements (thermal impedance RHS) 115°C 50°C 1.06W (3.0 RHS), 58°C/W 150°C 50°C +3.80W (3.0 RHS), 23.3°C/W short circuit operation must used choose heat sink. AAVID 577002 with 100LFM airflow meets heat sink requirement 23°C/W. Note that accurate current limit
Power Dissipated 1.25 3.03 Budget Remaining 8.68 7.58 6.48 5.23 3.93 3.83 3.33 3.03 0.00
Freewheeling Diode:
International Rectifier 32CTQ030 equivalent, legs paralleled 0.35V 115°C TJmax 150°C Heat Sink AAVID 577002 equivalent voltage schottky technology chosen maximize efficiency power supply, based lower forward voltage lack reverse recovery losses. operating duty cycle this Buck converter derived based equation3 (RSENSE RLOUT) RDSon)
Likewise, short circuit operating duty cycle
TABLE POWER DISSIPATION BUDGET
Description Budgeted Power Estimated Power Distribution (I2R) Losses Diode Losses Sense Resistor Output Inductor (I2R) Output Inductor (Core) Input Capacitance Ripple Current Losses UC3886 UC3910 Bias loads MOSFET (Switching, Conduction, Gate Drive)
APPLICATION NOTE
point achieved UC3886 allows minimum heat sink solution. Conduction losses determined PCOND RDSon DMAX
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MOSFET Switch:
International Rectifier IRL3103 RDSon 0.025 Estimated 115°C (Total Gate Charge) 50nC estimated Heat Sink AAVID 577202 equivalent From power budget, MOSFET should chosen achieve desired losses, including gate drive losses. Choosing Logic Level MOSFET standard threshold voltage MOSFET discussed U-156 [3]. This application will utilize Generation MOSFET from International Rectifier because combination RDSon well rated ±20V. power dissipation MOSFET consists components; Gate drive, COSS, Crossover losses, Conduction losses Gate Drive losses given PGATE IGATEavg From IRL3103 charge curve, with volts, required total charge, estimated 50nC. average current given IGATEavg 50nC 200kHz 10mA PGATE 0.010 Amps Volts 0.12 Watts Coss losses discharge energy stored capacitance Coss each cycle, equivalent PCOSS Coss (VIN VF)2 From IRL3103 capacitance curve, Coss estimated 2400pF. Therefore, PCOSS 2400pF (5.35V)2 200kHz 0.007W. Crossover (turn-on turn-off) losses estimated (VIN RISE/FALL where TRISE/FALL MOSFET current rise fall time, estimated approximately 150ns, switching period. This loss occurs once turn-on, once turn-off, therefore, this application 150ns PCROSSOVER 5.35V 11.2A Watts PCROSSOVER
worst maximum operating junction temperature, where RDSon highest. IRL3103, this loss PCOND 11.22 0.025 0.73 2.29 Watts Pd_Total_FET 2.29W 0.6W 0.007W 0.12W 3.02W MOSFET heat sink requirements determined from 115°C 50°C 3.02W (2.0 RHS), 19.5°C/W AAVID 577202 with 100LFM airflow provides 14°C/W, exceeding heat sink requirement.
Output Inductor:
Coilcraft S6030-B 20µH 10µH @11.2 Turns, 16AWG Micrometals T60-52D Core 0.008 max, 20°C Ambient TRISE 40°C maximum load output inductor Buck regulator often chosen maintain continuous current inductor under minimum load conditions. ripple current inductor under minimum current conditions equal IMIN this rule apply. this power supply, LOUT determined LOUT= (VIN VOUT) Duty 3.1V) 0.64 IMIN 0.3A 200kHz
10.1µH Load second condition choosing output inductor value limit input current power supply during step change current from IMIN IMAX. After step change load current, duty cycle Buck regulator responds assuming maximum duty cycle 100%. input current therefore equals output inductor current. limit input current rate required 0.1A/µs, output inductor chosen LOUT (VIN VOUT) 3.1V) 19µH di/dt 0.1A/µs
toroidal inductor design used meet these needs. form factor allows component height 0.800", thus allowing sizable inductor that designed cost simple winding techniques. inductance current shown Figure inductor must saturate with
APPLICATION NOTE
current equal power supply short circuit current limit, current limiting will effective.
Inductance (µH) Current
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Choosing output capacitors this regulator single most important decision with regards meeting transient load behavior Pentium®Pro. transient load step Pentium®Pro large fast that there control loop which respond quickly enough maintain regulation. Capacitance, providing impedance output, therefore best solution maintaining proper output voltage. Understanding Response Step Load During step load change from minimum maximum current, output power supply modeled shown Figure Prior change load current, average current output inductor IMIN average current output capacitor amperes. Once load current changes from Imin IMAX, parasitic components shown Figure have large affect output voltage.
Figure Output Inductor Performance Current Flux
in-circuit inductance will tend higher Flux imposed volt-seconds product Buck regulator. Micrometals material's permeability increases substantially with Flux. This same effect Flux permeability material plays major role during transient load response power supply. During transient load response, voltage differential across output inductor approximately VIN-VOUT. duration transient response, excess 100µs, means that Flux core this time given
(VIN VOUT) TLOUT
UDG-96214
3.1V) 100µs 13Turns 0.374 3908 Gauss which, according Micrometals results multiplying output capacitance approximately 260%. This results dynamic inductance, during load step, approximately 26µH. This feature will play important role selection output capacitors meet transient load performance.
Figure Large Signal Transient Model Power Supply Output Stage
connector pins have parasitic resistance inductance termed RCONN LCONN. parasitic inductance connector output capacitors (ESL) summed together RCONN cannot combined capacitor path this would result load regulation error. Figure below illustrates complexity output voltage waveform during step output load current. power supply with excellent load regulation assumed purposes understanding these dynamics. Reducing load regulation through non-integrating voltage loop gain will discussed later this application note. output voltage responds load current step four distinct phases, TSTEP, TLOOP, TLOUT TCHARGE.
Output Capacitors: C06-C09, C11, C12,
SANYO 6MV1500GX Parallel 1500µF Form Factor 10x20mm, Radial 0.044 (Estimated) Ripple Current Rating 1.25A 105°C, 100kHz
APPLICATION NOTE
Phase determined V_Phase1 COUT
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STEP STEP
STEP STEP COUT response output voltage during time therefore given VOUT STEP STEP i(t)dt COUT COUT
ISTEP ISTEP
TSTEP LOOP COUT COUT
TLOOP, UC3886 Average Current Mode Controller compensation components shown Figure less than switching cycle.
UDG-96215
Figure Dynamics Step Load
Phase step current phase from (TSTEP), characterized specified change current rise time. response output voltage consists voltage step proportional parasitic circuit inductance, ramp voltage proportional parasitic circuit resistance, where RCONN ESR. droop voltage proportional power supply output capacitance. response output voltage during time therefore given VOUT i(t) i(t)dt COUT which, TSTEP, equal VOUT ISTEP
Phase from (TLOUT), time when control loop forced Buck regulator maximum duty cycle (100% UC3886) inductor current ramping from IMIN IMAX. output inductor current during this phase given iLOUT(t) (VIN VOUT) LOUT
Since inductor current ramping during Phase capacitor current ramping down, given iCOUT(t) ISTEP ILOUT(t) ISTEP (VIN VOUT) LOUT
change output voltage during Phase consists voltage drop proportional RCONN. droop voltage proportional output capacitance. During Phase voltage drop capacitance changing because capacitor current decreases. voltage drop RCONN constant, constant value RCONN maximum load current, ISTEP. There initial discharge capacitor Phase which initial condition Phase determined V_Phase2
TSTEP
TSTEP COUT
Phase from (TLOOP), time where load current settled maximum value, IMAX, power supply loop responded. inductor current therefore still IMIN response output voltage therefore determined voltage proportional droop voltage proportional power supply output capacitance. There initial discharge capacitor Phase which initial condition
STEP
Cout Istep
STEP STEP LOOP STEP
APPLICATION NOTE
change output voltage during Phase given VOUT STEP
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Inductance mated 4.28nH Number output pins pairs parallel Resistance printed circuit board connector 0.2m Inductance printed circuit board connector 0.2nH RCONN 0.2m 2.02m LCONN 4.28nH 0.2nH 0.59nH
TLOOP TSTEP COUT
COUT
OUT(t)dt iCOUT(t)
ISTEP RCONN Which yields VOUT
ISTEP COUT
STEP TLOOP TLOUT
Step Establish allowable maximum voltage drop, VOUT, output. Application Note U-156 discusses non-integrating gain which allows larger voltage deviation during load transient. minimum load regulation VNOM ±1%. Therefore, voltage deviation allowed output voltage while still meeting minimum overall voltage -5%. Voltage ripple considered during this transient response duty cycle effectively 100%, there voltage ripple. These limits illustrated Figure
ISTEP
TLOUT CONN
TLOUT defined time takes inductor current equal change load current, ISTEP. ISTEP LOUT TLOUT (VIN VOUT)
Phase TCHARGE, time when inductor current overshoots reach programmed short circuit current limit order replace charge lost output capacitor. phase output voltage drop settles VOUT ISTEP RCONN duration phase determined
Regulation
5.0% 4.0% 3.0% 2.0% 1.0% 0.0% -1.0% -2.0% -3.0% -4.0%
Allowable Voltage Transient
Regulation Window IMIN
Regulation Load Non-integrating Gain
ICout COUT TCHARGE
which yields time
COUT V_Phase3 (ISC IMAX)
where programmed short circuit current limit, V_Phase3 voltage phase determined TLOUT TSTEP V_Phase3 STEP TLOOP COUT Procedure Determining Required Output Capacitor(s) Step Determine parasitic values RCONN LCONN. following estimates based connector pair used printed circuit board. Resistance Resistance mated
-5.0%
IMIN
100%
IOUT IMAX
Figure Setting Regulation Voltage Transient Requirements
VOUT 0.07 3.1V 0.217 volts Step Estimate total parasitic inductance, order derive required value from voltage step Phase Aluminum electrolytic capacitors, size 10mm 20mm, estimated have approximately 4.0nH. Size 1206 ceramic chip capacitors estimated
APPLICATION NOTE
have approximately 1.9nH [1]. Assume that combined will less than 0.51nH, total parasitic inductance 1.10nH This value must insured maintain overall regulation limits during first phase, TSTEP. Step Equate voltage deviation Phase allowed voltage step. Assume that change voltage capacitive discharge less than overall change. Therefore, minimum value COUT equal 10.9A 360ns 904µF COUTmin 0.217V 0.01 Solving maximum value step 11.2A 0.3A 10.9A yields, (0.217V 0.99) 10.9A 1.1nH 360ns 10.9A
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minum electrolytic capacitors chosen based their lower specifications. Required 16.6m 13.3m Sanyo MV-GX 1500µF, 10mm 20mm, 6.3V device rated maximum 44m. devices required, using 400mm2 board area. Sanyo MV-GX 1000µF, 20mm, 6.3V device rated maximum 64m. devices required, using 384mm2 board area. 1500µF device chosen reduce total parts count. solution COUT 1500µF 6000µF 11.0m 1.0nH Step Determine voltage waveform output given this solution output capacitors. current capacitor, during transient, ramps down) time determined output inductor. output inductor, during transient load step, approximately 26µH. ISTEP TLOUT LOUT (VIN VOUT)
=16.6m Step Equate voltage deviation Phase allowed voltage step, from which minimum value COUT obtained 0.217V
10.9A 26µH 149µs (5.0V 3.1V)
10.9A 5.0µs 360ns
OUTmin
capacitor current defined iCOUTt ISTEP STEP TLOUT voltage drop output power supply, during Phase (TLOUT) load transition, determined VOUT STEP COUT
(13.8m 10.9A) 10.9A (2.5µs 360ns)ww COUTmin 0.217V (16.6m 10.9A) =1457µF Step Choose capacitor type, manufacturer(s) values. Determine number capacitors required meet requirements from Step minimum capacitance requirements from Step margin variations from 20°C down 10°C (minimum operating temperature). Radial, high frequency aluminum electrolytic capacitors chosen based height allowed this power supply well their inherently ESL. Many manufacturers offer 6.3V devices rated 100kHz 200kHz operation. Sanyo's MV-GX series alu-
(ESR-
STEP LOOP LOUT LOUT CONN
STEP
entire voltage response plotted Figure Ceramic tantalum capacitors (C11, C12, C29) added parallel aluminum output capacitors reduce overall less than required
APPLICATION NOTE
-0.10 VOUT Capacitor -0.12 -0.14 -0.16 -193mV -0.18 -175mV -0.20 Time
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UDG-96216
Figure Voltage Droop Power Supply Output during Load Transient
Figure Input Capacitor(s) Current Waveform
0.51nH reduce high frequency noise meet ripple requirement peak-to-peak.
lAVG
lOmax VOUT PINPUTmax VINPUT Efficiency VINPUT 11.2A 3.1V 8.68A 0.80 5.0V
Input Capacitors: C01-C05
SANYO 6MV1500GX Parallel 1500µF Form Factor 20mm, Radial 0.044 (Estimated) Ripple Current Rating 1.25A 105°C, 100kHz input capacitance Buck regulator chosen based several criteria: Ripple Current Handling FSWITCH Ripple voltage FSWITCH Maintaining Input voltage during load transients resulting solution must present very impedance input supply Buck Regulator, resulting need ESR, large value capacitors. Ripple Current Voltage input capacitors chosen primarily based their switching frequency current handling capability. With just 10's nanohenries parasitic input inductance input capacitors must handle virtually 200kHz switching current. Figure shows switching waveforms input capacitor(s). average power supply input current calculated based maximum load power supply efficiency maximum load.
During MOSFET time, input capacitors must provide difference between load current input current. During MOSFET time, capacitor current complete input average current. Therefore, IOmax IAVG 11.2A 8.68A 2.52A IOFF -IAVG -8.68A duty cycle maximum operating current approximately 73%, therefore current capacitors, assuming rectangular waveform since current ramp very small, given IRMS IOFF2 Duty) ION2 Duty ARMS Three Sanyo capacitors chosen maintain reliable operation while operating this current level. Given current waveform Figure input voltage ripple will proportional input capacitance ESR, shown voltage waveform Figure high capacitance will keep ripple voltage low. ceramic capacitors added filter high frequency noise from switching power supply from input power bus. Filtering VINPUT During Load Transients During low-to-high output load transient, duty cycle goes 100% until output inductor current equal load current, output inductor limits di/dt input current. During high-to-low output load transient, however, there output
APPLICATION NOTE
inductor limiting input current rate because input switch opened duty cycle). result bulk power supply will continue source high current into this power supply some time. Figure illustrates difference circuits between low-to-high high-to-low load transient.
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volts VIN) during high-to-low load transient. current capacitor(s) defined iCIN(t) lAVG lIn_Rate 8.68A (0.1A/µs) where IIn_Rate defined rate which input current decays based bulk power supply, assumed here 0.1A/µs, therefore decaying 0.0A 86.8µs. voltage surge input capacitance during this time 86.8µs vCIN(t)
IN(t) (ESRIN iCIN(t))
8.68 -(105 ESR) 8.68
which plotted Figure Sanyo MV-GX type 1500µF, 0.044 Aluminum Electrolytic Capacitors.
10.0 Capacitor Current Current Input Surge Voltage 0.20 0.18 0.16 Surge Voltage 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 Time
UDG-96217
Figure Lout limits input current only low-tohigh output current transient
Figure shows typical current waveforms during high-to-low load transient. output current abruptly stops bulk power supply takes finite time react this change load current, therefore sourcing energy into input capacitors. Intel specifies that this input current must change rate faster than 0.1A/µs. input capacitor(s) chosen limit voltage surge input capacitors less then 0.15
Figure Input Capacitor Current Surge Voltage During High-to-Low Load Transient
Sense Resistor:
Dale WSR-2 0.01 10m, watt wire sense resistor, ±75ppm sense resistor chosen criteria discussed U-156, Appendix [3]. RSENSE 2wire, watt surface mount power product with very inductance. watt rating ambient temperatures 75°C allows derating typical maximum current Amperes [1]. short circuit current, ISC, chosen nominal 12.5 Amperes, more than over maximum current. value UC3886 Current Amplifier's gain, GCSA, bounded GCSA_MIN GCSA_MAX 2.5MHz/200kHz
Output Current
Current
Capacitor Current
Time
Figure Current Waveforms during High-to-Low Output Transient
APPLICATION NOTE
From Volt GCSA RSENSE 12.5A limit implies that Rsense must between 0.0064 0.016. Choose 0.010 lowest standard value. power dissipation RSENSE during normal short circuit conditions Normal: IAVG2 RSENSE 9.92 0.010 0.98 Watt rated Short Circuit: ISC2 RSENSE 12.52 0.010 1.56 Watt rated CONFIGURING UC3910 4-BIT VOLTAGE MONITOR UC3886 AVERAGE CURRENT MODE CONTROLLER With power stage chosen, UC3910 UC3886 ready programmed proper operation. Figure Figure show block diagrams UC3886 UC3910 ICs. Grounding UC3886 signal ground (SGND) well UC3910's ground pins referenced
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output voltage return path best regulation noise immunity. PGND UC3886 referenced input voltage return path, discussed U-156 [4], best gate drive performance. Decoupling High frequency decoupling provided power pins (C14, C18) VREF pins (C13, C17) both ICs. decoupled PGND UC3886 additionally with 0.1µF capacitor (C19) provide impedance gate drive source. UC3886 Oscillator Frequency 200kHz During load transient, very high duty cycle desired. Therefore, maximum duty cycle 99%. From UC3886 Data Sheet: DMAX 2.0V 0.99 4.0mA)
2.0V DMAX) 4.0mA 2.0V ((4.0mA 2.0V] =110pF 1.8V 4.0mA
Choose 100pF (C20) 54.9k (R10)
UDG-95098-1
Figure UC3886 Average Current Mode Control
APPLICATION NOTE
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UDG-95097-3
Figure UC3910 4-BIT Voltage Monitor
Note that internal capacitance UC3886 adds approximately 15pF capacitance. When using capacitor 100pF, substantial frequency shift result. resistor Test Point (R11 TP1) provided allow external synchronization unit from narrow synchronizing pulse [3]. This resistor required unless external synchronization desired. Driving MOSFET Gate from UC3886 Gate Drive Output gate drive resistor (R12) placed close MOSFET gate. resistor limits peak current provides damping MOSFET gate prevent oscillations. power dissipation this resistor approximately 1.0mW based average current 10mA. Figure shows that current path gate drive signal originates from C19, decoupling capacitor located closely UC3886 GATE pin. added from input voltage Power Ground (PGND) decouple high frequency current spike which exits MOSFET from DRAIN must find path back PGND. should located closely possible MOSFET prevent high frequency ringing MOSFET.
UC3612 dual schottky diode, added protect UC3886 from inductive spikes above below ground which occur high gate drive spikes parasitic inductance. External Enable Signal Intel specifies that Pentium®Pro power supply enabled open collector, active high signal, OUTEN. UC3886 CAO/ENBL connected input UC3886 comparator (Figure 12), with other side comparator attached oscillator ramp. oscillator ramp nominally 1.0V 2.8V peak ramp signal. UC3886 gate drive disabled bringing CAO/ENBL signal level below oscillator ramp signal. external OUTEN signal connected UC3886 CAO/ENBL signal through 1.0k resistor, 1.0k resistor recommended provide high impedance buffer between external noise output UC3886 Current Amplifier Output, insure noise does couple into control loop. CAO/ENBL source 400µA. Using 1.0k resistor will result 400mV drop. reasonable open collector output stage will able sink 400µA maintain saturation voltage less than 400mV, keeping level voltage CAO/ENBL less than 800mV.
APPLICATION NOTE
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UDG-96218
Figure Driving with UC3886
External Signal Intel specifies that signal used disable power supply capable supporting upgraded processor, either varying voltage supporting higher load currents. signal also open collector signal, normally high, pulled when Upgrade Processor place. inserting jumper resistor R25, power supply will disabled case upgrade processor. UNITRODE DEMONSTRATION SHIPPED WITHOUT R25. UPGRADE PROCESSORS EXCEED 12.5A CURRENT LIMIT DEMONSTRATION KIT. INSERT 0603 JUMPER RESISTOR DISABLE POWER SUPPLY UPGRADE PROCESSOR APPLICATION CONFIGURING UC3910 VOLTAGE MONITORING PROTECTION FEATURES regulation requirements this power supply ±5%. PWRGD requirement signal voltage regulation failure when output voltage outside range ±10%. UC3910 Undervoltage Overvoltage (UV, thresholds therefore chosen midrange nominally ±7.5%. equations setting Voltage Monitoring thresholds (see U-158 [7]) %VUV RDIV
%Vov RDIV %Vovp RDIV 33.4 %Vov Setting %VUV %VOV ±7.55 yields divider ratio RDIV 0.45. voltage divider between UC3910's DACBUF OVTH/UVTH pin. chosen draw approximately 1.0mA. 1.69k 1.34k, RDIV 0.448 nominal thresholds Overvoltage Threshold Undervoltage Threshold Overvoltage Protection Threshold PWRGD Signal: Intel requires PWRGD signal open collector active HIGH signal when voltage within specification. 4.7k resistor which added internally demonstration power supply evaluation purposes. schematic Figure INSTALLED UNITRODE'S DEMONSTRATION KIT. 4.7k 1/10W 0603 RESISTOR INTERNAL PULLUP DESIRED. Overvoltage Protection: UC3910 provides both OVPB pins protection case overvoltage. capable driving perform crowbar func= +7.48% -7.48% +14.96%
3.34k 100=-(RDIV 16.7)
APPLICATION NOTE
tion. OVPB open collector, active signal which designed pull down UC3886 CAO/ENBL signal disable UC3886 gate drive. Overvoltage Protection circuit consists SCR1, CR2, R06. Fuse serves protect circuit under circumstances: MOSFET short circuit failure when crowbar fired. fuse chosen based maximum operating power efficiency. POUTmax Volts 11.2 Amps Watts Watts lINmax Amperes 0.80 5.0V Ampere fuse chosen. Characterizing SCR's Crowbar Applications discussed extensively Motorola's Thyristor Device Data book [5]. SCR1 chosen based gate trigger current, On-State current rating, because discharge substantial amount aluminum capacitors, Peak Non-repetitive surge current rating. SCR1 itself will protect Pentium®Pro processor against overvoltage except causing fuse open, which take substantial amount time. provides additional path discharge output capacitors directly order clamp output voltage protect processor immediately. connected before sense resistor, order current limiting resistor when crowbar fired. rated surge current Amperes. Connecting crowbar output voltage appear best protect Pentium®Pro processor case overvoltage failure. However, UC3886 provides current limiting mechanism, which would cause sink programmed current limit. input fuse would open under these circumstances because output power being delivered. output would most likely fail thermally open, thus defeating protection mechanism. Resistor from gate ground chosen protect against false firing dv/dt conditions. will draw approximately 15mA when fired, gate voltage approximately volts. chosen limit current from UC3910 while insuring that gate trigger current sufficient down 10°C. UC3910 will source least 65mA when activated. limits current preventing excessive droop when fired.
U-157
open collector signal OVPB also triggered during overvoltage protection fault. This signal used disable UC3886 gate drive connecting directly UC3886 CAO/ENBL signal. installed Unitrode's demonstration "jumper" only, enable disable this feature. Normal applications will directly connect UC3886 CAO/ENBL UC3910 OVPB pin. Note that OVPB signal open collector signal therefore "OR';d" with external open collector OUTEN signals. Setting Filters VSENSE DACOUT UC3910 UC3910 VSENSE requires filter isolate from power supply output [6]. resistor acts both part filter limit current into VSENSE pin. During UVLO UC3910, VSENSE actively pulled order prevent false overvoltage protection signals. filter resistor chosen limit input current 500µA under maximum programmable voltage Pentium®Pro. 3.4V 6.8k 500µA
filter capacitor chosen filter corner frequency approximately FSWITCH/10 order reduce switching frequency ripple 20dB. 1170pF (200kHz/10) 6.8k 1200pF standard values filter capacitor output DACOUT, C15, chosen insure that DACOUT rises faster rate than VSENSE. This prevents false signals during brownout glitch conditions. 2720pF
2700pF standard value Note that resistor connected UC3910 VSENSE used debug purposes only required normal operation. Programming Current Limit with Current Sense Amplifier UC3886 nominal current limit 12.5 Amperes desired protect power supply under short circuit con-
APPLICATION NOTE
ditions. Accurate current limiting advantageous this Buck regulator limits power dissipated freewheeling diode under short circuit conditions. gain current sense amplifier, GCSA, based desired current limit value sense resistor [4], using: GCSA RSENSE GCSA Volt
REGULATION 5.0%
U-157
Reserved Ripple Voltage
4.0%
Reserved Tolerance
3.0% 2.0% 1.0% 0.0% -1.0% -2.0% -3.0% -4.0% -5.0% IOUT IMAX 100%
Desired Regulation Load
Regulation Load
Reserved Tolerance Reserved Ripple Voltage
Volt 12.5A 0.01
current sense amplifier configured differential amplifier using four external resistors, R18, R19, R21, with gain equal GCSA should load down UC3886 Current Sense Amplifier, chosen 33.2k. Therefore 33.2k 4.22k resulting GCSA 7.87 nominal short circuit current limit, ISC, 12.7 Amperes. signal UC3886 must filtered insure noise free bias voltage current sense signal ISO. Programming Non-Integrating Gain Voltage Amplifier UC3886 Managing voltage regulation load, maintaining regulation involves non-integrating gain about UC3886 voltage amplifier. Without non-integrating gain, number output capacitors must increase. Application note U-156 [4], Appendix details goals requirements programming non-integrating gain. specified regulation window ±5%. VRIPPLE Error, which each ±1%, reserve specified window. This leaves window load regulation. desired regulation performance, versus load current, shown Figure Setting load regulation nominally will allow maximum voltage excursion during load transient. UC3886 error voltage, COMP, will vary with load current from 0.0A 12.7A. change error voltage will 11.2 Amps 0.95V 0.95V 12.7 Amps 0.834 Volts
Figure Load Regulation
change COMP 0.95 volts used because change 1.0V ±50mV, under worst case regulation window must held. Figure shows that load regulation parasitic resistances from load maximum load. From desired load regulation curve, swing output voltage associated with change from Amps (Not IMIN this case) IMAX determined -6.3%. drop intrinsic circuit then subtracted desired regulation swing -5.3%. From lowest operating voltage, change output voltage VOUT 5.3% 0.127 Volts gain around Voltage Amplifier determined ratio chosen achieve desired voltage swing over operating load range. VOUT Gain R16/R14 0.88V 6.57 0.127V
therefore R16/R14
feedback resistor chosen very large insure that there loading effects voltage amplifier output. 100k resulting gain about Voltage Amplifier 6.67. Non-Integrating gain negative regulation slope with regards load current, must shifted order swing about nominal voltage. offset created resistive divider which shifts regulation window +3.1%. chosen (VNOM therefore VNOM
APPLICATION NOTE
yielding 487k. 1.03 Filtering Canceling Offset Current Command UC3886 recommended that decoupling capacitor, placed very close COMMAND UC3886, this voltage voltage which commands power supply output, noise will directly couple power supply output. added series between UC3910 DACOUT UC3886 COMMAND order minimize errors offset currents UC3886 voltage amplifier. chosen match impedance VSENSE input UC3886 voltage amplifier. Remember that UC3910 DACOUT internal resistor. Therefore RDAC 9.7k 100k 487k
U-157
From oscillator timing equations, ramp slope 5.0µs 50ns (Deadtime oscillator) Ramp 2.8V 1.0V 1.8Vp-p Ramp 1.8V Ramp Slope TS-TD 4.95µs 0.364 Volts/µs Step Calculate inductor current downslope. downslope occurs during Buck regulator switch time. inductor downslope maximum maximum output voltage with minimum output inductance, which occurs maximum load maximum output voltage. diode forward voltage approximately 0.35V 11.2A VOUTmax 3.4V LOUT maximum operating current 12µH Inductor 3.4V 0.35V 0.313A/µs 12.0µH Step Convert inductor current downslope voltage downslope seen output Current Sense Amplifier. Inductor dv/dt 0.313A/µs 0.01 33.2k 24.6mV/µs 4.22k Step gain from Current Amplifier meet slope criteria. Reduce GCAmax account amplified voltage ripple output capacitors. Reduce gain more account Inductor Oscillator variations. oscillator Ramp Slope 0.364V/µs Inductor dv/dt where gain Current Amplifier switching frequency Therefore: FSWITCH 364mV 0.60 24.6mV
CLOSING LOOP WITH UC3886 AVERAGE CURRENT MODE CONTROLLER basis closing Average Current Voltage loops this circuit found Unitrode Application Note U-140 Unitrode Seminar Topic "Switching Power Supply Control Loop Design" [7]. This application note presents step-by-step methodology solving loop compensation components found Figure current loop completed first with voltage loop follow. goal closing loops this power supply obtain stable closed loop response current voltage loops, with overall closed loop crossover frequency between 10kHz 32kHz. Closing Current Loop Step Calculate Oscillator Ramp seen Comparator input. From U-140, known that "The amplified inductor current downslope input comparator must exceed oscillator ramp slope other comparator input".
Resistors inverting
APPLICATION NOTE
gain about UC3886 Current Amplifier. Pick limit loading Current Amplifier output. Then program Current Amplifier's inverting gain FSWITCH. 10.5k 1.24k standard values 8.47 product UC3886 Current Amplifier 3.5MHz therefore gain 8.47 200kHz within device's GBW. Step Find crossover frequency current loop gain first finding small signal control-to-output gain, buck regulator current loop power section. Consider fact that inductor, LOUT, plays role equation that since LOUT swings significantly with load current, does small signal control-to-output gain defined U-140 from output, VCA, voltage across sense resistor, VRS. UC3886 application however must gain stage factor Current Sense Amplifier gain. determined Duty change duty cycle change Current Amplifier output 100%/VS, where Duty where peak-to-peak voltage change oscillator ramp change resistor voltage change inductor current simply value sense resistor, Figure ILout Duty
Lout Lout
U-157
change inductor current change duty cycle function input voltage. small signal voltage applied inductor simply small signal changes Duty. change inductor current change applied inductor voltage (small signal) given where Duty ZOUT therefore ILout Duty ZOUT
which leads transfer function ILout Duty ZOUT ZOUT dominated output inductor frequencies above resonant frequency, results single pole rolloff that inductor, which what shown U-140 "VIN/S LOUT" term. complete impedance function includes output Inductor, Capacitor, Sense Resistor, Inductor Resistance, ESR, Load Resistance. parasitic resistances will help dampen response resonant frequency should ignored. output impedance given ZOUT LOUT RLout
ESL) ESL)
RLout Resistance output inductor Output capacitance Output capacitance Output capacitance Load Resistance Now, solving control-to-output gain, Current Loop only), Duty Duty GCSA
Lout Lout
simplified
APPLICATION NOTE
U-157
SENSE)
maximum input voltage maximum value LOUT, minimum load. Solving crossover frequency: VImax FCmax GCSA LOUTmin 5.25V 0.01 7.87 8.47 1.8V 120mH
U-140 states multiply control-to-output power loop gain, gain Current Amplifier achieve overall current loop gain. Loop (RS) ZOUT
GCSA
.8kHz
GCSA
FCmin
VImin GCSA LOUTmax 4.75V 0.01 7.87 8.47 1.8V 24.0µH
Equating current loop gain will yield loop crossover frequency,
11.7kHz where input voltage Step pole-zero compensation into Current Amplifier solving CZERO (C25 C28) CPOLE (C27), solve current loop transfer function. zero should placed below minimum current loop crossover frequency, FCmin. value CZERO determined Czero FCmin 11.7kHz 10.5k
ZOUT dominated output inductor region crossover frequency, therefore ZOUT(fc) replaced LOUT Solving simplifying yields: (TS-TD)
Notice that LOUT falls equation, therefore only "Load" dependency value This true ONLY Lout Constant with load current. swinging choke used, then Lout cannot drop equation. crossover frequency current loop therefore determined GCSA LOUT therefore GCSA LOUT
1296pF CZERO 1220pF capacitors used allow tuning this frequency) pole should placed FS/2. value CPOLE determined CPOLE CZERO FS/2 CZERO)
1220pF 200kHz/2 10.5k 1220pF)
crossover frequency current loop will therefore vary function load, with minimum crossover frequency
173pF CPOLE 180pF
APPLICATION NOTE
transfer function compensated current amplifier GCAs (CPOLE CZERO) (CZERO (R24 CPOLE overall current loop determined multiplying control-to-output transfer function current amplifier transfer function, Loop GCAs ZOUTs
U-157
Step Generate model closed current loop transconductance. small signal current loop modeled fixed gain frequencies equal transconductance forced current loop, having pole current loop crossover frequency, fCI, shown Figure below.
TRANSCONDUCTANCE (dB)
GCSA GCAs which plotted Figure
FSWI
Minimum Load FREQUENCY (Hz)
GAIN (dB)
Maximum Load
Figure Small Signal Current Loop Transfer Function Loads
where transconductance, TC(s) determined frequency gain transconductance (remember, transconductance units 22.1dB Gain= GCSA 0.01 7.87 TC(s) GCSA Step Determine output impedance power circuit gain, GVs. output impedance determined output capacitance, parasitics, load resistance.
FREQUENCY Compensated Current Amplifier Current Loop Minimum Load Current Loop Maximum Load
Figure Current Amplifier Current Loop Bode Plot Minimum Maximum Loads
lower crossover frequency above estimated range 11.7kHz because gain compensated Current Amplifier flat gain 8.47 slightly higher integrating feedback Current Amplifier. changes loop gain frequencies dominated changes load resistance, while variation around crossover frequency function change inductance current. Closing Voltage Loop: voltage loop must closed according guidelines Unitrode Seminar Topic "Switching Power Supply Control Loop Design". compensation around voltage amplifier this circuit will differ from seminar topic however utilizing non-integrating gain [4].
ZVout(s)
ESL)+
RLOAD
LOAD
power circuit gain equals current loop transconductance times output impedance, TC(s) ZVout(s)
APPLICATION NOTE
Step Determine gain required compensated voltage amplifier. Insure that gain switching frequency does increase slope above required amount ESR. resistors around voltage amplifier were determined requirements non-integrating gain 15.0k 100k inductor current di/dt rate known maximum 0.313A/µs. This inductor current ramp times output capacitor multiplied gain voltage current amplifiers seen Comparator. total contribution ripple contributed ramp comparator limiting factor gain voltage amplifier, GVA. Step reduced GCAmax account this factor. gain Current Amplifier switching frequency, from Figure 3.3. Therefore, from Step with equivalent output capacitors being 11.0m 0.313A/µs (1+GCA(Fs)) GVAmax(Fs) 0.25 0364V/µs therefore GVAmax(Fs) 6.15 Since inverting gain 100k/15k 6.67, then voltage amplifier gain must rolled (add pole) prior switching frequency reduce gain less than GVAmax(Fs). Step Compensate Voltage Amplifier achieve desired loop gain phase reduce voltage amplifier gain switching frequency below GVAmax(Fs). voltage loop gain obtained multiplying power circuit gain, Voltage Amplifier gain, GVAs. 0.25 0364V/µs 0.313A/µs 0.011 3.3)
U-157
LoopVS GVAs GVAs TC(s)
COUT RLOAD
ESL)+
LOAD
voltage amplifier gain, without compensation, simply R16/R14 6.67. voltage loop gain plotted Figure showing very crossover frequency.
Voltage Loop Gain (dB)
Minimum Load Maximum Load
Frequency (Hz)
Figure Voltage Loop Gain without Additional Voltage Amplifier Compensation
voltage amplifier gain compensated adding frequency pole-zero pair order boost frequency gain. Note however, that gain cannot increased limited requirements nonintegrating gain. Secondly, high frequency pole added achieve desired crossover frequency reduce gain voltage amplifier beyond crossover frequency. frequency pole-zero pair order boost frequency (but gain, therefore boost crossover frequency. zero approximately 100Hz pole approximately 400Hz. equations pole zero FPOLE FZERO (R15 R14)
APPLICATION NOTE
0.1µF. Then FPOLE 3.98k 0.01µF
FCmin FCmax
U-157
Phase Margin (Degrees)
3.92k standard value. results are: FPOLE 406Hz FZERO 84Hz another pole roll gain obtain desired crossover frequency reduce gain voltage amplifier switching frequency. 180pF obtain pole frequency FPOLE 100k 180pF
Frequency (Hz) Loop Phase Minimum Load Loop Phase Maximum Load
FSWITCH
Gain (dB)
Frequency (Hz)
GVAmax
8.84kHz transfer function compensated voltage amplifier GVA(s) (R14 R15) With this compensation, voltage amplifier gain loop response Voltage Loop plotted Figure MEASURED RESULTS FROM DEMONSTRATION Figure provides measured open loop response bode plots power supply under nominal 3.1V output IOmax 11.2 Amperes. Figure shows regulation measured load test configuration, with nominal output voltage 3.100V. measured test configuration impedance from output connector resistive load 1.50m, which accounts 17mV (0.54%) drop full load. load regulation curve matches predicted nonintegrating regulation curve. Figure shows measured efficiency power dissipation test configuration, with nominal output voltage 3.100V. input voltage fixed 5.00V. test board
Gain (dB)
Compensated Voltage Amplifier Voltage Loop Gain Minimum Load Voltage Loop Gain Maximum Load
Figure Final Voltage Loop Gain Phase Plots
COMPONENTS USED VARIATIONS COMPENSATION SCHEME. DEMONSTRATION SHIPPED WITH Z1=10 WITHOUT C26.
Phase
Gain
1000
10000
100000
Frequency (Hz)
Figure Open Loop Response with VOUT 3.1V, IOUT 11.2A
subjected 100LFM airflow approximately 25°C ambient temperature. full load efficiency 83.6%.
Phase Margin (Degrees)
APPLICATION NOTE
100%
U-157
Efficiency
0.0%
100%
Power Dissipated
120%
20.0%
40.0%
60.0%
80.0%
100.0%
120.0%
IOmax
IOmax
Figure Regulation VOUT 3.1V Measured Load
Figure Efficiency Power Dissipation Load Module with 3.100V nominal Output
measured efficiency includes power dissipated bias power supply. +12V current, ICC, measured 25.0mA during normal operation, fixed with varying load. With
OUTEN signal disabling power supply, measured 18.5mA, supplying current only UC3886 UC3910, gate drive. average gate drive current measured 6.50mA.
Figure Ripple Voltage Gate Voltage. VOUT 3.03V, IOUT 11.2A.
Power Dissipated
Regulation
Efficiency
APPLICATION NOTE
U-157
Figure Source Voltage (Top) Gate Voltage. VOUT 3.03V, IOUT 11.2A
Figure Short Circuit Source Voltage (Top) Gate Voltage. VOUT 0.06V. UC3886 skips cycles maintain accurate current limit.
APPLICATION NOTE
U-157
Figure Transient Response 125Hz, 0.3A 11.2A 0.3A Load Change. VOUT (Top) centered about 3.10V, between cursors. Load current (Middle) 2A/div varies 30A/µs. Input current (Bottom) 5A/div. overshoots charge input output caps after load step.
Figure VOUT (Top) Centered about 3.100V (Marker during 0.3A 11.2A transient. Input current (Bottom, 2A/div) rises 0.047A/µs during load step.
APPLICATION NOTE
U-157
Figure VOUT (Top) Centered about 3.100V (Marker during 0.3A 11.2A transient. Source (Bottom) shows 100% duty cycle inductor current ramps full load current. Slope Source RDSon.
Figure VOUT (Top) Centered about 3.100V (Marker during 0.3A 11.2A transient. ISO, UC3886 (Bottom) swings from 3.10V (Marker 4.10V measured 12.6A short circuit current. output inductor calculated 27µH during this swing high Flux.
APPLICATION NOTE
U-157
Figure VOUT (Top) Centered about 3.100V (Marker during 11.2A 0.3A transient. Input current (Bottom, 2A/div) falls 0.054A/µs during load step.
Figure VOUT (Top) Centered about 3.100V (Marker during 11.2A 0.3A transient. ISO, UC3886 (Bottom) swings from 4.00V (Marker 3.10V. output inductor calculated 28uH during this swing high Flux.
APPLICATION NOTE
U-157
Figure Transient Response 125Hz, 0.3A 11.2A 0.3A Load Change. VOUT (Top) centered about 3.10V. Input voltage (Bottom) shows only 130mV deviation during load steps without input inductor, impedance input capacitors.
CONCLUSION highly accurate power supply been demonstrated which uses Unitrode's UC3886 UC3910 ICs. This meets Intel power supply specifications, excellent regulation, transient response, efficiency. been demonstrated that single output inductor allow continuous mode operation, meet stringent transient response Pentium®Pro, limit input current rate well. non-integrating voltage loop regulation been proven fewer output capacitors because larger transient voltage swing allowed this technique. REFERENCES Intel Application Note AP-523, Pentium® Processor Power Distribution Guidelines, November 1995, Order Number: 242764-001 Unitrode Application Note U-140, Average Current Mode Control Switching Power Supplies, Lloyd Dixon
Micrometals, Anaheim, Iron Powder Cores Catalog Issue Power Conversion Line Filter Applications, Percent Initial Permeability Peak Flux Density Curve. Unitrode Application Note U-156, UC3886 Controller Uses Average Current Mode Control Meet Transient Regulation Performance High Processors, Larry Spaziani Motorola Thyristor Device Data Book, DL137/D Motorola Inc. Phoenix, Arizona Unitrode Application Note U-158, UC3910 Combines Programmability, Accuracy Integrated Functions Control Monitor High Processor Power Supplies, Larry Spaziani Unitrode Power Supply Design Seminar SEM-800, Switching Power Supply Control Loop Design, Lloyd Dixon. Reprinted SEM900 SEM-1000.
UNITRODE CORPORATION CONTINENTAL BLVD. MERRIMACK, 03054 TEL. 603-424-2410 603-424-3460
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
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FUELING MEGAPROCESSOR DC/DC CONVERTER DESIGN REVIEW FEATURING UC3886 U

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