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HSTL16919 9-bit 18-bit HSTL LVTTL memory address latch with pull-up resistor
Product data File under Integrated Circuits ICL03 2001
Product data
9-bit 18-bit HSTL LVTTL memory address latch with pull-up resistor
HSTL16919
FEATURES
Inputs meet JEDEC HSTL Std. JESD 8-6, outputs meet
Level specifications
CONFIGURATION
pull-up inputs classification testing done JEDEC Standard JESD22.
Protection exceeds 2000 method A114.
Latch-up testing done JEDEC Standard JESD78, which
exceeds
Packaged 48-pin plastic thin shrink small outline package
(TSSOP48)
DESCRIPTION
HSTL16919 9-bit 18-bit D-type latch designed 3.15 3.45 operation. inputs accept HSTL levels outputs provide LVTTL levels. HSTL16919 particularly suitable driving address banks memory. Each bank nine outputs controlled with latch-enable (LE) input. Each nine inputs tied inputs D-type latches that provide true data outputs. While outputs corresponding nine latches follow inputs. When taken HIGH, outputs latched levels inputs. HSTL16919 characterized operation from
VREF
SW00768
ORDERING INFORMATION
PACKAGES 48-pin plastic thin shrink small outline package (TSSOP48) TEMPERATURE RANGE ORDER CODE HSTL16919DGG NUMBER SOT362-1
2001
853-2269 26745
Product data
9-bit 18-bit HSTL LVTTL memory address latch with pull-up resistor
DESCRIPTION
SYMBOL D[1-9] 1Q[1-9] Outputs 2Q[1-9] VREF Latch enable
HSTL16919
LOGIC DIAGRAM (positive logic)
FUNCTION
Inputs
VREF
Reference voltage Supply voltage Ground
EIGHT OTHER CHANNELS
SW00906
FUNCTION TABLE
INPUTS OUTPUT
NOTE: Output level before indicated steady-state input conditions were established.
2001
Product data
9-bit 18-bit HSTL LVTTL memory address latch with pull-up resistor
ABSOLUTE MAXIMUM RATINGS1
Over operating free-air temperature range (unless otherwise noted). SYMBOL Tstg PARAMETER Supply voltage range Input voltage range
HSTL16919
CONDITIONS
RATING -0.5 +4.6 -0.5 +0.5 -0.5 +0.5
UNIT °C/W
Output voltage range Input clamp current
±100 +150
Output clamp current Continuous output current Continuous current through each Package thermal impedance Storage temperature range
NOTES: Stresses beyond those listed cause permanent damage device. These stress ratings only functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. input output negative-voltage ratings exceeded input output clamp-current ratings observed. This current flows only when output high state VCC. package thermal impedance calculated accordance with JESD
RECOMMENDED OPERATING CONDITIONS1
LIMITS SYMBOL VREF Tamb Supply voltage Reference voltage Input voltage high-level input voltage low-level input voltage high-level input voltage low-level input voltage High-level output current Low-level output current Operating free-air temperature range inputs inputs inputs inputs PARAMETER 3.15 0.68 VREF VREF 0.75 3.45 VREF VREF UNIT
NOTE: unused inputs device must held ensure proper device operation.
2001
Product data
9-bit 18-bit HSTL LVTTL memory address latch with pull-up resistor
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range (unless otherwise noted). LIMITS SYMBOL Control inputs Data inputs VREF Control inputs Data inputs Outputs PARAMETER TEST CONDITIONS 3.15 3.15 3.15 3.45 3.45 3.45 VREF 0.68 3.45
HSTL16919
-1.2 -500 -500
UNIT
NOTE: typical values Tamb
TIMING REQUIREMENTS
Over recommended operating free-air temperature range (unless otherwise noted). SYMBOL tldr PARAMETER Pulse duration Setup time Hold time Data race condition time
TEST CONDITIONS (Figure before (Figure after (Figure after
±0.15
UNIT
NOTE: This maximum time after switches that data input return latched state from opposite state without producing glitch output.
SWITCHING CHARACTERISTICS
Over recommended operating free-air temperature range; VREF 0.75 SYMBOL PARAMETER FROM (INPUT) Propagation delay (Figure (OUTPUT) ±0.15 UNIT
SIMULTANEOUS SWITCHING CHARACTERISTICS
Over recommended operating free-air temperature range; VREF 0.75 SYMBOL PARAMETER FROM (INPUT) (OUTPUT) ±0.15 UNIT
Propagation delay; outputs switching (Figure
2001
Product data
9-bit 18-bit HSTL LVTTL memory address latch with pull-up resistor
VOLTAGE WAVEFORMS
INPUT VREF VREF 0.25
HSTL16919
LOAD CIRCUIT
FROM OUTPUT UNDER TEST (see Note)
1.25
SW00770
SW00773
Figure Pulse duration
NOTE: includes probe capacitance. Figure Load circuit
1.25
VREF 0.25 1.25
DATA INPUT
VREF
VREF 0.25
SW00771
Figure Setup Hold times
1.25 INPUT (Note VREF tPLH VREF 0.25 tPHL OUTPUT
SW00772
Figure Propagation delay times NOTES: input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement. tPHL tPLH same tpd.
2001
Product data
9-bit 18-bit HSTL LVTTL memory address latch with pull-up resistor
TSSOP48: plastic thin shrink small outline package; leads; body width
HSTL16919
SOT362-1
2001
Product data
9-bit 18-bit HSTL LVTTL memory address latch with pull-up resistor
HSTL16919
Data sheet status
Data sheet status Objective data Preliminary data Product status Development Qualification Definitions This data sheet contains data from objective specification product development. Philips Semiconductors reserves right change specification manner without notice. This data sheet contains data from preliminary specification. Supplementary data will published later date. Philips Semiconductors reserves right change specification without notice, order improve design supply best possible product. This data sheet contains data from product specification. Philips Semiconductors reserves right make changes time order improve design, manufacturing supply. Changes will communicated according Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
Please consult most recently issued datasheet before initiating completing design. product status device(s) described this data sheet have changed since this data sheet published. latest information available Internet
Definitions
Short-form specification data short-form specification extracted from full data sheet with same type number title. detailed information relevant data sheet data handbook. Limiting values definition Limiting values given accordance with Absolute Maximum Rating System (IEC 134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Applications that described herein these products illustrative purposes only. Philips Semiconductors make representation warranty that such applications will suitable specified without further testing modification.
Disclaimers
Life support These products designed life support appliances, devices systems where malfunction these products reasonably expected result personal injury. Philips Semiconductors customers using selling these products such applications their risk agree fully indemnify Philips Semiconductors damages resulting from such application. Right make changes Philips Semiconductors reserves right make changes, without notice, products, including circuits, standard cells, and/or software, described contained herein order improve design and/or performance. Philips Semiconductors assumes responsibility liability these products, conveys license title under patent, copyright, mask work right these products, makes representations warranties that these products free from patent, copyright, mask work right infringement, unless otherwise specified. Philips Semiconductors East Arques Avenue P.O. 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Copyright Philips Electronics North America Corporation 2001 rights reserved. Printed U.S.A. Date release: 07-01 Document order number: 9397 08587
2001
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