Designing Switching Voltage Regulators With TL494 Patrick Griffit
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Designing Switching Voltage Regulators With TL494
Patrick Griffith ABSTRACT TL494 power-supply controller discussed detail. general overview TL494 architecture presents primary functional blocks contained device. in-depth study interrelationship between functional blocks highlights versatility limitations TL494. usefulness TL494 power-supply controller also demonstrated through several basic applications, design example included 5-V/10-A power supply. Standard Linear Logic
Contents Introduction Basic Device Principle Operation Reference Regulator Oscillator Operation Frequency Operation Above Dead-Time Control/PWM Comparator Dead-Time Control Comparator Pulse-Width Modulation (PWM) Error Amplifiers Output-Control Logic Output-Control Input Pulse-Steering Flip-Flop Output Transistors Applications Reference Regulator Current Boosting Regulator Applications Oscillator Synchronization Master/Slave Synchronization Master Clock Operation Fail-Safe Operation Error-Amplifier-Bias Configuration Current Limiting Fold-Back Current Limiting Pulse-Current Limiting
Trademarks property their respective owners.
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Applications Dead-Time Control Soft Start Overvoltage Protection Modulation Turnon/Turnoff Transition Design Example Input Power Source Control Circuits Oscillator Error Amplifier Current-Limiting Amplifier Soft Start Dead Time Inductor Calculations Output Capacitance Calculations Transistor Power-Switch Calculations List Figures TL494 Block Diagram TL494 Modulation Technique Reference Regulator Reference Voltage Input Voltage Internal-Oscillator Schematic Oscillator Frequency RT/CT Variation Dead Time RT/CT Dead-Time Control/PWM Comparator Error Amplifiers Multiplex Structure Error Amplifiers Error-Amplifier-Bias Configurations Controlled-Gain Applications Amplifier Transfer Characteristics Amplifier Bode Plot Output-Steering Architecture Pulse-Steering Flip-Flop Output-Transistor Structure Conventional Three-Terminal Regulator Current-Boost Technique TL494 Reference Regulator Current-Boost Technique Master/Slave Synchronization External Clock Synchronization Oscillator Start-Up Circuit Fail-Safe Protection Error-Amplifier-Bias Configurations Fold-Back Current Limiting Fold-Back Current Characteristics Error-Signal Considerations
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Peak-Current Protection Dead-Time Control Characteristics Tailored Dead Time Soft-Start Circuit Overvoltage-Protection Circuit Turnon Transition Turnoff Transition Input Power Source Switching Control Sections Error-Amplifier Section Current-Limiting Circuit Soft-Start Circuit Switching Circuit Power-Switch Section
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Introduction
Monolithic integrated circuits control switching power supplies have become widespread since their introduction 1970s. TL494 combines many features that previously required several different control circuits. purpose this application report give reader thorough understanding TL494, features, performance characteristics, limitations.
Basic Device
design TL494 only incorporates primary building blocks required control switching power supply, also addresses many basic problems reduces amount additional circuitry required total design. Figure block diagram TL494.
VREF Output Control
Oscillator
Reference Flip-Flop Section
Dead-Time Control
Amplifier Inputs
Error Amplifiers
Feedback
Figure TL494 Block Diagram
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Principle Operation
TL494 fixed-frequency pulse-width-modulation (PWM) control circuit. Modulation output pulses accomplished comparing sawtooth waveform created internal oscillator timing capacitor (CT) either control signals. output stage enabled during time when sawtooth voltage greater than voltage control signals. control signal increases, time during which sawtooth input greater decreases; therefore, output pulse duration decreases. pulse-steering flip-flop alternately directs modulated pulse each output transistors. Figure shows relationship between pulses signals.
Control Signal
Figure TL494 Modulation Technique control signals derived from sources: dead-time (off-time) control circuit error amplifier. dead-time control input compared directly dead-time control comparator. This comparator fixed 100-mV offset. With control input biased ground, output inhibited during time that sawtooth waveform below This provides preset dead time approximately which minimum dead time that programmed. comparator compares control signal created error amplifiers. function error amplifier monitor output voltage provide sufficient gain that millivolts error input result control signal sufficient amplitude provide 100% modulation control. error amplifiers also used monitor output current provide current limiting load.
Reference Regulator
TL494 internal reference regulator shown Figure addition providing stable reference, acts preregulator establishes stable supply from which output-control logic, pulse-steering flip-flop, oscillator, dead-time control comparator, comparator powered. regulator employs band-gap circuit primary reference maintain thermal stability less than 100-mV variation over operating free-air temperature range 70_C. Short-circuit protection provided protect internal reference preregulator, load current available additional bias circuits. reference internally programmed initial accuracy maintains stability less than 25-mV variation over input voltage range input voltages less than regulator saturates within input tracks (see Figure
Designing Switching Voltage Regulators With TL494
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VREF
Figure Reference Regulator
VREF Reference Voltage
Input Voltage
Figure Reference Voltage Input Voltage
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Oscillator
schematic TL494 internal oscillator shown Figure oscillator provides positive sawtooth waveform dead-time comparators comparison various control signals.
Reference Regulator
Figure Internal-Oscillator Schematic Operation Frequency frequency oscillator programmed selecting timing components oscillator charges external timing capacitor, with constant current; value which determined external timing resistor, This produces linear-ramp voltage waveform. When voltage across reaches oscillator circuit discharges charging cycle reinitiated. charging current determined formula: ICHARGE V/RT period sawtooth waveform )/ICHARGE frequency oscillator becomes: fOSC 1/(RT
However, oscillator frequency equal output frequency only single-ended applications. push-pull applications, output frequency one-half oscillator frequency. Single-ended applications: 1/(RT Push-pull applications: 1/(2RT
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oscillator programmable over range kHz. Practical values range from respectively. plot oscillator frequency versus shown Figure stability oscillator free-air temperatures from 70_C various ranges also shown Figure
Timing Resistance 0.01 0.001
Frequency NOTE: percent oscillator frequency variation over 70°C free-air temperature range represented dashed lines.
Figure Oscillator Frequency RT/CT Operation Above operation frequency kHz, period oscillator 6.67 dead time established internal offset dead-time comparator (~3% period) yields blanking pulse This minimum blanking pulse acceptable ensure proper switching pulse-steering flip-flop. frequencies above kHz, additional dead time (above provided internally ensure proper triggering blanking internal pulse-steering flip-flop. Figure shows relationship internal dead time (expressed percent) various values
Timing Resistance 0.001 0.01 Frequency
Figure Variation Dead Time RT/CT
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Dead-Time Control/PWM Comparator
functions dead-time control comparator comparator incorporated single comparator circuit (see Figure functions totally independent; therefore, each function discussed separately.
Reference Regulator FlipFlop
VREF
Dead-Time Control
Error Amplifiers Feedback
Internal offset
Figure Dead-Time Control/PWM Comparator Dead-Time Control dead-time control input provides control minimum dead time (off time). output comparator inhibits switching transistors when voltage input greater than ramp voltage oscillator (see Figure 28). internal offset ensures minimum dead time with dead-time control input grounded. Applying voltage dead-time control input impose additional dead time. This provides linear control dead time from minimum 100% input voltage varied from respectively. With full-range control, output controlled from external sources without disrupting error amplifiers. dead-time control input relatively high-impedance input should used where additional control output duty cycle required. However, proper control, input must terminated. open circuit undefined condition.
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Comparator comparator biased from reference regulator. This provides isolation from input supply improved stability. input comparator does exhibit hysteresis, protection against false triggering near threshold must provided. comparator response time from either control-signal inputs output transistors, with only 100-mV overdrive. This ensures positive control output within one-half cycle operation within recommended 300-kHz range. Pulse-Width Modulation (PWM) comparator also provides modulation control output pulse width. this, ramp voltage across timing capacitor compared control signal present output error amplifiers. timing capacitor input incorporates series diode that omitted from control signal input. This requires control signal (error amplifier output) ~0.7 greater than voltage across inhibit output logic, ensures maximum duty cycle operation without requiring control voltage sink true ground potential. output pulse width varies from period voltage present error amplifier output varies from respectively. Error Amplifiers schematic error amplifier circuit shown Figure Both high-gain error amplifiers receive their bias from supply rail. This permits common-mode input voltage range from -0.3 less than Both amplifiers behave characteristically single-ended single-supply amplifier, that each output active high only. This allows each amplifier pull independently decreasing output pulse-width demand. With both outputs ORed together inverting input node comparator, amplifier demanding minimum pulse dominates. amplifier outputs biased current sink provide maximum pulse width when both amplifiers biased off.
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Reference Regulator
VREF AMP2 Comparator
Inverting Input Noninverting Input
Feedback
Figure Error Amplifiers Figure shows output structure amplifiers operating into 300-µA current sink. Attention must given this node biasing considerations gain-control external-control interface circuits. Because amplifier output biased only through current sink (ISINK mA), bias current required external circuitry into feedback terminal must exceed capability current sink. Otherwise, maximum output pulse width limited. Figure shows proper biasing techniques feedback gain control.
Reference Regulator Error Amplifier Error Amplifier
Comparator
Feedback
Figure Multiplex Structure Error Amplifiers
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Output VREF Output VREF
Figure Error-Amplifier-Bias Configurations Controlled-Gain Applications Figure shows plot amplifier transfer characteristics. This illustrates linear gain characteristics amplifiers over active input range comparator (0.5 This important overall circuit stability. open-loop gain amplifiers, output voltages from Bode plot amplifier response time shown Figure Both amplifiers have response time approximately from their inputs their outputs. Precautions should taken minimize capacitive loading amplifier outputs. Because amplifiers employ active pullup only, amplifiers' ability respond increasing load demand degraded severely capacitive loads.
Output Voltage
Input Voltage
Figure Amplifier Transfer Characteristics
Gain
Frequency
Figure Amplifier Bode Plot
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Output-Control Logic
output-control logic structured provide added versatility through external control. Designed either push-pull single-ended applications, circuit performance optimized selection proper conditions applied various control inputs. Output-Control Input output-control input determines whether output transistors operate parallel push-pull. This input supply source pulse-steering flip-flop (see Figure 14). output-control input asynchronous direct control over output, independent oscillator pulse-steering flip-flop. input condition intended fixed condition that defined application. parallel operation, output-control input must grounded. This disables pulse-steering flip-flop inhibits outputs. this mode, pulses seen output dead-time control/PWM comparator transmitted both output transistors parallel. push-pull operation, output-control input must connected internal reference regulator. Under this condition, each output transistors enabled, alternately, pulse-steering flip-flop.
Input Control Control Signal
Comparator
Control Signal Control Signal
COMP
Flip-Flop
Figure Output-Steering Architecture
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Pulse-Steering Flip-Flop pulse-steering flip-flop positive-edge-triggered D-type flip-flop that changes state synchronously with rising edge comparator output (see Figure 14). dead time provides blanking during this period ensure against possibility having both outputs simultaneously, during transition pulse-steering flip-flop outputs. schematic pulse-steering flip-flop shown Figure Since flip-flop receives trigger from output comparator, oscillator, output always operates push-pull. flip-flop does change state unless output pulse occurred previous period oscillator. This architecture prevents either output from double pulsing, restricts application control-signal sources feedback signals (for additional detail, Pulse-Current Limiting this application report).
Reference Regulator
Output Control
Output High
Transistor
Comparator Output
Figure Pulse-Steering Flip-Flop
Output Transistors
output transistors available TL494. output structure shown Figure Both transistors configured open collector/open emitter each capable sinking sourcing transistors have saturation voltage less than common-emitter configuration less than emitter-follower configuration. outputs protected against excessive power dissipation prevent damage, employ sufficient current limiting allow them operated current-source outputs.
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Flip-Flop Output Comparator Output
Collector Output
Emitter Output
Figure Output-Transistor Structure
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Applications
Reference Regulator
internal reference regulator designed primarily provide internal circuitry with stable supply rail varying input voltages. regulator provides sufficient drive sustain supply current additional load circuitry. However, excessive loading degrade performance TL494 because reference regulator establishes supply voltage much internal control circuitry. Current Boosting Regulator Conventional bootstrap techniques three-terminal regulators, such Figure recommended TL494. Normally, bootstrap programmed resistor that transistor turns load current approaches capability regulator. This works very well when current flowing into input (through determined load current. This necessarily case with TL494. input current only reflects load current includes current drawn internal control circuit, which biased from reference regulator well from input rail itself. result, load current drawn reference regulator does control bias shunt transistor
3-Terminal Regulator
ILOAD
Figure Conventional Three-Terminal Regulator Current-Boost Technique Figure shows bootstrapping technique that preferred TL494. This technique provides isolation between bias-circuit load reference regulator output provides sufficient amount supply current, without affecting stability internal reference regulator. This technique should applied bias circuit drive only because regulation high-current output solely dependent load.
Internal Circuit Reference Bias Reference
Figure TL494 Reference Regulator Current-Boost Technique
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Applications Oscillator
design internal oscillator allows great deal flexibility operation TL494 control circuit. Synchronization Synchronizing more oscillators common system easily accomplished with architecture TL494 control circuits. Since internal oscillator used only creation sawtooth waveform timing capacitor, oscillator inhibited long compatible sawtooth waveform provided externally timing capacitor terminal. Terminating terminal reference-supply output inhibit internal oscillator. Master/Slave Synchronization synchronizing more TL494s, establish device master program oscillator normally. Disable oscillators each slave circuit previously explained) sawtooth waveform created master each slave circuits, tying pins together (see Figure 19).
Master Slave Additional Slave Circuits
Figure Master/Slave Synchronization Master Clock Operation synchronize TL494 external clock, internal oscillator used sawtooth-pulse generator. Program internal oscillator period that master clock strobe internal oscillator through timing resistor (see Figure 20). turned when positive pulse applied base. This initiates internal oscillator grounding pulling base low. latched through collector and, result, internal oscillator locked charges, positive voltage developed across forms clamp trigger side completion period internal oscillator, timing capacitor discharged ground drives base negative, causing turn turn. With latch Q1/Q2 turned off, open circuited internal oscillator disabled until another trigger pulse experienced.
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VREF
Figure External Clock Synchronization common problem occurs during start-up when synchronizing power supply system clock. Normally, additional start-up oscillator required. Again, internal oscillator used modifying previous circuit slightly (see Figure 21). During power when output voltage low, biased causing stay internal oscillator behave normally. Once output voltage increased sufficiently VREF Figure 21), longer biased Q1/Q2 latch becomes dependent trigger signal, previously discussed.
VREF
Figure Oscillator Start-Up Circuit Fail-Safe Operation With modulation scheme employed TL494 structure oscillator, TL494 inherently turns either timing component fails. timing resistor opens, current provided oscillator charge addition bleeder resistor (see Figure ensures discharge With input ground, short circuits, both outputs inhibited.
(1/10)
Figure Fail-Safe Protection
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Error-Amplifier-Bias Configuration
design TL494 employs both amplifiers noninverting configuration. Figure shows proper bias circuits negative positive output voltages. gain control circuits, shown Figure integrated into bias circuits.
VREF Output VREF Positive Output Configuration Output Negative Output Configuration
Figure Error-Amplifier-Bias Configurations
Current Limiting
Either amplifier provided TL494 used fold-back current limiting. Application either amplifier limited primarily load-current control. architecture defines that these amplifiers used control applications. Both amplifiers have broad common-mode voltage range that allows direct current sensing output voltage rails. Several techniques employed current limiting.
Fold-Back Current Limiting
Figure shows circuit that employs proper bias technique fold-back current limiting. Initial current limiting occurs when sufficient voltage developed across compensate base-emitter voltage plus voltage across When current limiting occurs, output voltage drops. output decays, voltage across decreases proportionally. This results less voltage required across maintain current limiting. resulting output characteristics shown Figure
Figure Fold-Back Current Limiting
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ILOAD
Figure Fold-Back Current Characteristics Pulse-Current Limiting internal architecture TL494 does accommodate direct pulse-current limiting. problem arises from factors:
internal amplifiers function latch; they intended analog applications. pulse-steering flip-flop sees positive transition comparator trigger switches outputs prematurely, i.e., prior completion oscillator period.
result, pulsed control voltage occurring during normal on-time only causes output transistors turn also switches pulse-steering flip-flop. With outputs off, excessive current condition decays control voltage returns quiescent-error-signal level. When pulse ends, outputs again enabled residual on-time pulse appears opposite output. resulting waveforms shown Figure major problem here lack dead-time control. sufficiently narrow pulse result both outputs being concurrently, depending delays external circuitry. condition where insufficient dead time exists destructive condition. Therefore, pulse-current limiting best implemented externally (see Figure 27).
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Pulse Signal Response Dead-Time Control FlipFlop Output Control Logic
Error Signal Control Signal
Control Signal/CT Expected Outputs
Actual Outputs
Figure Error-Signal Considerations
Switching Circuit
VREF Dead-Time Control
Figure Peak-Current Protection Figure current switching transistors sensed RCL. When there sufficient current, sensing transistor forward biased, base pulled through dead-time control input pulled reference. Drive base provided through collector acts latch maintain saturated state when turns off, current decays through RCL. latch remains this state, inhibiting output transistors, until oscillator completes period discharges When this occurs, Schottky diode (D1) forward biases turns allowing dead-time control return programmed voltage.
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Applications Dead-Time Control
primary function dead-time control control minimum time output TL494. dead-time control input provides control from 100% dead time (see Figure 28).
Output Control Logic Dead-Time Control Dead Time
Control Input
Output
Figure Dead-Time Control Characteristics Therefore, TL494 tailored specific power transistor switches that used ensure that output transistors never experience common time. bias circuit basic function shown Figure dead-time control used many other control signals.
VREF (0.05 0.35
Dead-Time Control
Figure Tailored Dead Time Soft Start With availability dead-time control, input implementation soft-start circuit relatively simple; Figure shows example. Initially, capacitor forces dead-time control input follow reference regulator that disables both outputs, i.e., 100% dead time. capacitor charges through output pulse slowly increases until control loop takes command. additional control introduced this input, blocking diode should used isolate soft-start circuit. soft start desired conjunction with tailored dead time, circuit Figure used with addition capacitor across
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VREF Dead-Time Control
Figure Soft-Start Circuit blocking diode soft-start protection recommended. only does such circuitry prevent large current surges during power also protects against false signals that might created control circuit power applied. Overvoltage Protection dead-time control also provides convenient input overvoltage protection that sensed output voltage condition input protection. Figure shows TL431 sensing element. When supply rail being monitored increases point that developed driver node TL431 goes into conduction. This forward biases causing dead-time control pulled reference voltage disabling output transistors.
Monitored Supply Rail VREF
Dead-Time Control
TL431
Figure Overvoltage-Protection Circuit Modulation Turnon/Turnoff Transition Modulation output pulse TL494 accomplished modulating turnon transition output transistors. turnoff transition always concurrent with falling edge oscillator waveform. Figure shows oscillator output compared varying control signal resulting output waveforms. modulation turnoff transition desired, external negative slope sawtooth waveform (see Figure used without degrading overall performance TL494.
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Control Voltage Control Voltage/ Internal Oscillator
Output
On-Transition Modulated
Figure Turnon Transition
Control Voltage/ Internal Oscillator
Control Voltage
Output
Off-Transition Modulated
Figure Turnoff Transition
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Design Example
following design example uses TL494 create 5-V/10-A power supply. This design based following parameters: fOSC 20-kHz switching frequency 20-mV peak-to-peak (VRIPPLE) 1.5-A inductor current change
Input Power Source
32-V power source this supply uses 120-V input, 24-V output transformer rated 24-V secondary winding feeds full-wave bridge rectifier followed current-limiting resistor (0.3 filter capacitors (see Figure 34).
Bridge Rectifiers A/50
20,000 20,000
Figure Input Power Source output current voltage determined equations RECTIFIER SECONDARY RECTIFIER(AVG)
3-A/50-V full-wave bridge rectifier meets these calculated conditions. Figure shows switching control sections.
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NTE331 NTE6013
32-V Input
NTE153
VREF Control Load
TL494
0.001
Figure Switching Control Sections
Control Circuits
Oscillator Connecting external capacitor resistor pins controls TL494 oscillator frequency. oscillator operate kHz, using component values calculated equations
Choose 0.001 calculate
[(20
(0.001
*6)]
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Error Amplifier error amplifier compares sample output reference adjusts maintain constant output current (see Figure 36).
VREF TL494 TL494 Error Amplifier
Figure Error-Amplifier Section TL494 internal reference divided output-voltage error signal also divided output must regulated exactly 10-k potentiometer used place provide adjustment. increase stability error-amplifier circuit, output error amplifier back inverting input through reducing gain 100. Current-Limiting Amplifier power supply designed 10-A load current swing therefore, short-circuit current should 10.75 current-limiting circuit shown Figure
Load TL494 VREF TL494
(10)
Figure Current-Limiting Circuit Resistors reference about inverting input current-limiting amplifier. Resistor R11, series with load, applies noninverting terminal current-limiting amplifier when load current reaches output pulse width reduced accordingly. value
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Soft Start Dead Time reduce stress switching transistors start-up, start-up surge that occurs output filter capacitor charges must reduced. availability dead-time control makes implementation soft-start circuit relatively simple (see Figure 38).
Oscillator Ramp TL494
Voltage Oscillator Ramp Voltage
Output
Figure Soft-Start Circuit soft-start circuit allows pulse width output increase slowly (see Figure applying negative slope waveform dead-time control input (pin Initially, capacitor forces dead-time control input follow regulator, which disables outputs (100% dead time). capacitor charges through output pulse width slowly increases until control loop takes command. With resistor ratio 1:10 voltage after start-up soft-start time generally range clock cycles. clock cycles 20-kHz switching rate selected, soft-start time clock cycle value capacitor then determined soft-start time cycles) (13) (12)
This helps eliminate false signals that might created control circuit power applied.
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Inductor Calculations
switching circuit used shown Figure
Figure Switching Circuit size inductor required toff duty cycle VO/VI V/32 0.156 (design objective) time closed) (1/f) time open) (1/f) 42.2 ton/IL [(32 µs]/1.5 140.4
Output Capacitance Calculations
Once filter inductor been calculated, value output filter capacitor calculated meet output ripple requirements. electrolytic capacitor modeled series connection inductance, resistance, capacitance. provide good filtering, ripple frequency must below frequencies which series inductance becomes important. components interest capacitance effective series resistance (ESR). maximum calculated according relation between specified peak-to-peak ripple voltage peak-to-peak ripple current. ESR(max) O(ripple) 0.067 (14)
minimum capacitance necessary maintain ripple voltage less than 100-mV design objective calculated according equation 8fDV (15)
220-mF, 60-V capacitor selected because maximum 0.074 maximum ripple current
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Transistor Power-Switch Calculations
transistor power switch constructed with NTE153 drive transistor NTE331 output transistor. These power devices were connected hybrid Darlington circuit configuration (see Figure 40).
NTE331 10.8
NTE153
Control TL494
Figure Power-Switch Section hybrid Darlington circuit must saturated maximum output current IL/2 10.8 Darlington 10.8 must high enough exceed 250-mA maximum output collector current TL494. Based published NTE153 NTE331 specifications, required power-switch minimum drive calculated equations 16-18 FE(Q1) FE(Q2) 10.0 FE(Q2) FE(Q1)] (16) (17) (18)
value calculated BE(Q1) CE(TL494)] (1.5 0.7)] (0.144) Based these calculations, nearest standard resistor value selected R10. Resistors permit discharge carriers switching transistors when they turned off. power supply described demonstrates flexibility TL494 control circuit. This power-supply design demonstrates many power-supply control methods provided TL494, well versatility control circuit. (19)
Designing Switching Voltage Regulators With TL494
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