4Banks 16Bit Synchronous DRAM Preliminary Hyundai HY57V2571620 26
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HY57V2571620
4Banks 16Bit Synchronous DRAM Preliminary
Hyundai HY57V2571620 268,435,456bit CMOS Synchronous DRAM, ideally suited main memory applications which require large memory density high bandwidth. HY57V2571620 organized 4banks 4,196,304x16. HY57V2571620 offering fully synchronous operation referenced positive edge clock. inputs outputs synchronized with rising edge clock input. data paths internally pipelined achieve very high bandwidth. input output voltage levels compatible with LVTTL. Programmable options include length pipeline (Read latency 1,2, number consecutive read write cycles initiated single control command (Burst length 1,2,4,8, full page), burst count sequence(sequential interleave). burst read write cycles progress terminated burst terminate command interrupted replaced burst read write command cycle. (This pipelined design restricted `2N` rule.)
FEATURES
Single 3.3V 0.3V power supply device pins compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm pitch inputs outputs referenced positive edge system clock Data mask function Internal four banks operation Auto refresh self refresh 8192 refresh cycles 64ms Programmable Burst Length Burst Type Full Page Sequential Burst Interleave Burst Programmable Latency Clocks
ORDERING INFORMATION
Part
HY57V2571620TC-8 HY57V2571620TC-10P HY57V2571620TC-10S HY57V2571620TC-10 HY57V2571620LTC-8 HY57V2571620LTC-10P HY57V2571620LTC-10S HY57V2571620LTC-10
Clock Frequency
125MHz 100MHz
Power
Organization
Interface
Package
Normal 100MHz 100MHz 125MHz 100MHz Power 100MHz 100MHz 4Banks 4Mbits LVTTL 400mil 54pin TSOP
This document general product description subject change without notice. Hyundai Electronics does assume responsibility circuits described. patent licenses implied. Revision Jul.98
HY57V2571620
CONFIGURATION
VDDQ VSSQ VDDQ VSSQ LDQM /CAS /RAS A10/AP DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 VDDQ UDQM
54pin TSOP 400mil 875mil 0.8mm pitch
Clock NAME DESCRIPTION system clock input. other inputs registerd SDRAM rising edge CLK. Controls internal clock signal when deactivated, SDRAM will states among power down, suspend self refresh. Command input enable mask except CLK, Select either banks during both activity. Address RA12, Column Address Auto-precharge flag RAS, define operation. Refer function truth table details control output buffer read mode masks input data write mode Multiplexed data input output Power supply internal circuit input buffer Power supply connection
BA0,
Clock Enable Chip Select Bank Address Address Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground Connection
RAS, CAS,
DQ15 VDD/VSS VDDQ/VSSQ
Revision Jul.98
HY57V2571620
FUNCTIONAL BLOCK DIAGRAM
2Mbit 4banks Synchronous DRAM
4Mx16 Bank2
Addr. Latch/Predecode Decorder
Self Refresh Counter
Auto/Self Refresh
Address[0:12]
8KRef.Addr.[0:12]
Refresh Interval Timer
Refresh Counter
4Mx16 Bank0
Sense gates Column Decoder
[0:8]
BA(A14) State Machine BA(A13) /RAS /CAS
Precharge RowActive Column Active
Address Register
Column Addr. Latch Counter
Overflow
[0:8]
Burst Length Counter
Column Decoder Sense gates Addr. Latch/Predecode Decorder
LDQM UDQM
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
4Mx16 Bank1
4Mx16 Bank3
Mode Register
Test Mode
Control
Revision Jul.98
Data Input/Output Buffers
HY57V2571620
ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature Storage Temperature Voltage relative Voltage relative Short Circuit Output Current Power Dissipation Soldering TSTG VIN, VOUT TSOLDER Symbol -1.0 -1.0 Rating Unit
Note Operation above absolute maximum rating adversely affect device reliability.
OPERATING CONDITION (TA=0°C 70°C)
Parameter Power Supply Voltage Input high voltage Input voltage Symbol VDD, VDDQ -0.3 Typ. Unit Note
Note 1.All voltages referenced 2.VIH(max) acceptable 4.6V pulse width with 10ns duration. 3.VIL(max) acceptable -1.5V pulse width with 10ns duration.
OPERATING CONDITION (TA=0°C 70°C, VDD=3.3V 0.3V, VSS=0V)
Parameter input high level voltage Input timing measurement reference level voltage Input rise fall time Output timing measurement reference level Output load capacitance access time measurement Symbol Vtrip Voutref Value 2.4/0.4 Unit Note
Note Output load measure access times equivalent gates capacitor (50pF). details, refer AC/DC outputload circuit.
Revision Jul.98
HY57V2571620
CAPACITANCE (TA=25°C, f=1MHz)
Parameter Input capacitance A12, BA0, BA1, CKE, RAS, CAS, Data input output capacitance DQ15 Symbol Unit
CI/O
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250
Output
Output
50pF
50pF
Output Load Circuit
Output Load Circuit
CHARACTERISTICS 0.3V)
Parameter Input leakage current Output leakage current Output high voltage Output voltage Symbol Min. Unit Note -4mA =+4mA
Note 1.VIN 3.6V, other pins under test 2.DOUT disabled, OUT=0 3.6V
Revision Jul.98
HY57V2571620
CHARACTERISTICS (TA=0°C 70°C, VDD=3.3V 0.3V, VSS=0V)
Speed Parameter Symbol Test Condition Operating Current IDD1 IDD2P IDD2PS Burst Length=1, bank active tRAS tRAS(min),tRP tRP(min), IO=0mA VIL(max), min. VIL(max), VIH(min), VIH(min), Input signals changed time during 2clks. other pins VDD-0.2V 0.2V VIH(min), Input signals stable. VIL(max), VIL(max), VIH(min), VIH(min), Input signals changed time during 2clks. other pins VDD-0.2V 0.2V VIH(min), Input signals stable tCK(min), tRAS tRAS(min), IO=0mA banks active tRRC tRRC(min), banks active 0.2V CL=3 CL=2 -10P -10S Unit Note
Precharge Standby Current power down mode
IDD2N Precharge Standby Current power down mode IDD2NS IDD3P IDD3PS
Active Standby Current power down mode
IDD3N Active Standby Current power down mode IDD3NS
Burst Mode Operating Current Auto Refresh Current
IDD4
IDD5
Self Refresh Current
IDD6
Note 1.IDD1 depend output loading cycle rates. Specified values measured with output open. 2.Min. tRRC (Refresh cycle time) 70ns HY57V2571620TC-8/10P/10S) 80ns HY57V2571620TC-10 3.HY57V2571620TC-8/10P/10S/10 4.HY57V2571620LTC-8/10P/10S/10
Revision Jul.98
HY57V2571620
CHARACTERISTICS
Parameter Symbol System clock cycle time Clock high pulse width Clock pulse width Access time from clock Data-out hold time Data-Input setup time Data-Input hold time Address setup time Address hold time setup time hold time Command setup time Command hold time data output Z-time data output high Z-time Latency Latency Latency Latency Latency Latency tCK3 tCK2 tCHW tCLW tAC3 tAC2 tCKS tCKH tOLZ tOHZ3 tOHZ2 1000 1000 1000 1000 -10P -10S Unit Note
Note 1.Assume (input rise fall time 1ns. 2.Access times measured with input signals 1v/ns edge rate, 0.8v 2.0v
Revision Jul.98
HY57V2571620
CHARACTERISTICS
Parameter Symbol cycle time Operation Auto Refresh delay active time precharge time bank active delay delay Write command data-in delay Data-in precharge command Data-in active command data-out Hi-Z data-in mask command Precharge data output Hi-Z Power down exit time Self refresh exit time Refresh Time Latency Latency tRRC tRCD tRAS tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tPDE tSRE tREF 100K 100K 100K 100K -10P -10S Unit Note
Note command given tRRC after self refresh exit.
Revision Jul.98
HY57V2571620
DEVICE OPERATING OPTION TABLE
HY57V2571620TC-8
Latency 125MHz 100MHz 83MHz 66MHz 3CLKs 2CLKs 2CLKs 2CLKs tRCD 3CLKs 2CLKs 2CLKs 2CLKs tRAS 6CLKs 5CLKs 4CLKs 4CLKs 9CLKs 7CLKs 6CLKs 5CLKs 3CLKs 2CLKs 2CLKs 2CLKs
HY57V2571620TC-10P
Latency 100MHz 83MHz 66MHz 50MHz 2CLKs 2CLKs 2CLKs 2CLKs tRCD 2CLKs 2CLKs 2CLKs 1CLK tRAS 5CLKs 5CLKs 4CLKs 3CLKs 7CLKs 6CLKs 5CLKs 4CLKs 2CLKs 2CLKs 2CLKs 1CLK
HY57V2571620TC-10S
Latency 100MHz 83MHz 66MHz 50MHz 3CLKs 2CLKs 2CLKs 2CLKs tRCD 2CLKs 2CLKs 2CLKs 1CLK tRAS 5CLKs 5CLKs 4CLKs 3CLKs 7CLKs 6CLKs 5CLKs 4CLKs 2CLKs 2CLKs 2CLKs 1CLK
HY57V2571620TC-10
Latency 100MHz 83MHz 66MHz 50MHz 3CLKs 2CLKs 2CLKs 2CLKs tRCD 3CLKs 2CLKs 2CLKs 2CLKs tRAS 5CLKs 5CLKs 4CLKs 3CLKs 8CLKs 7CLKs 6CLKs 4CLKs 3CLKs 3CLKs 2CLKs 2CLKs
Revision Jul.98
HY57V2571620
COMMAND TRUTH TABLE
Command Mode Register Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge Banks Precharge selected Bank Burst Stop UDQM, LDQM Auto Refresh Entry Self Refresh Exit Entry Precharge power down Exit Clock Suspend Entry Exit CKEn-1 CKEn
ADDR
A10/ code
Note
Note Code Operand Code Valid, Dont care, Logic High, Logic Low, Address, Column Address.
Revision Jul.98
HY57V2571620
PACKAGE INFORMATION 400mil 54pin Thin Small Outline Package
Unit mm(Inch)
Revision Jul.98
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