WIDE RANGE Cliff Ortmeyer Claudio Adragna This application n
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DESIGN TIPS L6561 POWER FACTOR CORRECTOR
WIDE RANGE
Cliff Ortmeyer Claudio Adragna
This application note will describe some basic steps optimize design L6561 wide range voltage input (105V- 300V) while also having broad output power range (65W 105W). Initial design steps covered application note AN966. This serve supplement that application note also give example wide range demo board optimized market (110V 277V). deeper look control L6561 also found application note AN1089 "Control loop modeling L6561-based PFC".
Introduction Designing circuit with singular input voltage singular output power task that rather straight forward gives very good component values when design equations used. task becomes little more difficult when wide range needed specifications tight. This common applications such lighting where there demand good power factor >.99) less than full range nominal operating conditions. problem occurs since design must done worst case conditions which input voltage maximum output power. will see, this will diminish performance circuit when input voltage high output power low. What must done this case look closely limits L6561 external components optimize compromise where needed.
Design Tips
Multiplier Operation. Once initial design done measurements have been made, next step look operating parameters L6561 that working within full capabilities without going over linear operating range. copy table will referring shown Fig.
Figure Multiplier Characteristics
VCS(pin4) upper voltage
clamp
D97IN555A
VCOMP(pin2)
VMULT(pin3)
optimal operation device should stay linear operation multiplier. seen, there three pins that should measured worst case conditions. first with lowest input voltage (low line) highest output power. second highest input voltage (high line) lowest output power. first measured Vcomp (pin2). This output error amplifier (Figure will determine which curve will referenced when measuring other parameters Vmult. Once this established, peak voltage multiplier input (pin should measured noted. Next measure peak voltage current sense resistor (Vcs Looking graph Figure determine which curve from Vcomp voltage.
December 2000
Next, note where Vmult curve make sure that they linear operating region. operation linear region met, adjust variable that allows linear operation met. however device operating linear region allowing full range multiplier used, then increasing variables (the multiplier voltage example) help maximize full operating range multiplier. Figure Multiplier Block Diagram.
CURR.CMP
1.7V
Zero crossing dead time. Once multiplier operating parameters have been met, input voltage well input current should looked together. problem look distortion current waveform especially high line load. example seen figure
Figure Current Shape Zero Crossing with High Capacitance slow Turn-on Diode.
main reason this effect that near zero-crossings energy stored inductor very low, enough charge drain node total capacitance (basically, FET's drain-to-source capacitance inductor's parasitic intrawinding capacitance) turn boost diode turn-on speed boost diode adds problem well. result, energy exchanged between reactive components there input-to-output transfer. This seen figure minimize Coss, Rds(ON) should maximized within limits acceptable conduction losses, voltage rating should minimum that still provides adequate breakdown capability. fact, both
D97IN675
Rds(ON) high voltage imply higher Coss. Inductor parasitic capacitance reduced minimizing number winding layers. Adding layer tape between winding layers reduce capacitance considerably. slotted bobbin also very effective. Also optimizing diode offer positive contribution. minimum junction capacitance will somewhat beneficial, even though this minor contribution total drain capacitance. major improvement offered diode with well controlled resistivity (such Turboswitch series) which lower peak forward voltage, that actually turns just volts above output voltage. example improvement given optimizing diode shown figure Figure Current Shape Zero Crossing with Lower Capacitance Turboswitch Diode
Input capacitance (EMI filtering). Another source error input filter. Since voltage output from rectifier bridge used reference current follow, distortions this waveform will translate into distortions current waveform, hence lower power factor greater THD. cause this large high frequency filter capacitor being used after bridge. high value capacitor filter rectified voltage cause voltage deviate from rectified sinusoid even reach zero light load. This seen figure
Figure Non-discontinuous Voltage Error
obvious improving this lower high frequency capacitor value. Care must taken lower capacitance such that effectiveness filter front diode bridge) degraded pass regulatory requirements. lowering that capacitance, filter capacitor front diode bridge need increased.
Switching frequency. other method using full dynamic range L6561 reduce minimum switching frequency FET. using lowest possible switching frequency L6561, wider range
switching frequencies available used. This helps minimize effects internal propagation delay well offset current sense comparator. this current will track voltage waveform better, particular near zero-crossings. This, however, must weighed against size increase inductor because lower switching frequency implies larger inductance value. When determining lowest frequency, must noted that switching below 15kHz recommended since this interfere with internal starter. special construction technique inductor offer optimum compromise: that allows inductance value minimize inductor size and, same time, have lower switching frequency near zero-crossings. price that additional step inductor manufacturing flow. so-called "step-gap core" technique: centre half ferrite core ground that thickness step change, shown fig. inductor current small thinner part dictates high inductance value (L1). current increases above certain value (IL1), thinner part will progressively saturate inductance will drop value (L2<L1) determined thicker part (lg). non-linearity deliberately introduced that, given switching frequency rectified sinusoid where current high (that given L=L2), switching frequency near zero-crossings where current will high with linear inductor. Figure Step-gap ferrite grinding effect inductance value
"step-gap"
core half
appropriate height breadth ferrite step (both them determine IL1) given application will found empirically.
Wide Range Example Circuit example circuit designed with varying voltage input 110V 277V output power 105W. techniques this paper (except step-gap core) were used help bring power factor into acceptable levels. example schematic associated filter shown below along with measured results. Figure Example Schematic
STTA106 998K
Vo=450V Po=105W 47µF 250V
240K BRIDGE 1N4007 FUSE 4A/250V (105V 305V)
1N4150 1N5248B
12nF
33nF 630V
1.24M
L6561
22µF 10nF
STP6NB50 47µF 250V
5.6K
D99IN1098
120K 499K, 620K
TRANSFORMER core THOMSON-CSF B1ET2910A (ETD 10mm) EQUIVALENT (OREGA 473201A8) primary Litz wire 0.2mm secondary (0.15mm) 1.25mm total primary inductance 0.8mH
Figure Filter
LINE
EARTH
D97IN680
Table Example Schematic Results
[VAC) Vout Iout [mA] 0.998 0.998 0.995 0.993 0.999 0.999 0.997 0.994 11.0 11.2 66.4 65.8 65.0 65.0 115.8 114.7 111.0 111.0 Pout 61.0 61.0 61.0 61.0 106.5 106.5 106.5 106.5 Efficiency 91.9 92.7 93.9 93.9 92.0 92.9 96.0 96.0
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