John Pritiskutch Brett Hanson ABSTRACT This second installment tw

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John Pritiskutch Brett Hanson ABSTRACT This second installment tw

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RELATE LDMOS DEVICE PARAMETERS PERFORMANCE
John Pritiskutch Brett Hanson
ABSTRACT This second installment two-part paper series LDMOS technology (see Understanding LDMOS Device Fundamentals, AN1226) will explain LDMOS circuit-level performance through intrinsic device characteristics. Understanding current laterally diffused Metal-Oxide-Semiconductor (LDMOS) technology necessary optimally these devices high-power circuitry. circuit designers must come understanding relationship between circuit performance device characteristics beyond first-order approximations. These higher-order device relationships offer insight into many common device parameters their interdependencies and, more important, enable design engineer monitor semiconductor manufacture process more effectively. general, LDMOS devices field-effect transistors (MOSFETs) channel primary importance. channel inversion layer created within body device that electrically connects source drain, described first part this series. channel dimensions doping determine forward transconductance contribute body-related capacitances that ultimately influence power gain frequency response. body-doping profile critical device ruggedness reliability. Since introduction LDMOS devices high-voltage commercial applications device dimensions have evolved from supermicron submicron only short years. This progress indicative future LDMOS generations should noted that reduction device size below micron necessarily followed traditional scaling laws. Specification sheets MOSFETs include many parameters that will explained context circuit design performance criteria. order which these device parameters presented here indicative relative importance. BREAKDOWN VOLTAGE. saturated-drain-source breakdown voltage DSS) MOSFET device specified particular value current with drain biased gate, well source, shorted. BVDSS take many forms represented Fig. which shows curve tracer displays LDMOS breakdown. BVDSS curve have soft breakdown with multiple breaks curve which indicative non-uniformities stress within inter-digitated cell structure. Figure shows curve with characteristics that typical device exhibiting punch-through improper body-doping profile. There four significant areas this curve low, mid, high breakdown drain-voltage regions which reflect leakage, punch-through, space-charge-limited current avalanche current respectively. Figure also shows curve with very sharp break where current suddenly increases. There significant regions this curve pre-breakdown post-breakdown. Prior breakdown, leakage current exists that could from many sources, such normal p-type, n-type (pn) junction leakage recombination generation carriers
July 2000
AN1228 APPLICATION NOTE quasi-neutral region junction. breakdown-voltage regime avalanching carriers electric field being greater than critical electric field (approximately 1x105 V/cm). Under these conditions electron accelerated electric field. elastic inelastic scattering this electron acceleration generate more than carrier thus multiplication scheme transpires. Figure Typical Breakdown Curves LDMOS Transistor
Operating near BVDSS reliability risk since device sustains high-stress conditions. Under these conditions high-energy carriers alter device characteristics creating, filling emptying interface traps. LDMOS device, this avalanche condition exists under near gate, carriers penetrate gate oxide well alter off-state characteristics. Typical problems this avalanching include threshold-voltage drift increased gate leakage. While evaluating devices this parameter large variations indicative inconsistencies device fabrication. circuit design general rule thumb states that BVDSS should times operating voltage order support variations voltage. saturated gate-source current (IGSS) leakage current generated when gate biased specified voltage while maintaining other terminals ground. IGSS many factors that related integrity gate oxide surrounding regions. Ideally this value would zero voltage levels that less than voltage required reach dielectric strength gate oxide. However, practice this condition achieved omnipresence impurities that exist wafer fabs vagaries oxide growth with temperature profiles used. IGSS used evaluate reliability this integral component MOSFET. Increase this parameter with particular device stress used extrapolate mean time failure (MTTF) gate oxide. Overstressing gate either periodically with statically with also cause increase this parameter thus degrades device performance with respect power gain. Other considerations gate oxide include careful electrostatic-discharge (ESD) precautions since gate oxide easily damaged. IDSS current produced when drain biased specific voltage while maintaining source gate contacts ground. IDSS many component contributions. Normal junction leakage reliability problem long maintained specified value does continue increase indefinitely. Other sources IDSS include minority carrier injection from source carriers overcoming energy barrier resulting from surface band bending also from subcritical avalanching caused high electric fields non-ideal body well Laterally-Diffused-Drain (LDD) doping profile.
AN1228 APPLICATION NOTE reverse transfer capacitance feedback capacitance from device drain gate that limits device high-frequency gain. This capacitance function many factors including gate area, gate-drain metallurgical over-lap well dynamics drain-source depletion spread function drain bias. three regions capacitance-voltage (CV) characteristics figure indicative device formation. Figure Reverse Transfer Capacitance Supply Voltage
(pF)
VOLTAGE (VOLTS)
LDMOS devices zero-volt capacitance mainly gate-oxide capacitance (Cox). initial decrease bias applied formation depletion capacitance, dictated doping profile that series with important that slope this initial decrease large approaches final value some voltage near saturated drain-source voltage DS(sat)) linearity considerations. gate-source capacitance (Cgs capacitance formed between gate ground plane. LDMOS source, body, epitaxial layer substrate form referenced ground plane. charge formed application voltage gate dependent area gate, doping body metallurgical gate-source overlap. This capacitance critical since largest component input capacitance constrains device switching speed which comparable limiting maximum frequency operation. capacitance formed between drain ground plane where referenced ground plane formed LDMOS source, body, epitaxial layer substrate. charge formed application voltage drain dependent area heavily doped drain, concentration epitaxial layer and, lesser extent, body doping. This capacitance critical since largest component output capacitance influences device efficiency. Device data sheets identify these primary capacitances form Crss Ciss, Coss. Capacitance Crss simply gate-drain capacitance, Cgd, whereas Ciss parallel combination Cgd. Capacitance parallel combination forward transconductance (gfs) identifies differential drain current differential gate voltage. There three major regions function versus Vgs. increases from mid-range values expands until linear region reached. Beyond this region, high voltages applied, compresses. Class operation peak device current should remain below
AN1228 APPLICATION NOTE compression region maximum linearity. specification usually measured linear region shown device data sheets. DEFINING RUGGEDNESS. ruggedness load-mismatch tolerance LDMOS technology defined ways. first that after being subjected extreme load conditions there shall degradation device performance output power. more-stringent criterion would that there would degradation device parameters such shift threshold voltage, increase leakage current subtle increase Rds(on). Changes these parameters indication long-term reliability problems. overall ruggedness device when tested extreme load conditions related amount localized thermal stress, ability sustain high levels drain-source current BVdss maxi-mum current capability intensity avalanching occurring under near gate structure. CONCLUSION sagacious engineer will take heed previously defined parameters their relationship circuit performance reliability. These parameters very helpful when identifying problems early design stage. Other parameters, such substrate current, even more sensitive always accessible design engineer. implications instability these parameters manifold ultimately expressed from sub-atomic device physics regime circuit performance. This paper focused aspects that design engineer would consider tractable. better understanding relationship these basic MOSFET parameters circuit performance, designers more accurately create effective amplifiers other active circuits.
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specification mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo trademark STMicroelectronics 2000 STMicroelectronics Printed Italy rights reserved
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John Pritiskutch Brett Hanson ABSTRACT This second installment tw

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