FPGA Configuration Basics Xilinx Specific Typical Implementation Solut

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FPGA Configuration Basics Xilinx Specific Typical Implementation Solut

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Configuring FPGAs with FLASH+PSD
FPGA Configuration Basics Xilinx Specific Typical Implementation Solution
Summary Reference
There several well-documented methods configuring Field Programmable Gate Arrays (FPGAs). Each method involves transferring configuration data from some sort NonVolatile Memory (NVM) FPGA. There usually many modes doing transfer, including stand alone (Master Mode), conjunction with embedded microcontroller (Peripheral Slave Mode). method chosen depends many factors specific particular application, such
Speed configuration Number pins available Microcontroller configuration Simplicity design Multiple configuration files Board space Cost.
Invariably, cost usually main factor determining method chosen.
EasyFLASHPSD8XXF devices members family Flash memory-based peripherals with embedded systems. These programmable system devices (PSDs) consist memory, logic, I/O. When coupled with low-cost microcontroller (MCU), forms complete embedded Flash memory system that 100% In-System Programmable (ISP).
This application note shows benefits using PSD8XXF provide necessary functions configuring FPGA. PSD8XXF devices only extremely cost compared other solutions, also provide inherent benefits associated with Flash-based PSDs, such
In-system programmable (re)configurable Additional memory (Flash, optional SRAM, optional secondary Flash memory EEPROM) power consumption Integration many parts, including memory, programmable logic, decode logic, security Flexibility Improved reliability Reduced number components Board space saving
April 2002
AN1424 APPLICATION NOTE
Reduced development time.
FPGA CONFIGURATION BASICS Each manufacturer FPGAs their unique configuration format. Usually, configuration made internal data structure containing preamble bits, length count, data frame size, configuration normally generated manufacturer's development software. Although this note focuses specifically Xilinx families FPGAs, general concepts presented applicable configurable FPGAs. Xilinx Specific There least different programming modes available, which user selectable three mode pins FPGA: programming modes include: Mode 0-Master Serial Mode 1-Master Parallel (Address 0000 Mode 2-Slave Parallel (Express Mode-XC4000EX XC5200 families only) Mode 3-Master Parallel (Address =FFFF down) Mode 4-Reserved Mode 5-Peripheral Parallel Mode 6-Reserved Mode 7-Slave Serial complete description these modes, refer Xilinx's data sheets. Typical Implementation typical application using 8031 microcontroller connected external Kbyte Flash, octal latch, FPGA configured Slave Serial Mode, shown Figure Both program code FPGA configuration code stored Flash. This simplest method configuring FPGA since simply bit-bangs data into Figure Typical Implementation FPGA Configuration Slave Serial Mode
EA/VP RESET INT0 INT1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 80C31
7414
RESET
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 ALE/P PSEN
74ALS373
Reset INIT Done/Prog~ CCLK XC3xxx
29F010
AI06684
AN1424 APPLICATION NOTE
Solution Although solution above simple, Flash memory cannot programmed updated after soldered board. Using cost PSD8XXF device provides optimal solution configurable FPGA applications. PSD8XXF contains needed memory store system program code, FPGA program code, FPGA configuration data. memory programmed/ updated over JTAG channel time. Figure shows example PSD8XXF might interface FPGA configured Slave Serial Mode. Figure FPGA Configuration Circuit using PSD8XXF
EA/VP RESET INT0 INT1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 80C31
7414
RESET
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 PSEN ALE/P
/PSEN
ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 CNTL1 CNTL0 CNTL2
Reset INIT Done/Prog~ CCLK XC3xxx
/RESET
7414
(TMS) (TCK) (VSTBY) (TSTAT) (TERR) (TDI) RESET (TDO)
PSD813F5
JTAG Header
AI06685
Chip selects internal components external devices generated PSD's Decode (DPLD). address demultiplexing latch shown Figure (U2) absorbed programmable interface PSD. also replaces microcontroller ports lost when accessing external memory, which used general purpose provide control signals needed interface FPGA. Since provides plenty memory, could used store multiple configurations FPGA. These configurations could changed (re-programmed) in-system when necessary using JTAG port. flexibility PSD8XXF ports allow them configured many functions, including:
Standard Chip select outputs Latched address outputs Additional address inputs Registered I/O.
circuit designer freedom select whichever FPGA mode best suited particular application. Another option designer would Peripheral Mode Express mode. this case, PSD8XXF ports would configured 8-bit parallel data port. Some other port pins could then used provide additional control signals necessary that particular mode. Also note that Output Micro Cells connected form loadable shift register that could used load FPGAs parallel. Application Note more information CPLD usage.
AN1424 APPLICATION NOTE
SUMMARY PSD8XXF family ideal solution embedded control applications that configurable FPGAs because multiple configurations stored updated necessary using JTAG port. Also, with PSD, have four multi-purpose ports that used conjunction with MCU, FPGA, other external devices form complete solution.
REFERENCES more information PSD8XXF family uses, visit site www.st.com/psm following documents:
PSD813F Family Data Sheet
Application Note AN1153- JTAG Information-PSD8XXF detailed JTAG channel Application Note AN1171-CPLD Primer-PSD8XXF details CPLD pins Application Note AN1154-PSD813F1/80C31 Design Tutorial details I/O, GPLD, logic simulation, PSDsoft features.
AN1424 APPLICATION NOTE
Table Document Revision History
Date Sep-1999 03-Jan-2002 12-Apr-2002 Rev. Description Revision Document written (AN065) format Front page, back pages, format, added file References Waferscale, PSDsoft 2000 updated PSDsoft Express Document converted format
AN1424 APPLICATION NOTE
current information products, please consult pages world wide web: www.st.com/psm have questions suggestions concerning matters raised this document, please send them following electronic mail addresses:
apps.psd@st.com ask.memory@st.com
(for application support) (for general enquiries)
Please remember include your name, company, location, telephone number number.
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics other names property their respective owners 2002 STMicroelectronics Rights Reserved STMicroelectronics group companies Australia Brazil Canada China Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States.

FPGA Configuration Basics Xilinx Specific Typical Implementation Solut

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