This tutorial takes step-by-step through development cycle M88x3Fxx ba
|
|
|
Top Searches for this datasheet
8031 FLASH+PSD Design Tutorial
This tutorial takes step-by-step through development cycle M88x3Fxx based design, from design entry, programming device. first part this tutorial shows M8813F1x used conjunction with handful other implement automatic gain control (AGC) design. tutorial also shows this design would implemented using discrete part solution, Appendix summarizes various benefits using M88x3Fxx device over discrete solution. members FLASH+PSD family programmable system devices Flash-based peripherals with embedded microcontrollers (MCUs), In-System-Programmable (ISP). These PSDs designed interface easily with variety 8-bit MCUs, provide them with memory, logic, I/O. Embedded designs typically bound cost, size, power consumption. market products using embedded MCUs extremely competitive. Time-to-market quality features-per-dollar define success. using FLASH+PSD device, will reduce your cost, time-to-market, power consumption, board space, design complexity, chip count. read this document, will learn FLASH+PSD enhance your MCU, meet needs Flash memory, EEPROM, SRAM, configurable pins, programmable logic (both sequential combinatorial), decoded address space, address expansion, backup power, code integrity, code security, ISP. these features found cost-effective M8813F1x device, allow cost, minimal feature, ROM-less device. addition giving step-by-step design entry tutorial, this document usefully highlights three aspects FLASH+PSD solution: using concurrent memory JTAG MicroCell technology logic simulation capabilities PSDsilosIII typical design with Flash memory consists
main Flash memory boot PROM SRAM implement download main Flash memory over UART channel, some other communication link.
systems that SRAM ISP, Flash-programming algorithm must first downloaded SRAM then executes from SRAM during ISP. power interruption system glitches that occur will corrupt system. Therefore, boot PROM necessity applications that demand high system reliability. However, boot PROM adds cost system, difficult update once service. Flashbased PSDs address these concerns combine elements necessary enable download easily main Flash memory, boot memory, while in-system.
January 2000
1/83
AN1154 APPLICATION NOTE
method just described requires participation. FLASH+PSD also offers another method, which uses JTAG interface, requires participation. This means that completely blank soldered into place, entire chip programmed, in-system, using ST's JTAG FlashLink cable PSDsoft development software. This powerful feature FLASH+PSD that allows easy updates field. Typically, adding peripheral memory space involves adding circuitry decode address lines, latch data lines, handle timing. FLASH+PSD device used, address, data, control signals already routed processed inside PSD, this hardware overhead required. MicroCells take advantage this, allow designer build logic peripherals inside efficient flexible manner. This tutorial compares MicroCell design with equivalent functional design using Altera EPM7064S CPLD device, thereby emphasizing efficiency approach. M88x3Fxx output MicroCells (OMCs) input MicroCells (IMCs). Each MicroCell occupies memory location address space, connected data bus. ability load flip-flops OMCs, read them back, useful such applications loadable counters, shift registers, other system logic. IMCs latch external inputs, read microcontroller. IMCs also useful when implementing handshake communication logic with outside source. provides complete chip-level Verilog-HDL models devices with PSDsilosIII simulator. These models used conjunction with user-defined stimulus file simulate functionality PSD. PSDsilosIII also comes with Waveform Editor/Viewer Watch window (for stepping through simulation) that used conjunction with stimulus file. Most PSD's status control signals, well user-defined logic CPLD, available with Waveform Editor/Viewer Watch window. Thus, user define MCU-level tasks, such read write, that used external chip-level stimuli PSD, results stimuli viewed using Waveform Editor/Viewer Watch window PSDsilosIII. utility featured PSDsoft version 5.X. This utility automatically generates ANSI-C code functions, used with user's choice cross-compilers. Design Example design that been chosen, example, Figure piece hardware with closedloop Automatic Gain Control (AGC). This analog receiver section, which Programmable Gain Amplifier (PGA) control signal level that output though envelope detection circuit. gain must adjusted real-time keep constant signal level envelope detection output. Analog-to-Digital Converter (ADC) monitors this output. When function works properly, constant signal level output from receiver, which used other analog digital circuitry signal processing.
2/83
AN1154 APPLICATION NOTE
Figure Block Diagram Automatic Gain Control Circuit
Desired Level 80C31 Interrupt Boost Trim State Machine
Amplifier Gain Control Setting
Closed Loop
Converter
Modulated Signal
PreAmp
Filter
Base Band Signal Envelope
Receiver
AI03141
could used perform this real-time gain adjustment, this would leave with little execution time other tasks. highly desirable free off-loading these repetitive tasks dedicated hardware. function moved into state machine, implemented using programmable logic, shown Figure this configuration, first loads state machine with desired signal level, starts running, then gets with other tasks. Most time, state machine works autonomously, reading outputs comparing measured value with desired value. state machine only needs interrupt when signal drifted from desired level. Along with Interrupt line, provides signals: `Trim' `Boost'. signal level from receiver high, interrupt accompanied `Trim', writes appropriate value decrement gain. Likewise, signal level low, interrupt from state machine accompanied `Boost'. This tutorial shows implement this function different ways: discrete solution (using individual devices programmable logic, memory, etc.), shown Figure integrated solution, shown Figure addition function, other features that have been implemented include: Real-Time-Clock (RTC), In-System Programmability (ISP), miscellaneous signals. Please refer Appendix information related system memory mapping, issues using UART, memory paging considerations.
3/83
4/83
EPM7064S
RESET RESET/ RTC_INTR/ AGC_INTR/ INT0 INT1 EEPROM_OE/ EEPROM_CS/ T28C256
Pushbutton With Debounce
Reset
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
I/O0 1/01 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
7414
EEPROM_A EEPROM_A
TRIM BOOST SH_CS/ SH_OE/ FLASH_CS/ FLASH_OE/ PSEN/ I/OE1 I/OE2/GCLK2
P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7
SH_A14 SH_A15 SH_A16
FLASH_A FLASH_A FLASH_A
EEPROM
128K FLASH
RTC_CS/
AN1154 APPLICATION NOTE
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
29F010
PSEN LE/P
PSEN/
80C31
CPLD
CONTROL0 CONTROL1 CONTROL2 I/GCLR I/GClk1 M_CS/ M_OE/ DC_OUT7 DC_OUT6 DC_OUT5 DC_OUT4 CONV_STA RESET/ Clock AGC_INT/ RTC_CS/
EEPROM_A EEPROM_A EEPROM_OE/ EEPROM_CS/
INTR
DP8572A
RTC_INTR/
JTAG Connector
RS232 PORT
32.768
Figure Block Diagram Discrete Solution
System Clock
Control0 Control1 Control2
BOOST TRIM _Din2 _Din1 _Din0
UUUU OOOO CCCC DDDD AAAA SRAM_CS/ SRAM_OE/ LH5116 I/O1 1/02 I/O3 I/O4 1/O5 1/O6 I/O7 I/O8
SRAM
SRAM_Vcc
NTENNA (Receiver)
DDDDDDDD
PreAmp Filter Vout
Envelope Detector
ELOPE_OUT
COMPARATOR 7414 LITHIUM BATTERY
AI03139
AN1154 APPLICATION NOTE
This 80C31 application that 128K Flash memory, battery-backed SRAM, EEPROM, real-time clock (RTC), 8-bit analog-to-digital converter (ADC), JTAG interface, EPM7064S CPLD, analog receiver circuit (including PGA). discrete solution, Figure four extra devices required. M8813F1x solution, Figure Flash memory, EEPROM, SRAM, CPLD, battery backup circuitry combined M8813F1x device. following notes made regarding discrete solution (Figure
80C31 using external memory since internal program data storage sufficient. result, Port Port sacrificed address data. EPM7064SLC84-5 CPLD needed address decoding, control logic, implementation paging/segmentation scheme Flash memory EEPROM, interfacing ADC. Please refer Appendix complete design listing 29F010 Flash memory contains 128K bits program memory. Notice that address lines A14A16 driven CPLD support additional address space. A128C256 EEPROM contains bits boot memory. This allows concurrent programming Flash memory. Address lines A13-A14 driven CPLD support additional address space. DP8572A RTC, programmable Real-time Clock, used time-stamp various data received MCU. LH5116-2K SRAM configured with battery backup protection. generic 8-bit converts target signal envelope into digital value. This controlled CPLD. receiver circuit consists collection components, including: pre-amplifier, mixer, local oscillator (LO), PGA, envelope detector circuit. circuit takes signal from antenna, input, outputs signal envelop. 7414 inverter with hysteresis (U7B) used provide stable reset signal (U1). part battery backup circuit SRAM. generic OPAMP comparator part battery backup circuit SRAM. When falls below battery voltage, circuit switches over powering SRAM from battery.
integrated design, Figure compared discrete design, Figure memory (U3, U6), battery backup circuit (U9A U10) Figure incorporated into M8813F1x (U2) Figure Also, functions handled CPLD Figure implemented PSD's CPLD. pins individually configured match functions implemented original design. Using JTAG, entire M8813F1x device programmed. Also, JTAG pins multiplexed with other I/O. These JTAG features beyond capabilities EPM7064S.
5/83
6/83
INTR DP8572A RTC_INT/
RTC_CS/
EA/V RESET _DIN0 _DIN1 _DIN2 RESET AGC_ INT/ RTC_INT/ INT0 INT1 ADC_OUT4 ADC_OUT5 ADC_OUT6 ADC_OUT7
32.768
AN1154 APPLICATION NOTE
Pushbutton With Debounce
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 CONTROL0 CONTROL1 CONTROL2
Control0 Control1 Control2
Reset
7414 TRIM BOOST PSEN/ CNTL1 CNTL0 CNTL2 TMS; GC_INT/ TCK; START_CONV/
7414
P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7
ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 PSEN ALE/P CLKIN RTC_CS/ RESET M8813F1x Battery RESET/ PSEN/ 80C31
74HC126 INT/ CONV_START/ TSTA TRIM TERR/; BOOST JEN/
System_ Clock
Figure Block Diagram Integrated Design
(TMS) (TCK) (VSTBY (TSTAT) (TERR) (TDI) (TDO)
OOOO JEN/4
RS232 PORT
(Receiver)
ANTENNA
JTAG Connector Filter
Signal Envelope
PreAmp Envelope Detector
Applic ation
AI03140
AN1154 APPLICATION NOTE
Matching Functions M8813F1x mapping functional areas, original design, into M8813F1x shown Table 80C31, running MHz, tAVIV (time between address valid instruction valid) M8813F1x-15 (the part) selected meet 80C31 access time requirement. Table Discrete Solution Compared M8813F1x Solution
Functional Area Design Example with Discrete Components KByte Flash Memory Memory KByte EEPROM KByte SRAM Memory Paging/Segmentation, Control Extra logic drive address lines, output enables, chip selects Flash EEPROM Decoder (EPM7064S) Address latch logic CPLD PLD/Control/Demux Various registers used hold data control information used external devices Latched data inputs outputs CPLD Combinatorial outputs CPLD Automatic switch battery backup Matching M8813F1x Function Same Same Same Automatically taken care internally DPLD, page register, register, prioritized memory access. DPLD (Decoding PLD) Port latched address mode (A7-A0)
Output MicroCell each register mode feature
same Built-in comparator automatically switches battery power when system voltage drops below battery voltage (VSTBY) Utilizes standard JTAG non-standard extensions speed programming); JTAG port multiplexed with other I/O, memory logic within JTAG port.
Supervisory/JTAG
Limited JTAG interface with multiplexing JTAG port available, JTAG memory available
7/83
AN1154 APPLICATION NOTE
FLASH+PSD FUNCTIONAL BLOCKS M88x3Fxx provides five system-level functional blocks, allows user define configure these blocks meet design specification. Interface Interface adapts address, data, control lines particular PSD. Choices include multiplexed non-multiplexed address/data bus, associated control/handshake signals. PLDs (Decode memory registers, General logic) DPLD generates internal chip selects FLASH+PSD Flash memory, EEPROM, SRAM, Control registers Ports, Peripheral mode, MicroCells. CPLD implements general logical functions, such state machines, shift registers, counters, combinatorial logic. Both PLDs based Flash memory technology. Ports M88x3Fxx four ports: Ports These ports have several modes operation selected within PSDsoft during design entry, firmware run-time. Modes that defined PSDsoft implemented with Non-Volatile Memory (NVM) configuration bits that cannot altered unless device reprogrammed. remaining available port operational modes determined writing control registers. Please Application Note AN1x55 more details. Memory M8813F1x KBytes Flash memory, KBytes EEPROM, KBytes battery-backed SRAM. these memories operate concurrently. That that, while more) type memory being written erased read, still fetching program code from another. These memory blocks placed system address space using PSDsoft development software. FLASH+PSD also offers some run-time features that used alter system memory fly, which useful memory paging, ISP. JTAG interface FLASH+PSD family includes JTAG channel In-System Programming (ISP). This function extension typical JTAG boundary-scan function. implementation JTAGISC (In-System Configuration) specification that becoming industry standard. entire device configured programmed while soldered product. completely blank before programming because JTAG interface needs assistance from MCU. enhanced standard four-wire IEEE 1149.1 JTAG interface making available additional handshake lines speed programming. JTAG interface, additional handshake lines, defined using PSDsoft. Also, some control over JTAG interface run-time.
8/83
AN1154 APPLICATION NOTE
PSDSOFT DEVELOPMENT TOOLS PSDsoft ST's integrated system development software tool, which runs Windows Windows environments. PSDsoft supports configuration functional blocks, described previous sections. PSDsoft consists following major modules:
PSDabel Configuration Fitter Simulator Programmer Code Generator
PSDsoft design process devices follows flow shown Figure PSDabel PSDabel MINC's ABEL engine core (formerly DATA ABEL). PSDabel environment provides editor create/edit .abl file that used define chip select logic, general-purpose logic, configuration parameters. Template files provided many combinations. When file compiled, logic synthesized, files created passed PSDsoft fitting utility. Configuration This utility used specify interface type, special assignments, particular internal functions. output this module .glc configuration file, which also used PSDsoft Fitter. Fitter Fitter main functions: Fitter Address Translator. Fitter accepts input from PSDabel Configuration, synthesizes this user logic configuration, fits design silicon. Address Translator process allows user firmware from crosscompiler Intel S-Record format) into blocks within PSD. result, firmware merged with logic configuration definition PSD. output Address Translator .obj file that used programmer program device. This .obj file also used program FLASH+PSD using JTAG FlashLink cable. .obj file includes chip configuration information, fuse-map, firmware. Simulator ST's version SIMUCAD's SILOSIII simulation software provides functional chip-level simulation devices. PSDsoft automatically creates files input simulator. These files convey relevant design information simulator. result, user only create stimulus file since signals node names taken from .abl file. Programmer Programmer interface MagicProIII®, PSDpro, PEP300, FlashLink programming devices. accepts .obj file input, allows viewing editing .obj file, programs device. Code Generation This feature PSDsoft that automatically generates code functions headers controlling Flash devices. These functions headers ANSI-C compatible. generated files
9/83
AN1154 APPLICATION NOTE
edited suit particular application, then compiled linked with rest code. Afterwards, linker output cross-compiler (usually Intel Motorola S-record format) merged with configuration file device Address Translate utility PSDsoft. functions headers provided PSDsoft, cover operations such
Flash memory program erase algorithms EEPROM program algorithms control definition memory management power management.
DESIGN FLOW This section describes design flow project, from initial entering design, PSDabel, programming device, simulation. Figure shows PSDsoft Design Flow utility. This first window appear after invoke PSDsoft. double clicking each box, associated process initiated. While this convenient method navigate through steps, this tutorial shows step through process using menus tool-bars since this approach less obvious. section, starting page after next, takes step-by-step through tutorial design. Figure PSDsoft Design Flow
AI03314
10/83
AN1154 APPLICATION NOTE
PSDsoft Program Flow high level steps design follows: Create open project, after entry into PSDsoft. creating project, specify project name, directory path, device family, part number, provide small description design desired. Select design template (project.abl file), modify this template your design. PSDabel edit, compile, optimize project.abl file. Perform ABEL simulation desired. will need create necessary test vectors, place them PSDabel file. successful PSDabel compile operation generates optimized file project.tt2) Fitter. Configure device using Configuration. This generates project.glc file Fitter. design using Fitter. Fitter's input files obtained from PSDabel Configuration. Fitter generates project.fob file that passed Address Translator. Fitter also generates fuse-map files, project.afu project.pfu Simulator. After successful fit, possible skip step (simulation), desired, since PSDsilosIII used before after firmware merged with configuration. Generate code, desired. Edit this code suit your particular application. Then, compile link with your other application code. Your cross-compiler will output Intel Motorola Srecord file containing firmware. Perform address translation. Address Translator combines firmware file project.fob file into project.obj file. This project.obj file includes firmware, fuse-map, configuration bits. Verify design using Simulator. Chip level simulation based user's Verilog stimulus file (project.stl) fuse-map files from Fitter. must create project.stl file. However, PSDsoft creates files used with simulator that allow same names that appear your project.abl file, various reserved names. PSDsoft download project.obj file MagicProIII®, PSDpro, FlashLink JTAG programmer program device. compatible third party programmer also used. Contact representative near list compatible programmers.
11/83
AN1154 APPLICATION NOTE
FLASH+PSD TUTORIAL EXAMPLE This section uses tutorial design example illustrate steps involved implementing functionality discussed earlier. files required, which were generated tutorial design, found directory. this point, wish start PSDsoft program, that follow along with tutorial example. Managing Project Each project have working directory, which files generated PSDsoft reside. Once specify project name, PSDsoft passes working directory pertinent information other functional modules. following sections, will guided through full sample design process, windows displayed help follow example. Start PSDsoft. PSDsoft dialog pops (Figure enquiring whether want open existing project, create one. Select "Open existing project", click Figure PSDsoft Dialog
AI03143
leave PSDsoft without closing project were working will automatically reopen when next PSDsoft. PSDsoft dialog does appear, pull down Project menu select Open Project). Either way, "Open Project" dialog appears, shown Figure Figure Open Project Dialog
AI03144
12/83
AN1154 APPLICATION NOTE
Click Browse button, which brings "Open" dialog box, shown Figure directory, select tutor8XX.ini file, click Open button (this closes "Open" dialog box). Figure Open Project Open Dialog
AI03145
Click button (this closes "Open Project" dialog box).
13/83
AN1154 APPLICATION NOTE
PSDabel File detailed information PSDabel, relates FLASH+PSD, please read comments file tutor8XX.abl Appendix Also, refer ST's Application Note AN1171 PSDsoft PSDabel-HDL Reference Manual. more information system memory this tutorial design, Appendix open tutor8XX.abl design file, shown Figure click View>Design File, click "Design Entry" button tool bar, click "Design Entry" design flow window. Figure Design File
AI03146
14/83
AN1154 APPLICATION NOTE
Compiling Tutor Design compile tutor8XX.abl file, take following steps: Click Options menu. This brings "Options" dialog box, with "Compile Options" selected. Click each options, read description "Description" feel what each option will Then options, shown Figure with Standard Listing selected under "Listing options" Retain redundancy checked. better description various options available, please refer PSDabel-HDL Reference Manual. Figure ABEL Compiler Options
AI03147
Select "Optimization Options" tab, options, shown Figure Default should only item selected.
15/83
AN1154 APPLICATION NOTE
Figure ABEL Compiler Options Optimization Options
AI03148
Click button when have finished setting options. Click Compile->Compile, shown Figure click "Compile" button tool bar.
16/83
AN1154 APPLICATION NOTE
Figure Compile->Compile
AI03149
PSDabel compiler generates error file- tutor8XX.ERR (even errors present), writes file. compiler also generates output file, tutor8XX.tt2, which used PSDsoft fitting, optimized, based reduction algorithm specified "Optimization Options" under Options menu. After compilation, display optimized logic equations that will used Fitter pulling down VIEW menu selecting Compiled Equations, shown Figure This opens tutor8XX.eq2 file. Figure View->Compiled Equations
AI03150
17/83
AN1154 APPLICATION NOTE
Simulating Your Design Using ABEL Simulation very simplistic functional simulation blocks that make using simulator that included with PSDabel. important note that only functions that generated within .abl file simulated using test vectors file. chip-level functional simulation, must have version PSDsoft that includes PSDsilosIII simulation software. simulator that comes with PSDabel, take following steps: Click Options menu, shown Figure which brings "Options" dialog box. Figure Options Dialog
AI03151
Click "Simulator Options" tab, window, shown Figure under "Format", choose Table format. Ensure that X-value Z-value selected their respective boxes, that Brief trace selected "Trace" box. "Register" box, select Register powerup make sure that "Use .TMV file" checked. Click button save your changes.
18/83
AN1154 APPLICATION NOTE
Figure ABEL Compiler Simulation Options
AI03152
select Simulation Results View menu, PSDabel will automatically start simulation process, display simulation results based logic equations test vectors .abl file, shown Figure
19/83
AN1154 APPLICATION NOTE
Figure Simulation Results
AI03153
PSDsoft Configuration FLASH+PSD programmable interface, able interface directly many microcontrollers. Using Configuration, specify interface have chosen your design. also configure functions specific device using. This tutorial design based Intel 80C31 microcontroller, which 8-bit multiplexed with PSEN control signals, active-high level address latch enable (ALE). perform configuration, take following steps: Pull down PSDsoft menu main PSDsoft window choose Configuration, click "Configuration" button click "Device Config" "PSDsoft Design Flow" window. dialog opens entitled "The Global Configuration", shown Figure Make sure "MCU Configuration" selected. global configuration shown Figure Ensure 8-Bit selected under "Data Width", selected under "Address/Data Mode", High selected under "Address Latch/Strobe Setup", "Enable Chip-Select Input (CSI)" checked, PSEN selected under "Control Setting", Data Space selected under "Flash", Program Space checked under "EEPROM". This arrangement program data space allows boot from EEPROM program space, download Flash memory data space, needed. Afterwards, override this arrangement example, Flash memory needs become part program space. This done writing register.
20/83
AN1154 APPLICATION NOTE
Figure Configuration
AI03154
Click "Other Configuration" tab, shown Figure ensure that Enable Standby Voltage Input (PC2) checked under "Standby Voltage", Edge selected under "Mode Loading MicroCell MCU", other boxes unchecked.
21/83
AN1154 APPLICATION NOTE
Figure Other Configuration
AI03155
Click "JTAG Configuration" tab, shown Figure ensure that none boxes checked (because checking boxes would enable JTAG port operational 100% time). Since, this tutorial, multiplexing JTAG pins with other signal functions, desired that JTAG functions only operational when signal active (see Figure schematic). Enter value `ABCDEF12' "User Code" below. This value will programmed into your device. User Code value wish (e.g. identify product software revisions, serial numbers, etc.). eight hexadecimal characters entered.
22/83
AN1154 APPLICATION NOTE
Figure JTAG Configuration
AI03156
Click "Sector Protection" tab, shown Figure ensure that none boxes checked. appropriate sector should only checked desired that selected sector write protected. These bits changed, later, through JTAG port device programmer.
23/83
AN1154 APPLICATION NOTE
Figure Sector Protection
AI03157
When finished with global configuration settings, click button. This saves configuration. FLASH+PSD configuration completed. ever wish view configuration file, first ensure Configuration Mode (see step this section). Next, pull down View menu select Configuration Report, shown Figure then select File->Print.
24/83
AN1154 APPLICATION NOTE
Figure Configuration Report
AI03158
Fitter: Fitting Address Translation Fitter consists Fitter Address Translator. Fitter accepts input from PSDabel Configuration, synthesizes user logic configuration, fits design FLASH+PSD silicon. Address Translator process allows user firmware from cross-compiler Intel S-Record format) into blocks within PSD. result, firmware merged with logic configuration definition PSD. output Address Translator tutor8XX.obj file. Fitting Design input files Fitter are:
tutor8XX.tt2-PLA file generated PSDabel. tutor8XX.glc-M88 FLASH+PSD configuration file generated Configuration. tutor8XX.fob-PLD fuse-map FLASH+PSD configuration file. tutor8XX.afu-Generated Simulator. tutor8XX.pfu-Generated Simulator. tutor8XX.obj-Object file (PLD Configuration portion only). tutor8XX.frp- Fitter report file.
output files generated Fitter are:
Design: Click Options Menu, select "Fitter Options" specify four fitting options, shown Figure tutorial, choose Keep Current under "Pin Assignment", ensure that "Enable Product Term Expansion" "Perform Register Synthesis" boxes checked.
25/83
AN1154 APPLICATION NOTE
Figure Fitter Options
AI03159
Click save Fitter options. Then, pull down PSDsoft menu PSDsoft window choose Fitter, shown Figure click "Logic Synthesis Fitting" "PSDsoft Design Flow" window.
26/83
AN1154 APPLICATION NOTE
Figure PSDsoft->PSD Fitter
AI03160
Pull down Fitter menu choose Fitting, shown Figure click button tool bar. clicked "Logic Synthesis Fitting" design flow, Fitter would automatically, this step would necessary. Figure Fitter->Fitting
AI03161
Fitter appends files: file PSDsoft.log) error file (tutor8XX.ERR Check file possible errors. there errors present (there should modify tutor8XX.abl file), skip Step fitting successful, have view tutor8XX.eq2 file PSDabel which logic function caused fitting problem, modify tutor8XX.abl file accordingly. view optimized equation file (tutor8XX.eq2 step section entitled "Compiling Tutor Design" page
27/83
AN1154 APPLICATION NOTE
Re-compile modified tutor8XX.abl file. Repeat Steps until successful been found. Re-enter Fitter program, proceed Step Examine Fitter Report File pulling down VIEW menu, shown Figure report file shows results fitting process, assignment M88x3Fxx. want fitting other than generated, return tutor8XX.abl file change signal assignments appropriate. Figure View->Fitter Report
AI03162
Generating code PSDsoft generate ANSI code functions headers controlling FLASH+PSD. This optional step. However, will save time implementing low-level driver function header files. functions headers ANSI-C compatible. files that generated should edited suit your application, then compiled linked with rest your application code, using cross-compiler linker. functions headers that generated PSDsoft include following operations:
Flash memory program erase algorithms EEPROM program algorithms control definition memory power management.
Although code generation performed anytime after project opened, recommend done after have successfully performed your design. Once successful achieved, functions configurations defined, code tailored accordingly. source programming files implement function this tutorial have been provided. Since this tutorial meant cover aspects FLASH+PSD design, though, cover description would code generation utility your project. Take following steps generate code: Pull down Tools menu PSDsoft window choose Generate Code, shown Figure
28/83
AN1154 APPLICATION NOTE
Alternately, click Code Gen" button Design Flow window. Figure Tools->Generate Code
AI03163
dialog should appear, shown Figure Figure Code Generation Functions/Headers
AI03164
"Functions/Headers" dialog following sections: Device Info: This contains FLASH+PSD family part number current project. These values cannot changed unless this project closed different opened. Header: This specifying folder which would like place header files (.h) generated PSDsoft. (Click Browse button help filling this section). Typically, folder your cross-compiler environment chosen. cannot change name headers
29/83
AN1154 APPLICATION NOTE
file(s) this point since these header files referenced name within other header files functions that also generated PSDsoft. Once headers functions copied their designated folders, edit header file names wish, long change their names respective "#include" statements. Functions: This specifying folder which would like place function file (.c). (Click Browse button help filling this section). Typically, folder your crosscompiler environment chosen. This file will contain functions specify next section. Code Selection: Select categories code functions that would like integrate into your application program. Under "PSD Category" major functional groups that supported with code device that used this project. Under Code Coverage" brief list individual functions that available within each category. select more than category, hold "Ctrl" while making selections with left mouse button. Even more than category selected, though, only file generated because functions appended within same file. Description: This offers description functions that generated selected Code Selection" box. double-click function within Description box, code that will generated shown, idea what will appear sample file. After have made your selection, first click Apply, then click this example, three files will written your folder(s), which are: m8813F1.c: ANSI-C source selected functions m8813F1.h: ANSI-C header file define particular registers map813F1.h: ANSI-C header file define locations system memory elements (Flash, EEPROM, registers, etc.). m8813F1.h file contains define statements each individual function within m8813F1.c file. Later, edit m8813F1.h, simply remove comment delimiters (//) from define statement function that would like compiled with rest your source code. Click "Coded Examples" dialog box, shown Figure
30/83
AN1154 APPLICATION NOTE
Figure Code Generation Coded Examples
AI03165
This sheet contains several examples that basis building your code application. These complete projects (main, functions, headers) targeted particular MCU. copy these files another folder, browse them ideas, paste sections from examples into your cross-compiler environment. There three sections: Example: specify folder which would like place example project files generated PSDsoft. (Click Browse button, select folder, when filling this section). Example Selection: There several areas which generate code. Each category implements high-level system function, such memory paging, UART downloads Flash memory, etc. Description: This describes each coded examples "Example Section" Once code generated PSDsoft integrated into your application, successfully compiled linked your cross-compiler, ready address translation. Performing Address Translation Address Translator combines tutor8XX.fob file with firmware file(s) generated your chosen cross-compiler. Address Translator generates tutor8XX.obj file that downloaded programmer that compatible with FLASH+PSD. addresses within generated tutor8XX.obj file special "direct" addresses meaningful programming device. They "system" addresses, that would use, that DPLD decodes. That what meant "Address Translate". translation "system" addresses that
31/83
AN1154 APPLICATION NOTE
compiler/linker knows about, "direct" addresses that device programmer knows about. perform address translation, take following steps: Pull down PSDsoft menu, choose Fitter. Then, pull down Fitter menu choose Address Translate, select "MCU Code Mapping" design flow. "Address Translation" dialog appears, shown Figure Figure Address Translation
AI03166
will notice warning message from PSDsoft upon entering Address Translate window. This warning reminder ensure that take paging into account when entering start/stop addresses file names. Address Translation dialog following sections: Memory Select Name: This name memory segment that will selected when associated equation true. Memory Select Equations: Each cell shows equation appropriate memory segment. These optimized equations from PSDabel file. They displayed convenience, cannot modified this window. File Address Start: This first system address, from compiler/linker, that will mapped memory segment. File Address Stop: This last system address, from compiler/linker, that will mapped memory segment. File Name: This firmware file that generated your Compiler/Linker. Record Type: supported formats Intel Motorola S-Record. Mapping Mode: modes mapping supported, direct relative. more information, please consult PSDsoft User Manual. Notice that PSDsoft attempts fill File Start File Stop Addresses based your PSDabel equations. However, paging used, this tutorial, these file addresses must handled carefully since PSDsoft does know your cross-compiler linker handles paging. progress, this process should become clear.
32/83
AN1154 APPLICATION NOTE
Type file names your linker output appropriate places. this example, five files used. (See Appendix information system memory these files relate.) Four five files programmed into Flash memory different pages. remaining file programmed into boot area EEPROM. four Flash files page_0.hex, page_1.hex, page_2.hex, common.hex. file EEPROM boot.hex. Each these files contain KBytes code. Enter File Start Addresses, File Stop Addresses, File Names according Table Table Mapping Memory Sectors Files
Memory Select EES0 EES1 EES2 EES3 File Start Address 0000 4000 8000 C000 8000 C000 8000 C000 0000 2000 File Stop Address 3FFF 7FFF BFFF FFFF BFFF FFFF BFFF FFFF 1FFF 3FFF File Name Common.hex Common.hex Page_0.hex Page_0.hex Page_1.hex Page_1.hex Page_2.hex Page_2.hex boot.hex boot.hex
this design, different file name been used each sections code Flash memory. This because address space overlap segments. This file scheme used because, even though these sections code physically reside different memory pages, some linkers will place them overlapping absolute address space. method depends your linker. Alternatively, single file name across many memory chip selects your linker automatically appends extra address bits that represent your paging scheme. would then, example, enter 18-bit addresses accompany single file name, which passed Address Translate utility, instead 16-bit addresses accompany several file names. Optionally, specify only EEPROM contents programmed device programmer. desired load system code into Flash memory while in-system, device programmer. this case, only information EES0 EES1 should entered Address Translate utility. Ensure that Direct Mapping selected "Mapping Mode" box. Select Intel Record "Record Type" box. Click perform address translation. errors indicated, then tutor8XX.obj will placed your project directory. your copy PSDsoft includes PSDsilosIII simulator, should simulate verify your design before programming FLASH+PSD. Please next section simulate tutorial design.
33/83
AN1154 APPLICATION NOTE
FLASH+PSD Chip Simulation PSDsilosIII ST's version SIMUCAD's SILOSIII simulator software. provides chip-level simulation design verification using Verilog Hardware Description Language (Verilog-HDL). Appendix lists stimulus file tutor8XX.stl) this tutorial. Many internal nodes M88x3Fxx available tracing. Descriptions signals that traced simulator listed Appendix PSDsoft generates input files required simulator. file that must created stimulus file (.stl). stimulus file, same names used your PSDabel file, predefined ones Appendix
PSDsoft.run File files generated PSDsoft simulation process PSDsoft.run, listed Figure command batch file used PSDsilosIII. additional information PSDsilosIII commands (those commands that start with please refer PSDsilosIII's on-line help.
Figure PSDsoft.run File !Reset !file .sav Tutor8XX !control .ext `timescale 1ns/0.1ns !lib d:\psdsoft\psd8.v `include "tutor8XX.top" `include "tutor8XX.stl" endmodule PSDsoft.run file:
"`time-scale 1ns/0.1ns" compiler directive defining delay values module unit measurement times delays "0.1 precision which delays rounded "`include" also compiler directive that allows entire contents Verilog source file included another file (PSDsoft.run this case).
Tutor8XX.top generated PSDsoft, based PSDabel file, allows signal names within PSDabel file. There also parameter definitions high impedance state signals through Z32) .top file. Notice "endmodule" statement last statement PSDsoft.run file. there because complements "module WSIdesign" statement .top file. There important thing note about included library files: these files look other files automatically generated PSDsoft from fuse-map file, have .afu .pfu extension. They allow simulation logic, defined .abl file, stimulus file.
Running Logic Simulator Review stimulus file tutor8XX.stl) listed Appendix Pull down PSDsoft menu main PSDsoft window select Simulator, click simulator button tool bar. tutor8XX.stl file automatically opened PSDsoft, shown Figure
34/83
AN1154 APPLICATION NOTE
Figure Running Logic Simulator
AI03167
Click LogicSim, shown Figure invoke PSDsilosIII simulator Figure LogicSim
AI03168
following events happen automatically, result clicking LogicSim button: PSDsilosIII simulator starts simulator loads project tutor8XX.spj, PSDsoft.run, window displaying tutor8XX.stl file, shown Figure
35/83
AN1154 APPLICATION NOTE
Figure Logic Simulator Input
AI03169
Click button. This automatically opens "Output" window viewing results simulation, shown Figure Figure Logic Simulator Output
AI03170
Running Analyzer that logic simulation complete, results displayed with PSDsilosIII Data Analyzer performing following steps: Pull down Window menu select Data Analyzer, shown Figure press click appropriate button tool bar.
36/83
AN1154 APPLICATION NOTE
Figure Running Analyzer
AI03171
PSDSilosIII Data Analyzer window appears with simulation results displayed screen, shown Figure (but Your screen will look different.). Please tutorial Data Analyzer Explorer under Help->Contents rearrange group signals. Figure Simulation Results
AI03172
Working With Explorer Explorer PSDSilosIII used conjunction with Data Analyzer trace signals. open explorer, ensure that have simulated design following steps section entitled "Running Logic Simulator", page Next click Window->Open Explorer menu selection Explorer button explorer window will appear, shown Figure Explorer shows viewable signals.
37/83
AN1154 APPLICATION NOTE
Figure Explorer
AI03173
Signals added Data Analyzer window using Explorer holding "CTRL" button down, clicking signals that want Data Analyzer window. Once have chosen desired signals, right-click signals, select Signals Analyzer. Next, click anywhere Data Analyzer window, signals added will appear bottom window, shown Figure Figure Adding Signals Analyzer
AI03174
more information Explorer Data Analyzer, please on-line help, PSDsilosIII User Manual. Also, please refer this manual information PSDsilosIII Watch Window, which beyond scope this tutorial. Programming FLASH+PSD Programmer programming interface MagicProIII®, PSDpro, FlashLink programmers. enables downloading .obj file; displays Flash EEPROM locations, fuse-map, configuration bits (ACR). also perform following operations from Functions menu: Blank Test: check device blank. Upload: upload contents device that were programmed buffer. Program: program device with .obj file. Verify: verify programmed device against .obj file buffer. Erase: erase device completely.
38/83
AN1154 APPLICATION NOTE
have MagicProIII, PSDpro, FlashLink device programmer connected your take following steps program FLASH+PSD after design been compiled .obj file been generated: Pull down PSDsoft menu main PSDsoft window choose Programmer, click appropriate button tool bar. tutor813XX.obj file downloaded displayed screen automatically, shown Figure Figure Programmer
AI03175
Assuming have MagicProIII programmer installed, program device following: Pull down Functions menu select Program; click Program button tool that available when Programmer invoked. "PSD Programmer Program Confirmation" dialog appears, shown Figure which enables program Flash, EEPROM PLD/ (PSD Configuration) regions device.
39/83
AN1154 APPLICATION NOTE
Figure Programmer Program Confirmation
AI03176
Select "All", shown Figure Place device into programmer, checking that correctly orientated, snap down device carrier. Then, click button. programming takes place, MagicProIII programmer checks each location, after programmed, make sure matches contents .obj file. particular location cannot programmed properly, error message shown. this occurs, must restart from beginning, program fully erased functional part. PSDpro have PSDpro connected your PC's parallel ports, select configure going Options menu Programmer environment selecting Hardware Setup, shown Figure Figure Programmer Hardware Setup
AI03177
Once "PSD Programmer Hardware Setup" dialog appears, select PSDpro, "Hardware Section", shown Figure
40/83
AN1154 APPLICATION NOTE
Figure
AI03178
Next, will that Auto Select option becomes active. This means that PSDsoft will automatically detect which parallel port your PSDpro connected. Just click PSDpro will detected configured connections good. same menu options capabilities that apply MagicProIII section above also apply PSDpro. JTAG: FlashLink have FlashLink cable installed your PC's parallel ports, select configure follows: Options menu Programmer environment, select Hardware Setup. Once "PSD Programmer Hardware Setup" dialog appears, select FlashLink, "Hardware Section", shown Figure Figure FlashLink
AI03179
Next, will that Auto Select option becomes active, well Loop Test, shown Figure
41/83
AN1154 APPLICATION NOTE
Figure Auto-select Loop Test
AI03180
Auto Select means that PSDsoft will automatically detect which parallel port your FlashLink cable connected (even other FlashLink cable connected target system). Just click FlashLink cable will detected. Optionally, return Hardware Setup menu Loop Test FlashLink cable. This hardware integrity test that requires loop-back cable (that provided) installed FlashLink cable. (Please FlashLink installation manual). connect FlashLink cable your target system, power-on system. target system needs powered since FlashLink circuitry draws power from target. your JTAG chain described next section) Once your JTAG chain been program your device while in-system. (Programming accomplished "JTAG Chain Setup" window. This described next section.) Setting JTAG Chain This section takes step-by-step through creation JTAG Chain File. Since this procedure been finalized, please check site (www.st.com) updates this document. following rules apply setting JTAG chain:
JTAG chain more devices must defined. JTAG compatible devices that connected JTAG bus, including FLASH+PSD non-PSD devices from other vendors compose JTAG chain. Non-PSD devices that part JTAG chain will placed, automatically, bypass mode. length instruction register, along with name device must entered each nonPSD device. future versions PSDsoft, will able load this information automatically with BSDL file.) Before programming device(s), user must have valid .obj file each device chain Additionally, Serial Vector Format file, filename.svf, created third party JTAG programming support.
Please refer Application Note AN1153 information these areas: JTAG Spec Compliance Programming Support Program/Erase Flow Control SVF/BSDL file information Enhanced functions Multiplexed JTAG functions Dedicated JTAG functions
42/83
AN1154 APPLICATION NOTE
JTAG connector JTAG Chaining Now, let's step through sample JTAG chain setup, create JTAG chain file (.jcf). Under JTAG menu, select JTAG Chain Setup, shown Figure click "JTAG Prog" design flow. Figure JTAG Chain Setup
AI03181
This opens "JTAG Chain Setup" dialog box, shown Figure Figure JTAG Chain Setup Dialog
AI03182
"Chain Information" box, click Browse. This brings "Open" window, shown Figure Select Tutor8XX.obj file directory, click Open.
43/83
AN1154 APPLICATION NOTE
Figure JTAG Chain Setup Open Window
AI03183
Your "JTAG Chain Setup" window should appear shown Figure Figure JTAG Chain Setup Window
AI03185
device name (M8813F1x this case) does automatically appear "Device Name" window, select appropriate device. Click button. Your "JTAG Chain Setup" window should appear shown Figure
44/83
AN1154 APPLICATION NOTE
Figure JTAG Chain Setup Window After
AI03186
Right-click anywhere line that just appeared (line select Properties, shown Figure
45/83
AN1154 APPLICATION NOTE
Figure JTAG Chain Setup Window Selecting Properties
AI03187
This opens "JTAG Chain Setup Properties" dialog box. Ensure that "Set Pins/Flow Control" selected, window with following selections (based Figure this tutorial). proper selections shown Figure Under "Flow Control", select Option "Set Pins" box, ports follows: Port pins "OUTPUT (CMOS)" Port pins "INPUT (HI-Z)", pins "OUTPUT CMOS)" Port change "TSTAT (CMOS)", "TERR (CMOS)". Leave rest pins they are. Port pins "INPUT (HI-Z)", "OUTPUT HIGH (CMOS)"
46/83
AN1154 APPLICATION NOTE
Figure JTAG Chain Setup Properties
AI03188
Click Apply button (which saves information have entered, far, greys "Apply" button out). Then, click "JTAG Attributes" tab. Your "JTAG Chain Setup Properties" window should appear shown Figure
47/83
AN1154 APPLICATION NOTE
Figure JTAG Chain Setup Properties JTAG Attributes
AI03189
"Device Name", "Instruction Register Length:", "JTAG Device ID:" greyed because this information automatically entered whenever select M88x3Fxx device. want enter information about non-PSD device, which included your chain, here place another device, need enter valid information "JTAG Attributes" section. Also, note that select "JTAG Device box, PSDsoft verifies JTAG before programming erasing device. Click "User Code" tab, give display shown Figure enter value "User Code" box, value compared with User Code already programmed into device before JTAG operation occurs (e.g. Erase, Program, etc.). leave this area blank, comparison performed. Enter ABCDEF12 "User Code" box. Then press Apply (which greys "Apply" button out), finally press
48/83
AN1154 APPLICATION NOTE
Figure JTAG Chain Setup Properties User Code
AI03190
Now, should back "JTAG Chain Setup" window. Right click same line step only this time, choose Erase, shown Figure
49/83
AN1154 APPLICATION NOTE
Figure JTAG Chain Setup Erase
AI03191
should "Operation: Erase" dialog box, shown Figure Ensure that checked under "Regions" block, click Figure Operation Erase
AI03192
10.Your "JTAG Chain Setup" window should appear shown Figure Click start exchange FlashLink cable. "Log Mode" checked, JTAG communication status will appear PSDsoft window, file tutor8XX.log. Turning Mode feature will slow down JTAG communications.
50/83
AN1154 APPLICATION NOTE
Figure JTAG Chain Setup After Erase
AI03193
11.After erase completed indicated window), right click same line step choose Program. Select when window, shown Figure appears. Figure Operation Program
AI03194
Your "JTAG Chain Setup" should appear shown Figure Select will programmed with information tutor8XX.obj file.
51/83
AN1154 APPLICATION NOTE
Figure JTAG Chain Setup After Program
AI03184
12.After have programmed device, click Reset bottom window. This resets target circuit board that connected FlashLink cable. This needed after Flashlink programs because will have lost "mind" this point. 13.Click Save button, save your work JTAG Chain File future use. This action brings "Save dialog box, shown Figure Type tutor8xx" "File name" box, click Save. file tutor8xx.jcf will created. Figure JTAG Chain Setup Save
AI03195
14.Now, "JTAG Chain Setup" window should appear shown Figure
52/83
AN1154 APPLICATION NOTE
Figure JTAG Chain Setup After Save
AI03196
15.If need load this .jcf file future, will have click Browse button, which will bring "Open" dialog box, shown Figure Choose tutor8xx.jcf file, click Open. Figure JTAG Chain Setup Open Dialog
AI03197
Lastly, before leaving "JTAG Chain Setup" window, wish create Serial Vector Format (.svf) file with third-party programmer. click Create button, Browse through your directory tree find place where want place .svf file.
53/83
AN1154 APPLICATION NOTE
FLASH+PSD FLASH+PSD programmed in-system, with without participation from MCU. with MCU, please Appendix UART download information considerations. without participation, Section entitled "JTAG: FlashLink" page FlashLink JTAG programming within PSDsoft environment please application note, AN1153. REFERENCES FLASH+PSD Family Data Sheet Application Note AN1153 detailed JTAG channel Application Note AN1171 details CPLD pins Application Note AN1176 design guide 68HC11 M8813F1x. Application Note AN1177 design guide 80C51XA M8813F2x. Application Note AN1178 design guide 80C51 M8813F2x.
54/83
AN1154 APPLICATION NOTE
APPENDIX ABEL DESIGN FILE "TUTOR8XX.ABL"
module Tutor8XX title '8XX Tutorial Design File'; Designed by:Dan Harris Mark Rootz Design date:6-16-98 Description:This shows logic implementation sample design Tutorial. design highlights following functionality M88x3Fxx: Effective efficient Input Output Micro<->Cells pins while underlying Micro<->Cell being used other functionality. WSIPSD PROPERTY statement output demultiplexed address bits, define Input Micro<->Cells/Output Micro<->Cells. Multiplexing JTAG pins with other I/O. logically interface 80C31 MCU, RTC, circuit. Revision:1.0 Date:9-21-98 Convention:The used throughout file indicate active signals. Note that used with reserved signal names below.
"************************** Interface signal declarations ************************** reserved signal names automatically assigned appropriate following inputs from pin; "CNTL0 Input:(pin 47)- write strobe pin; "CNTL1 Input:(pin 50)- read strobe psen pin; "CNTL2 Input:(pin 49)- program store enable pin; "PD0 Input:(pin 10)- address latch enable reset pin;"Input:(pin 48)- system reset a15.a0 pin;"Input:(pins 46.39,37.30)- demuxed address
"************************** **************************
Port declaration
Port Control outputs mode outputs Control0.Control2pin 21;"Some generic control signals Assign latched/demultiplexed address Port pins pa0. WSIPSD PROPERTY 'Address_Out Aout[4:0]:Addr_Out[4:0]';
Port
55/83
AN1154 APPLICATION NOTE
PGA_Din2.PGA_Din0pin 7;"Data bits used program "Implemented with mode Measured_Level3.Measured_Level0 istype 'reg';"Upper bits converter (ADC) WSIPSD PROPERTY 'DataBus_IMC D[7:4]:Measured_Level[3:0] PortB'; Port Note that pins pc0, pc1, pc5-6 multiplexed output/JTAG signals. pc3, pc4, JTAG signals that multiplexed. Ensure that under "Global Configuration" with "JTAG Configuration" selected that none boxes enabling various JTAG signals certain pins checked because device will expect only valid JTAG signals these pins, multiplexing done under these circumstances. (pin used VSTBY (set global configuration) Intrn 20;"Interrupt when gain needs changed/JTAG Start_Convpin 19;"Start Conversion signal ADC/JTAG Trim 17;"The gain high needs decremented/JTAG TSTAT Boost 14;"There enough gain-increment it/JTAG TERRn JCEn 11;"JTAG chip enable signal used demultiplex Port output JTAG
Port (pin assigned above signal from microcontroller. external chip selects that generated decoding address should placed Port when possible save many resources possible. RTCcsn 8;"Real Time Clock (RTC) chip select/JTAG clkin pin;"Port (pin System clock
Output Micro<->Cell assignments WSIPSD PROPERTY 'DataBus_OMC D[7:4]:Desired_Level[3:0] MCELLAB'; WSIPSD PROPERTY 'DataBus_OMC D7:begin_cycle MCELLBC'; "************************** ************************** mxord3 meqd Internal node declarations
node;"This signal needed save product terms node;"True when measured signal equals desired signal level
56/83
AN1154 APPLICATION NOTE
begin_cycle node istype 'reg';"This signal takes state machine idle STATE1.STATE0 node istype 'reg';"State machine bits Desired_Level3.Desired_Level0 node istype 'reg';"The desired gain level fs7.fs0 node;"Main Flash memory segments ees3.ees0node; "EEPROM memory segments Reserved node names node;"Select SRAM memory space csiop node; "Control register jtagsel node 102;"This JTAG enable product term. used enable "the JTAG port signals. pgr1.pgr0 node;"Internal Page Register bits
following page register definitions example manipulate memory facilitate ISP. This scheme explained Appendix Application note
swapnode 117;" This page register (pgr7) will used swapping memory segments after firmware download from 8031 UART port completed. When swap secondary occupies boot area ISP, swap primary occupies boot area. enable_data_half node 116; This page register (pgr6) will used manipulate EEPROM. this divide EEPROM into equal sections, boot general data. When this bit=0, boot section active. When this data section active.
"**************************
DEFINITIONS
**************************
DLEVEL gain level MLEVEL gain level latched IMCs STATE_MACHINE [STATE1.STATE0]; .x.;"Don't care symbol .c.;"Clock symbol page [pgr1,pgr0]; address [a15.a0];"De-muxed microcontroller address signals
57/83
AN1154 APPLICATION NOTE
EQUATIONS "************************** DPLD equations **************************
Generate active high chip selects main Flash segments. Each segment bytes M88x3Fxx devices. ((address ^h8000) (address ^hBFFF) (page !swap) ((address ^h0000) (address ^h3FFF) (page swap); (address ^h4000) (address ^h7FFF) (page (address ^h8000) (address ^hBFFF) (page (address ^hC000) (address ^hFFFF) (page (address ^h8000) (address ^hBFFF) (page (address ^hC000) (address ^hFFFF) (page (address ^h8000) (address ^hBFFF) (page (address ^hC000) (address ^hFFFF) (page
Generate active high chip selects EEPROM segments. Each segment bytes M8813F1x devices. ees0 ((address ^h0000) (address ^h1FFF) (page !swap) ((address ^h8000) (address ^h9FFF) (page swap !enable_data_half); ees1 ((address ^h2000) (address ^h3FFF) (page !swap) ((address ^hA000) (address ^hBFFF) (page swap !enable_data_half); ees2 (address ^hC000) (address ^hDFFF) (page swap enable_data_half; ees3 (address ^hE000) (address ^hFFFF) (page swap enable_data_half;
//Generate active high chip select SRAM bytes). (address ^h0100) (address ^h08FF) (page
Generate active high chip select control registers. contiguous bytes must decoded M88x3Fxx devices. csiop (address ^h0900) (address ^h09FF) (page
Enable JTAG port when JTAG Chip Enable (JCEn) Signal active
58/83
AN1154 APPLICATION NOTE
jtagsel !JCEn;
"************************** **************************
GPLD/ECSPLD equations
IMPORTANT NOTE: Comment these next four equations ABEL simulation only. PSDsilosIII Simulator requires equations (and they functionally correct). problem that presets (loads) clears these registers, value registered through input. However, ABEL simulator does reconize "dot" extentions these would normally through equations). basic functionality still properly tested, actually implemented hardware slightly different. intend ABEL Simulator, comment following four lines that test vectors file will work properly. DLEVEL.ck DLEVEL begin_cycle.ck begin_cycle mxord3 Measured_Level3 !Desired_Level3; Trim gain when Measured signal level greater than desired signal level. Trim MLEVEL DLEVEL Trim (Measured_Level3 !Desired_Level3) ((Measured_Level2 !Desired_Level2) mxord3) ((Measured_Level1 !Desired_Level1) mxord3 (Measured_Level2 !Desired_Level2)) ((Measured_Level0 !Desired_Level0) mxord3 (Measured_Level2 !Desired_Level2) (Measured_Level1 !Desired_Level1)); Boost gain when Measured signal level less than desired one. meqd (MLEVEL DLEVEL); Boost !meqd !Trim; Generate chip select !RTCcsn ((address ^h0a00) (address ^h0aff)); Loading various registers
59/83
AN1154 APPLICATION NOTE
MLEVEL.ld !clkin; State machine which controls conversion start ADC, interrupt MCU, strobing IMCs STATE_MACHINE.ck clkin; STATE_MACHINE.re !reset; state_diagram STATE_MACHINE; state Start_Conv Intrn (begin_cycle then else state Start_Conv goto state Start_Conv goto state !Intrn Trim Boost; "Interrupt when Measured equal Desired goto
Test_Vectors Test state machine, trim, ([clkin, reset, begin_cycle, MLEVEL, [Start_Conv, Intrn, STATE1, STATE0, ^h3, ^h4, ^h5, ^h5, ^h5, ^h4, ^h4,
boost signals DLEVEL] Trim, Boost]) ];"system reset ];"system reset
60/83
AN1154 APPLICATION NOTE
APPENDIX STIMULUS FILE "TUTOR8XX.STL"
tutor8xx.stl file consists four sections: Parameter Definitions: each FLASH+PSD control registers address (offset from CSIOP base address). parameters make stimulus file easier read. User-defined tasks: these used define implement microcontroller cycles. each task, timing control signals address data should follow that microcontroller, they have exact; they just have scale. Simulator will simulate cycle every time read, write, psen task called. Signal Initialization: must specify initial logic level input signals before simulation. output signals that want simulate should initialized high impedance state. stimulus inputs: here stimulus inputs needed perform read write cycles access Flash, EEPROM, SRAM ports. Inputs also generated exercise CPLD functions. //Title:tutor8XX.stl //Function:Simulation file M88x3Fxx Tutorial //Designed by:Dan Harris //Design Date:6-23-98 //Description:This file intended used PSDsilosIII environment stimulus file M88x3Fxx Tutorial. idea this file show Verilog-HDL language works, rather format .stl file, applies this tutorial example. main parts this file are: Parameter declarations which make file more readable Read, write "PSEN/" cycle tasks 80C31 area where user wish file order test more functions actual stimulus design Parameters declarations address offsets CSIOP address space //Port parameter parameter parameter parameter //Port
='h0902; ='h0900; 'h0908; Port_A_En_Out='h090C;
61/83
AN1154 APPLICATION NOTE
parameter parameter parameter parameter ='h0903; ='h0901; 'h0909; Port_B_En_Out='h090D;
//Port parameter ='h091A; parameter ='h0910; parameter 'h0916; //Port parameter ='h0917; parameter ='h0911; parameter Port_D_En_Out='h091B; //Port OMCs parameter 'h0922; //Port OMCs parameter 'h0923; //Other control registers parameter 'h09C2; parameter PMMR0_Reg='h09B0,PMMR1_Reg ='h09B2; parameter PMMR2_Reg='h09B4,JTAG_En 'h09C4; parameter Page_Reg='h09E0,VM_Reg ='h09E2;
Defining tasks simulate 80C31 cycles (read, write psen cycles). Note that cycles shortened simulation purposes, functionality remains same. //The "write task" implements 80C31 write cycle task write; input [15:0] addr_bus; input [7:0] data_in;
62/83
AN1154 APPLICATION NOTE
begin 1;//Latch address lines adio addr_bus;//Read valid address (adio defined .top file) 0;//Ale inactive adio[7:0] data_in;//Write operation 0;//Write pulse #100 1;//Write ends adio[7:0] Z8;//Z16 defined .top file endtask
//The "read task" implements 80C31 read cycle timing task read; input [15:0] addr_bus; begin 1;//Latch address lines adio addr_bus;//Read valid address 0;//Ale inactive adio[7:0] Z8;//Float address defined .top) 0;//Read pulse #100 1;//Read ends endtask
//The "psen task" implements 80C31 psen program fetch cycle task psen; input [15:0] addr_bus; begin 1;//Latch address lines adio addr_bus;//Set-up right address 0;//Ale inactive adio[7:0] Z8;//Float address psen 0;//Read pulse #100 psen 1;//Read ends
63/83
AN1154 APPLICATION NOTE
endtask
Define some busses here make program easier read. //adrout latched address output Port [4:0] adrout; Addr_Out4, Addr_Out3,Addr_Out2, Addr_Out1, Addr_Out0; assign {Addr_Out4, Addr_Out3, Addr_Out2, Addr_Out1, Addr_Out0} adrout; [3:0] measured_value; Measured_Level3, Measured_Level2, Measured_Level1, Measured_Level0; assign {Measured_Level3, Measured_Level2, Measured_Level1, Measured_Level0} measured_value; [3:0] desired_value; Desired_Level3, Desired_Level2, Desired_Level1, Desired_Level0; assign {Desired_Level3, Desired_Level2, Desired_Level1, Desired_Level0} desired_value; [3:0] PGA_data; PGA_Din3, PGA_Din2, PGA_Din1, PGA_Din0; assign {PGA_Din3, PGA_Din2, PGA_Din1, PGA_Din0} PGA_data; [2:0] cntrl; Control2, Control1, Control0; assign {Control2, Control1, Control0} cntrl;
Stimulus starting point Initialize first. Then proceed with rest simulation.
64/83
AN1154 APPLICATION NOTE
initial begin //Initialize signals first reset 0;adio 'h0000; 0;psen adrout measured_value 'h0; desired_value 'h0; PGA_data=Z4;cntrl Intrn Z1;Start_Conv Trim Z1;Boost JCEn #100 reset Take reset after 100ns
//We ready some configuration //Port configuration //Configure Port pins output latched address, rest //of port will output control information mode. //Writing "1F" Port control register enables latched address output //pins pa0, rest port output I/O. write(Port_A_Cntl_Reg, 'h1f); //Writing "FF" Port direction register sets Port pins outputs. write(Port_A_Dir_Reg,'hff); //Port configuration //Since there latched address output Port control register //defaults mode output, only direction register needs setup. //Only pins will outputting data, rest will receiving //input write(Port_B_Dir_Reg,'h0f); //All Port output (with exception Vstby input write(Port_C_Dir_Reg,'hfb);
65/83
AN1154 APPLICATION NOTE
//There only output Port (RTCcs/), direction register //setup follows: write(Port_D_Dir_Reg,'h04); //Set mask registers that only desired portion OMCs //written. Only desired value (MCELLAB[7:4]), begin (MCELLBC7) //written write(Port_AB_OMC_Mask, 'h0f); write(Port_BC_OMC_Mask, 'h7f);
//Write EEPROM segment ees0, Flash segment //then read SRAM write('h0020,'h5a);//write ees0 write('h5A00,'ha5);//write read ('h07FE); //read internal SRAM Wait, then initialize gain output data pins pb0. write(Port_B_Dout_Reg,'h01);
Assume small value output since gain measured_value='h3;
Load into desired value register write(Port_AB_OMC, 'h50);
Take state machine idle state generate chip select. write(Port_BC_OMC, 'h80);
Since measured value less than desired one, gain would boosted after interrupt generated cycles after start state machine). should increment gain that time. #400 write(Port_B_Dout_Reg, 'h02); $finish;
66/83
AN1154 APPLICATION NOTE
initial begin Generate system clock used state machine, etc. Note time scale psdsoft.run file. clkin=0; forever #100 clkin=~clkin; //stimulus ends here
67/83
AN1154 APPLICATION NOTE
APPENDIX LIST FLASH+PSD SIMULATION SIGNALS
Figure gives list signals from Explorer that viewed using Data Analyzer. This list based tutor8XX.abl file, predefined signals. list will vary depending names your .abl file, most signals will same. Figure List Simulation Signals
AI03198
above signals dragged Data Analyzer window viewing. Once there, signals made into buses. more information Explorer Data Analyzer, PSDsilosIII's on-line help, PSDsilosIII User Manual.
68/83
AN1154 APPLICATION NOTE
Table contains viewable predefined signal names, along with brief description each. conventions used table are:
represents number represents letter
list above determine which letters numbers apply respective signal. Table Table C1-Predefined Signal Names their Descriptions
Signal/Bus Name adioh[15:8] adiol[7:0] ctrl_x data[7:0] din_x dirff_x dout_x drive_x ecsdn ee_boot_oe ee_power_down ee_protection[3:0] ee_ready_busy_N ee_sdp_disable ee_sdp_enable ee_toggle eesel_f enable_x f_protection[7:0] flash_oe flash_polling flash_ready_busy flash_toggle flsel_f jtag mask_mcab mask_mcbc mcellabn mcellabn_clk Description register Address/Data high byte Address/Data byte Port control register Non-multiplexed 8-bit data Port data register Port direction register Port data register Port drive register External chip select output EEPROM output enable EEPROM power down signal security EEPROM sector protection EEPROM ready/busy signal EEPROM software data protection disable EEPROM software data protection enable EEPROM toggle signal EEPROM final chip select Enable port driver Flash sector protection register (read only) Flash output enable Flash data polling Flash ready/busy signal Flash toggle Flash final chip select JTAG enable register Mask register outputs Mask register outputs MicroCell output Output MicroCell clock input
69/83
AN1154 APPLICATION NOTE
Signal/Bus Name mcellabn_pr mcellabn_reg mcellabn_re mcellbcn mcellbcn_clk mcellbcn_pr mcellbcn_reg mcellbcn_re nib_xn out_mcab[7:0] out_mcbc[7:0] pxn_imc pxn_oe pgr7_0 pmmrn pseln rd_bsy sram_oe Description Output MicroCell preset input Output MicroCell register input Output MicroCell reset input Output MicroCell output Output MicroCell clock input Output MicroCell preset input Output MicroCell register input Output MicroCell reset input Product term control port x[7:4] x[3:0] input MicroCell Output registers MicroCell Output registers MicroCell Port Port Input MicroCell Port output enable product term Power down signal Page register outputs Power management mode register Port peripheral select internal ready/busy status signal SRAM output enable signal
70/83
AN1154 APPLICATION NOTE
APPENDIX DESIGN FILE EPM7064S FIGURE
Title:8XX Tutorial-Discrete Solution Function:Replacement programmable logic portions M88x3Fxx Designed by:Dan Harris Design date:6/15/98 Description:This design shows what chip logic would required replace -programmable logic portions M8813F1x. This chip will responsible -for following tasks: Latching address generated 80C31 MCU. Decoding address generating internal/external chip selects. Storing control/status information internal registers. Address translation memory pageng. Interfacing controlling Receiver circuit, -RTC, SRAM, EEPROM, FLASH, MCU. Interfacing JTAG-compatible port ISP. Convention:The tilde used throughout this design indicate active signals. CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT PAGE_REG_ADDR H"09E0"; VM_REG_ADDR H"09E2"; MCU_IO_OUT_ADDR H"0902"; DESIRED_REG_ADDR H"0920"; GAIN_REG_ADDR H"0901"; START_SIG_ADDR H"0921";
subdesign 8XXtutor following signals generated (U1): A/D[7.0]: BIDIR;- Multiplexed address (lower byte)/data A[15.8]: INPUT;- Upper byte addr INPUT;- Read strobe INPUT;- Write strobe INPUT;- addr latch enable signal PSEN~ INPUT;- Program store enable System-level inputs: Reset~ INPUT;- System reset Clock INPUT;- System clock following signals generated (U1): AGC_Interrupt~: OUTPUT;- Interrupt when desired measured signal levels don't match
71/83
AN1154 APPLICATION NOTE
Trim OUTPUT;- True when measured level greater than desired Boost OUTPUT;- Opposite Trim chip select output (U5): RTC_CS~: OUTPUT; This signals to/from (U7): Start_Conversn: OUTPUT; Indicates when should start analog-todigital conversion ADC_Out[3.0]: INPUT; measured signal strength used gain (part PGA_Din[2.0]: OUTPUT; following outputs external memories: Chip selects FLASH_CS~: OUTPUT; EEPROM_CS~: OUTPUT; SRAM_CS~: OUTPUT; Output enables FLASH_OE~: OUTPUT; EEPROM_OE~: OUTPUT; SRAM_OE~: OUTPUT; Upper address bits FLASH_A[16.14]: OUTPUT;- addr bits 128K FLASH segmentation EEPROM_A[14.13]: OUTPUT;- addr bits EEPROM segmentation Latched/demultiplexed address output Addr_Out[7.0]: OUTPUT;- outputs external memories Control Output mode Control[2.0]: OUTPUT; VARIABLE A/D[7.0] TRI;- Needed drive data output onto data la[7.0] LATCH;- Must demux lower byte addr page_reg[7.0]: DFFE;- Page register vm_reg[7.0]: DFFE; Used memory mapping combined memory space mode desired_reg[3.0]: DFFE;- Register store desired signal level (set MCU) gain_reg[2.0]: DFFE; Register store gain level (set MCU) begin_comparrison: DFFE; takes state machine idle state (s0)
72/83
AN1154 APPLICATION NOTE
cntrl_port_reg[2.0]: DFFE;- mode control register addr[15.0]: NODE;- Demultiplexed addr fs[7.0] NODE;- FLASH segment enable signals ees[3.0] NODE; EEPROM segment enable signals swap NODE; page register enable_data_half: NODE;- page register measured[3.0]: NODE;- Output from desired[3.0]: NODE;- Input from meqd NODE;- True when measured value equals desired MACHINE WITH STATES (s0, s3); BEGIN Right now, there nothing output lines A/D[] GND; Latch addr[] la[] A/D[]; la[].ena ALE; addr[7.0] la[]; addr[15.8] A[]; Addr_Out[] la[]; begin_comparrison A/D7; begin_comparrison.clk Clock; begin_comparrison.clrn Reset~; begin_comparrison.ena !WR~ (addr[] START_SIG_ADDR); desired_reg[] A/D[7.4]; desired_reg[].clk Clock; desired_reg[].clrn Reset~; desired_reg[].ena !WR~ (addr[] DESIRED_REG_ADDR); gain_reg[] A/D[2.0]; gain_reg[].clk Clock; gain_reg[].clrn Reset~; gain_reg[].ena !WR~ (addr[] GAIN_REG_ADDR); cntrl_port_reg[] A/D[2.0]; cntrl_port_reg[].clk Clock; cntrl_port_reg[].clrn Reset~; cntrl_port_reg[].ena !WR~ (addr[] MCU_IO_OUT_ADDR); page_reg[] A/D[];
73/83
AN1154 APPLICATION NOTE
page_reg[].clk Clock; page_reg[].clrn Reset~; page_reg[].ena !WR~ (addr[] PAGE_REG_ADDR); vm_reg[] A/D[]; vm_reg[].clk Clock; vm_reg[].clrn Reset~; vm_reg[].ena !WR~ (addr[] VM_REG_ADDR); measured[] ADC_Out[]; desired[] desired_reg[]; PGA_Din[] gain_reg[]; Control[] cntrl_port_reg[]; Memory Section swap page_reg7; enable_data_half page_reg6; ((addr[] H"8000") (addr[] H"BFFF") (page_reg[] !swap) ((addr[] H"0000") (addr[] H"3FFF") swap); (addr[] H"4000") (addr[] H"7FFF"); (addr[] H"8000") (addr[] H"BFFF") (page_reg[] (addr[] H"C000") (addr[] H"FFFF") (page_reg[] (addr[] H"8000") (addr[] H"BFFF") (page_reg[] (addr[] H"C000") (addr[] H"FFFF") (page_reg[] (addr[] H"8000") (addr[] H"BFFF") (page_reg[] (addr[] H"C000") (addr[] H"FFFF") (page_reg[] ees0 ees1 ees2 ees3 ((addr[] H"0000") (addr[] H"1FFF") !swap) ((addr[] H"8000") (addr[] H"9FFF") swap !enable_data_half); ((addr[] H"2000") (addr[] H"3FFF") !swap) ((addr[] H"A000") (addr[] H"BFFF") swap !enable_data_half); (addr[] H"C000") (addr[] H"DFFF") swap enable_data_half; (addr[] H"E000") (addr[] H"FFFF") swap enable_data_half;
FLASH upper EEPROM upper address encoding FLASH_A16 FLASH_A15 FLASH_A14 EEPROM_A14 ees3 EEPROM_A13 ees3 fs4; fs2; fs1; ees2; ees1;
Chip Selects Output Enables
74/83
AN1154 APPLICATION NOTE
SRAM highest priority, followed EEPROM, then FLASH !FLASH_CS~ (fs0 fs7) (EEPROM_CS~ SRAM_CS~); !EEPROM_CS~ (ees0 ees1 ees2 ees3) SRAM_CS~; !SRAM_CS~ ((addr[] H"0100") (addr[] H"08FF")); !RTC_CS~ ((addr[] H"0A00") (addr[] H"0A1F")); !SRAM_OE~ !(!RD~ (!PSEN~ vm_reg0)); !EEPROM_OE~ !((!PSEN~ vm_reg1) (vm_reg3 !RD~)); !FLASH_OE~ !((!PSEN~ vm_reg2) (vm_reg4 !RD~)); Comparator Trim (measured[] desired[]); meqd (measured[] desired[]); Boost !Trim !meqd;
State Machine sm.clk Clock; sm.reset !Reset~; CASE WHEN Start_Conversn GND; AGC_Interrupt~ VCC; (begin_comparrison) THEN ELSE WHEN Start_Conversn VCC; WHEN Start_Conversn GND; WHEN !AGC_Interrupt~ Trim Boost;- Interrupt when Measured equal Desired CASE; END;
75/83
AN1154 APPLICATION NOTE
APPENDIX COMPARING DISCRETE INTEGRATED SOLUTIONS
This appendix compares circuits Figure Figure following categories:
Cost Average Current Usage Board Space Usage Time market
(Only major compared here.) COST M8813F1x PLCC package purchased significantly lower price than total cost individual EEPROM, Flash, SRAM, CPLD devices. AVERAGE CURRENT USAGE M88x3Fxx would typically 4.29 according "Example M88x3Fxx Typical Power Calculation Parameters" sections FLASH+PSD Data Sheet. take total average current devices discrete solution, 32.4 (with EPM7064S turbo mode). This shows that discrete solution uses 755% more current than PLD. BOARD SPACE USAGE M8813F1x PLCC package takes chips that make discrete solution take combined 1493 mm2. That equates 373% more board space. (All calculations have been based PLCC packages.) This calculation does reflect extra board space, complexity, noise associated with routing signals discrete solution. TIME MARKET time market will reduced significantly many reasons:
integrated solution involves complex integrated circuit, four. There templates predefined routines that, when used conjunction with user-friendly PSDsoft, help with every step your design process. Issues related concurrent memory, memory mapping, assisted simplified. code generated you. JTAG interface greatest benefits time savers. allows program, configure, test entire PSD, leave soldered board whole time. There just fewer places wrong, fewer things debug when have this level integration.
76/83
AN1154 APPLICATION NOTE
APPENDIX SYSTEM MEMORY UART
INTRODUCTION system memory developed this tutorial take full advantage memory available M8813F1x, expand beyond KByte address space limitation 8031 MCU. This memory facilitates downloading firmware from host computer Flash memory using 8031 UART. 8031 boots from EEPROM, concurrently downloads Flash memory, then 8031 execution jumps from EEPROM Flash memory. After this jump, EEPROM boot area address space replaced with Flash memory special register within (the Register). After that, entire Flash memory available 8031. This system memory also allows concurrent downloading boot code into EEPROM while executing code Flash memory. This possible non-PSD systems that PROM boot code. total memory available 8031 defined this system
KBytes Flash KBytes EEPROM boot code KBytes EEPROM data storage KBytes battery-backed SRAM addition bytes SRAM resident 8031)
SYSTEM MEMORY system memory shown Figure Figure Figure Figure labels EESx names internal memory segments within M8813F1x device. represents Kbyte Flash segments, EESx represents Kbyte EEPROM segments. this design, paging used because system contains more memory than 8031 address linearly. M8813F1x facilitates paging using page register, which 8031 access. Because paging used, common memory area needed firmware routines that must accessible regardless what page executing from. This common area resides lower half each memory page program space (shown Figure Figure Figure Figure 65). should contain routines that handle initialization, interrupts, implement page switching, drive physical devices. also used keep critical data space items available times. example, this design, control registers, I/O, system SRAM stack global variables available memory page (see Figure Figure Figure Figure 65). There fundamental modes operation: boot/download mode, other normal operation. Figure Figure Figure Figure show memory during transition from boot/download mode normal operation mode. Figure represents memory power-on (boot). system boots from EEPROM, then facilitate download main Flash memory needed) using 8031 UART. this point, Flash memory 8031 "data space" EEPROM 8031 "program space". This "MCU Configuration" that performed step section entitled "PSDsoft Configuration" page 20), shown Figure This step configuration automatically sets register 12h. Please refer FLASH+PSD Data Sheet information register settings. very important note that Configuration utility initialises register (located CSIOP space offset E2h), that only changed after booted. After Flash been programmed validated, Flash memory moved from 8031 data space
77/83
AN1154 APPLICATION NOTE
8031 program space writing register (while still executing EEPROM). Figure represents memory after Flash memory been moved program space. This intermediate step that result writing register. Next, 8031 execution jumps from EEPROM Flash memory. While executing from Flash memory, 8031 sets page register that call "SWAP". EEPROM that booted from, during power-up, replaced with Flash memory that contains application vectors code, shown Figure transition between maps Figure Figure under control 8031 setting "SWAP" inside (defined PSDabel, tutor8XX.abl, file). Again, state memory map, shown Figure intermediate step. Individual bits within 8-bit page register used functions other than memory page definition. example, this tutorial, eight page register bits define four memory pages, page register bits used "SWAP" bit, described above. Finally, while executing from Flash memory, 8031 must write register move EEPROM from 8031 program space 8031 data space. This finalizes memory map, shown Figure Now, KBytes Flash memory program space, with KBytes common area KBytes spread across three memory pages. Also, EEPROM data space, accessible from memory page. Notice that more EEPROM segments (EES2 EES3) appear Figure These segments general data while other EEPROM segments (EES0 EES1) contain 8031 power-on boot code. that system memory looks like that Figure another feature becomes available. Besides mechanisms mentioned, there more memory mapping control used this tutorial design. This bit, "ENABLE_DATA_HALF", another page register used protect boot code EES0 EES1 from inadvertent writes. same time, enables other half EEPROM (EES2 EES3) accessed general data. example, update boot code EES0 EES1 with code downloaded over UART, 8031 would leave ENABLE_DATA_HALF logic zero, perform update writing EES0 EES1, then ENABLE_DATA_HALF logic one. boot code inaccessible (protected while booting), data half EEPROM accessible. Figure System Memory 8031-M8813F1x, boot/download POWER-UP Register 12h)
PROGRAM SPACE (PSEN\)
PAGE FFFF PAGE PAGE
DATA SPACE (RD\)
PAGE PAGE FFFF
C000
NOTHING MAPPED
C000
NOTHING MAPPED
8000
8000
Execute from here
4000
4000
EES1
2000
NOTHING MAPPED NOTHING MAPPED NOTHING MAPPED NOTHING MAPPED
COMMON MEMORY ACROSS DATA PAGES
EES0
0000 SYSTEM SYSTEM SYSTEM SYSTEM
1000 0000
AI03300
78/83
AN1154 APPLICATION NOTE
Figure System 8031-M8813F1x, move Flash program space WRITE REGISTER
PROGRAM SPACE
PAGE FFFF PAGE PAGE PAGE
DATA SPACE
PAGE FFFF
C000
NOTHING MAPPED
C000
8000
NOTHING MAPPED
8000
COMMON MEMORY ACROSS PROGRAM PAGES
Execute from here
4000
4000
EES1
2000
EES1
EES1
EES1
1000 SYSTEM 0000
EES0
0000
EES0
EES0
EES0
AI03301
Figure System Memory 8031-M8813F1x, swap boot EEPROM with Flash segment SWAP
PROGRAM SPACE
PAGE FFFF PAGE PAGE PAGE
DATA SPACE
PAGE FFFF
C000
NOTHING MAPPED
C000
EES1 Execute from here
EES1
EES1
EES1
EES0
8000
EES0
EES0
EES0
NOTHING MAPPED
8000
COMMON MEMORY ACROSS PROGRAM PAGES
4000
4000
0000
1000 SYSTEM 0000
AI03302
79/83
AN1154 APPLICATION NOTE
Figure Final 8031-M8813F1x, move EEPROM data space WRITE REGISTER
PROGRAM SPACE
PAGE FFFF PAGE PAGE PAGE
DATA SPACE
PAGE FFFF
EES3
C000
EES2
C000
NOTHING MAPPED
EES1
8000
EES0
8000
COMMON MEMORY ACROSS PROGRAM PAGES
4000
NOTHING MAPPED
4000
0000
1000
SYSTEM
0000
AI03303
CODE PARTITIONING FLASH MEMORY PAGES Ultimately, will executing from Flash memory since EEPROM used boot-up this design. assume that have KBytes program space Flash memory, shown Figure KBytes code resides four areas: KBytes common area (FS0 FS1, accessible from page), KBytes page zero (FS2 FS3), KBytes page (FS4 FS5), KBytes page (FS6 FS7). 8031 never leaves page zero while executing, access KBytes Flash memory through well SRAM I/O. 8031 execution jumps Flash memory pages from call upper half page zero (FS2 FS3), care must taken leave path return page zero again. However, call page from routine lower half page zero (the common area, FS1), there problem returning from call. When placing code Flash memory upper half pages zero, one, two, software designer must break tasks into logical groups. These groups should need access code frequently other pages. (Most software split this manner result good modular design.) Since system SRAM available page, firmware routines that reside different pages pass data using global variables stack. designer create page-switching algorithms jump between tasks different pages. There many ways implement paging scheme: method involves table that contains addresses page numbers program tasks, which called from page page. table algorithms must reside portion Flash memory that located common area. This provides very clean paging solution, which implemented using high-level compiler. (The compiler from Keil supports this directly, creates tables you.) only penalty when using this method overhead experienced when switching from page another. this tutorial design, five different files from cross-compiler linker used program sections M8813F1x. These dummy files with code them, present illustrate merging firmware with configuration during Address Translate operation. this were real design, file common.hex would contain common functions interrupt vectors, would programmed into FS0/FS1. Three more files from linker, page_0.hex, page_1.hex, page_2.hex would contain partitioned code described above. such, these three files would programmed into segments FS2/FS3, FS4/FS5, FS6/FS7, respectively. Finally, file boot.hex,
80/83
AN1154 APPLICATION NOTE
containing power-up boot code programming algorithms Flash memory, would programmed into EES0/EES1. START-UP SEQUENCES, UART DOWNLOADS assume that lap-top used host download firmware this embedded system over RS-232 UART channel (instead JTAG). These download actions program main Flash memory very first time; update main Flash after been programmed once; update boot code after being programmed first time device programmer JTAG link. There valid boot-up arrangements (labelled respectively: that must handled system power-up (reset). default setting register power-up places main Flash memory data space EEPROM program space. Please refer memory maps Figure Figure Figure Figure RS-232 cable attached, main Flash valid 8031 action: Boot from EES0/EES1 checksum Flash memory Check UART pending host download request main Flash (Figure register main Flash into program space (Figure SWAP PSD, which swaps EES0/EES1 with (Figure register EEPROM into data space (Figure Now, system normal operating mode. More 8031 action: Check UART host download request boot memory ENABLE_DATA_HALF boot download request exists Normal application code executed from main Flash memory. RS-232 cable attached, main Flash valid, download demands from host Action: same step "a.", above. RS-232 cable attached, main Flash valid, download main Flash demanded host 8031 action: Boots from EES0/EES1 checksum Flash memory Check UART pending host download request main Flash (Figure Program main Flash memory with data from UART register main Flash into program space (Figure SWAP PSD, which swaps EES0/EES1 with (Figure register EEPROM into data space (Figure Now, system normal operating mode. More 8031 action: Check UART host download request boot memory ENABLE_DATA_HALF boot download request exists Normal application code executed from main Flash memory.
81/83
AN1154 APPLICATION NOTE
RS-232 cable attached, main Flash blank invalid 8031 action: Boot from EES0/EES1 checksum Flash memory Check UART pending host download request main Flash (Figure Wait until UART traffic present (Figure RS-232 cable attached, main Flash blank invalid 8031 action: Boot from EES0/EES1 checksum Flash memory Check UART pending host download request main Flash (Figure Program main Flash memory with data from UART register main Flash into program space (Figure SWAP PSD, which swaps EES0/EES1 with (Figure register EEPROM into data space (Figure Now, system normal operating mode. More 8031 action: Check UART host download request boot memory ENABLE_DATA_HALF boot download request exists Normal application code executed from main Flash memory. RS-232 cable attached, main Flash valid, system requests download boot memory 8031 action: Boot from EES0/EES1 checksum Flash memory Check UART pending host download request main Flash (Figure register main Flash into program space (Figure SWAP PSD, which swaps EES0/EES1 with (Figure register EEPROM into data space (Figure Now, system normal operating mode. More 8031 action: Check UART host download request boot memory Program EEPROM boot memory EES0 EES1 with data from UART checksum EES0 EES1 ENABLE_DATA_HALF protect boot code EES0 EES1 from inadvertent writes Enable data access EES2 EES3 Normal application code executed from main Flash memory. these host UART download options, assumed that normal boot (EES0/EES1) area programmed very first time device programmer before installed circuit card JTAG interface while in-system.
82/83
AN1154 APPLICATION NOTE
current information FLASH+PSD products, please consult pages world wide web: www.st.com/flashpsd have questions suggestions concerning matters raised this document, please send them following electronic mail addresses:
apps.flashpsd@st.com ask.memory@st.com
(for application support) (for general enquiries)
Please remember include your name, company, location, telephone number number.
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. 2000 STMicroelectronics Rights Reserved logo registered trademark STMicroelectronics. other names property their respective owners. STMicroelectronics GROUP COMPANIES Australia Brazil China Finland France Germany Hong Kong India Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom U.S.A. http://www.st.com
83/83
Other recent searches
TC0173A - TC0173A TC0173A Datasheet
STPRA2020CTW - STPRA2020CTW STPRA2020CTW Datasheet
ST10X167 - ST10X167 ST10X167 Datasheet
F168 - F168 F168 Datasheet
REJ03C0043-0200Z - REJ03C0043-0200Z REJ03C0043-0200Z Datasheet
NP36N055HHE - NP36N055HHE NP36N055HHE Datasheet
NP36N055IHE - NP36N055IHE NP36N055IHE Datasheet
CLK32 - CLK32 CLK32 Datasheet
2SK2649-01R - 2SK2649-01R 2SK2649-01R Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
