Product data File under Integrated Ciruits ICL03 2001 Product dat
|
|
|
Top Searches for this datasheet
GTLPH16612 18-bit GTLP LVTTL/TTL bidirectional universal translator (3-State)
Product data File under Integrated Ciruits ICL03 2001
Product data
18-bit GTLP LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
FEATURES
18-bit bidirectional interface Translates between GTLP logic levels ports) LVTTL/TTL Edge rate control circuitry outputs rising/falling edges tolerant LVTTL side current loading when LVTTL output tied 3-State buffers Output capability: mA/-32 LVTTL side; LVTTL input levels control pins Power-up reset Power-up 3-State Positive edge triggered clock inputs Latch-up protection exceeds JESD78 protection exceeds 2000 JESD22-A114,
JESD22-A115 exceeds 1000 JESD22-C101 GTLP side minimize system noise multipoint backplane environment logic levels ports)
DESCRIPTION
GTLPH16612 high-performance BiCMOS product designed operation 3.3V with compatibility GTLPH16612 unique that connect this device used replacement device sockets where 3.3/5 BIAS VCC. This device 18-bit universal transceiver featuring non-inverting 3-State compatible outputs both send receive directions. Data flow each direction controlled output enable (OEAB OEBA), latch enable (LEAB LEBA), clock (CPAB CPBA) inputs. A-to-B data flow, device operates transparent mode when LEAB High. When LEAB Low, data latched CPAB held High logic level. LEAB Low, A-bus data stored latch/flip-flop Low-to-High transition CPAB. When OEAB Low, outputs active. When OEAB High, outputs high-impedance state. clocks controlled with clock-enable inputs (CEBA/CEAB). Data flow B-to-A similar that A-to-B uses OEBA, LEBA CPBA.
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CI/O CI/O ICCZ PARAMETER Propagation delay Input capacitance (Control pins) capacitance capacitance Total supply current VI/O VI/O Outputs disabled CONDITIONS Tamb TYPICAL UNIT
ORDERING INFORMATION
PACKAGES 56-Pin Plastic SSOP 56-Pin Plastic TSSOP TEMPERATURE RANGE ORDER CODE GTLPH16612DL GTLPH16612DGG NUMBER SOT371-1 SOT364-1
NOTE: Standard packing quantities other packaging data available
2001
853-2285 27174
Product data
18-bit GTLP LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
CONFIGURATION
OEAB LEAB OEBA LEBA CEAB CPAB VREF CPBA CEBA
DESCRIPTION
NUMBER SYMBOL OEAB/OEBA CEBA/CEAB LEAB/LEBA CPAB/CPBA NAME FUNCTION A-to-B/ B-to-A Output enable input (active Low) B-to-A/A-to-B clock enable A-to-B/B-to-A Latch enable input A-to-B/B-to-A Clock input (active rising edge) Data inputs/outputs side)
A0-A17
B0-B17
Data inputs/outputs side)
VREF
Ground (0V) Positive supply voltage GTLP reference voltage connect
SW00486
2001
Product data
18-bit GTLP LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
FUNCTION TABLE
INPUTS CEAB OEAB LEAB CPAB OUTPUT Trans arent Transparent Clocked storage data MODE Isolation
Latched storage data Clock inhibit
Don't care High voltage level voltage level High High impedance "off state A-to-B data flow shown: B-to-A flow similar uses OEBA, LEBA, CPBA, CEBA. condition when OEAB OEBA both same time recommended. Output level before indicated steady-state input conditions were established. Output level before indicated steady-state input conditions were established, provided that CPAB before LEAB went Low.
LOGIC SYMBOL (Positive Logic)
VREF
OEAB
CEAB
CPAB
LEAB
LEBA
CPBA
CEBA
OEBA
other channels
SW00894
2001
Product data
18-bit GTLP LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
ABSOLUTE MAXIMUM RATINGS1,
SYMBOL Tstg PARAMETER supply voltage input diode current input voltage3 output diode current output voltage3 Current into output state Current into output HIGH state Storage temperature range port port port Output High state; port Output High state; port port port port CONDITIONS RATING -0.5 +4.6 -0.5 +7.0 -0.5 +4.6 -0.5 +7.0 -0.5 +4.6 +150 UNIT
NOTES: Stresses beyond those listed cause permanent damage device. These stress ratings only functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. performance capability high-performance integrated circuit conjunction with thermal environment create junction temperatures which detrimental reliability. maximum junction temperature this integrated circuit should exceed input output negative voltage ratings exceeded input output clamp current ratings observed.
RECOMMENDED OPERATING CONDITIONS1,
SYMBOL VREF t/VCC Tamb PARAMETER supply voltage Termination voltage reference voltage Input voltage HIGH-level HIGH level input voltage LOW-level level input voltage HIGH-level output current LOW-level output current Input transition rise fall rate Power-up rate Operating free-air temperature range GTLP GTLP port Except port port Except port port Except port port port, port, GTLP port Outputs enabled TEST CONDITIONS 3.3V RANGE LIMITS 1.14 1.35 0.74 VREF+50mV 1.26 1.65 0.87 1.10 Note VREF-50mV UNIT ns/V µs/V
NOTES: Normal connection sequence first; VCC, I/O, control inputs, VREF (any order) last. VREF adjusted optimize noise margins, normally two-thirds VTT. adjusted accommodate backplane impedances recommended ratings exceeded absolute rating exceeded.
2001
Product data
18-bit GTLP LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
ELECTRICAL CHARACTERISTICS (3.3 "0.3 RANGE)
LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp Input clamp voltage High-level High level output voltage -100 Low-level output voltage Input leakage current IOFF IHOLD IPU/PD ICCH ICCL ICCZ5 ICCH ICCL CI/O CI/O Additional supply current input pin2 Control pins capacitance capacitance capacitance B-Port Port Outputs input VCC-0.6 Other inputs VI/O VI/O 0.04 12.0 7.36 Output current Hold current outputs current, Current into output High state when Power up/down 3-State output current3 A-Port Port Outputs Disabled Outputs high VCC; 10.5 18.5 11.5 17.5 port port Data pins4 port port Control pins -140 port 0.55 ±100 ±100 port VCC-0.2 TYP1 -0.85 0.07 0.25 -1.2 UNIT
VCC; Don't care Outputs high
NOTES: typical values Tamb This increase supply current each LVTTL input specified voltage level other than This parameter valid between with transition time msec. From transition time µsec permitted. This parameter valid Tamb only. Unused pins GND. ICCZ measured with outputs pulled pulled down ground. maximum capacitance based simulation data.
2001
Product data
18-bit GTLP LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
CHARACTERISTICS PORT)
Tamb GTLP GTLPH16612 Port ±0.3 VREF SYMBOL Fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPHZ tPZL tPLZ LEBA LEBA CPBA CPBA OEBA OEBA OEBA OEBA PARAMETER WAVEFORM TYP1 UNIT
NOTE: Typical values Tamb
CHARACTERISTICS PORT)
Tamb GTLP GTLPH16612 Port ±0.3 VREF SYMBOL Fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL trise tfall LEAB LEAB CPAB CPAB OEAB OEAB Transition time outputs Transition time outputs PARAMETER WAVEFORM TYP1 UNIT
NOTE: Typical values Tamb
2001
Product data
18-bit GTLP LVTTL/TTL bidirectional universal translator (3-State)
SETUP REQUIREMENTS (3.3 ±0.3 RANGE)
GTLPH16612
Port: Input Tamb VREF Port: Input VREF LIMITS SYMBOL DESCRIPTION PARAMETER WAVEFORM tw(H) tw(H ts(H ts(H) ts(L) ts(H ts(H ts(L) ts(L) th(H th(H th(H th(H th(H) th(H) Pulse duration Pulse duration Setup time Setup time Setup time Setup time Setup time Setup time Setup time Hold time Hold time Hold time Hold time Hold time Hold time LEAB LEBA CPAB CPBA before CPAB rising edge before CPBA rising edge before CPBA rising edge before LEAB falling edge before LEBA falling edge CEAB before CPAB rising edge CEBA before CPBA rising edge after CPAB rising edge after CPBA rising edge after LEAB falling edge after LEBA falling edge CEAB after CPAB rising edge CEBA after CPBA rising edge ±0.3 UNIT
2001
Product data
18-bit GTLP LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
WAVEFORMS
ports control pins; ports GTLP mode.
1/fMAX VCC, whichever less OEBA VCC, whichever less
CPBA CPAB
tW(L) tPHL tW(H) tPLH
tPZH
tPHZ
SW00181
SW00223
Waveform Propagation delay, clock input output, clock pulse width, maximum clock frequency
VCC, whichever less tPLH tPHL
Waveform 3-State output enable time high level output disable time from high level
OEBA VCC, whichever less
tPZL
tPLZ
SW00176
SW00224
Waveform Propagation delay, transparent mode
Waveform 3-State output enable time level output disable time from level
OEAB VCC, whichever less
LEAB LEBA
VCC, whichever less
tW(H) tPHL tPLH tPLH tPHL
SW00177
SW00495
Waveform
Propagation delay, enable output, enable pulse width
Waveform
Output enable time open collector output with pull-up
CEAB CEBA
VCC, whichever less
CPAB CPBA, LEAB LEBA
2001
tS(H) th(H) tS(L) th(L)
VCC, whichever less SW00222
Waveform Data setup hold times
Product data
18-bit GTLP LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
TEST CIRCUIT
Open
D.U.T. VOUT
NEGATIVE PULSE tTHL (tF) tTLH (tR)
PULSE GENERATOR
tTLH (tR) tTHL (tF)
Test Circuit Outputs
FROM OUTPUT UNDER TEST (INCLUDES PROBE CAPACITANCE) TEST POINT
POSITIVE PULSE
Input Waveforms
Load Circuit Outputs
SWITCH POSITION
TEST tPLZ/tPZL tPLH/tPHL tPHZ/tPZH SWITCH Open
DEFINITIONS
Load resistor; CHARACTERISTICS value. Load capacitance includes probe capacitance: CHARACTERISTICS value. Termination resistance should equal ZOUT pulse generators. GTLP FAMILY Amplitude
INPUT PULSE REQUIREMENTS Rep. Rate
whichever less
v2.5 v2.5
SW00255
2001
Product data
18-bit GTLP LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
SSOP56: plastic shrink small outline package; leads; body width
SOT371-1
2001
Product data
18-bit GTLP LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
TSSOP56: plastic thin shrink small outline package; leads; body width
SOT364-1
2001
Product data
18-bit GTLP LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
NOTES
2001
Product data
18-bit GTLP LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
Data sheet status
Data sheet status Objective data Preliminary data Product status Development Qualification Definitions This data sheet contains data from objective specification product development. Philips Semiconductors reserves right change specification manner without notice. This data sheet contains data from preliminary specification. Supplementary data will published later date. Philips Semiconductors reserves right change specification without notice, order improve design supply best possible product. This data sheet contains data from product specification. Philips Semiconductors reserves right make changes time order improve design, manufacturing supply. Changes will communicated according Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
Please consult most recently issued data sheet before initiating completing design. product status device(s) described this data sheet have changed since this data sheet published. latest information available Internet
Definitions
Short-form specification data short-form specification extracted from full data sheet with same type number title. detailed information relevant data sheet data handbook. Limiting values definition Limiting values given accordance with Absolute Maximum Rating System (IEC 60134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Applications that described herein these products illustrative purposes only. Philips Semiconductors make representation warranty that such applications will suitable specified without further testing modification.
Disclaimers
Life support These products designed life support appliances, devices systems where malfunction these products reasonably expected result personal injury. Philips Semiconductors customers using selling these products such applications their risk agree fully indemnify Philips Semiconductors damages resulting from such application. Right make changes Philips Semiconductors reserves right make changes, without notice, products, including circuits, standard cells, and/or software, described contained herein order improve design and/or performance. Philips Semiconductors assumes responsibility liability these products, conveys license title under patent, copyright, mask work right these products, makes representations warranties that these products free from patent, copyright, mask work right infringement, unless otherwise specified.
Contact information
additional information please visit Fax: 24825
Koninklijke Philips Electronics N.V. 2001 rights reserved. Printed U.S.A. Date release: 09-01
sales offices addresses send e-mail
Document order number:
9397 08911
2001
Other recent searches
P0120002P - P0120002P P0120002P Datasheet
MAX7317 - MAX7317 MAX7317 Datasheet
MAX6966 - MAX6966 MAX6966 Datasheet
MAX6967 - MAX6967 MAX6967 Datasheet
KSN-2554A-119+ - KSN-2554A-119+ KSN-2554A-119+ Datasheet
IXTH02N250 - IXTH02N250 IXTH02N250 Datasheet
IXTV02N250S - IXTV02N250S IXTV02N250S Datasheet
EN5866 - EN5866 EN5866 Datasheet
DPC34-300 - DPC34-300 DPC34-300 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
