8-bit Micro Application Team AVOIDING SPURIOUS INTERRUPT DURING R

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

8-bit Micro Application Team AVOIDING SPURIOUS INTERRUPT DURING R

Datasheet Thumbnail

Top Searches for this datasheet

NOTES USING ST623XB/ST628XB UART
8-bit Micro Application Team
AVOIDING SPURIOUS INTERRUPT DURING RESET
Care must taken during RESET, reception RXD/PD4 line stuck zero. this case, high-to-low transition will latched inside UART cell RESET structure, even real falling edge occured RXD/PD4 line. This active falling edge will acknowledged UART cell valid receive start bit. UART clocks clocks bit) then needed receive burst bits start data parity stop bit). Receive Interrupt flag RXRDY (bit7 UART Control Register) after bits have been received enabled, Receive interrupt generated. avoid this early UART interrupt, enabling UART receive interrupt should ONLY occur after software delay sequence insterted just after RESET jump instruction. RXRDY flag must also cleared before when enabling UART Receive Interrupt first time. length time delay depends selected operating Baud rate (bit BR2.BR0 UART Control Register). following tables show required timing with respect selected baud rate:
0.00 0.00 0.00 0.00 1.00 1.00 1.00 1.00 0.00 0.00 0.00 0.00 1.00 1.00 1.00 1.00 0.00 0.00 1.00 1.00 0.00 0.00 1.00 1.00 0.00 0.00 1.00 1.00 0.00 0.00 1.00 1.00 0.00 1.00 0.00 1.00 0.00 1.00 0.00 1.00 0.00 1.00 0.00 1.00 0.00 1.00 0.00 1.00 FOSC division 6656 3328 1664 RESERVED FOSC division 6656 3328 1664 RESERVED FOSC=8MHz 1200 2400 4800 9600 19200 31200 38400 RESERVED FOSC=4MHz 1200 2400 4800 9600 15600 19200 RESERVED Time Delay Required 9.6ms 4.8ms 2.4ms 1.2ms 600µs 400µs 300µs RESERVED Time Delay Required 19.2ms 9.6ms 4.8ms 2.4ms 1.2ms 740µs 600µs RESERVED
AN1016/1098
AVOIDING SPURIOUS INTERRUPT DURING RESET
following delay loop sequence proposed
Reset Uartcr, Select faster Baud rate (Uart control reg.) count, 03h; count 01h, tempo takes approximately call tempo; 100us. this example, time 300us FOSC 8MHz Start Uartcr, 30h; clear RXRDY flag (bit7) enable UART interrupts
tempo count; total temporisation: 62cyc*count 8cyc 8cyc endtemp loop1 loop2 need 62cyc 100us FOSC 8Mhz jrnz loop2 count jrnz loop1 endtempret
.org 0FFEh Reset
IMPORTANT NOTES: configuration (BR2=1, BR1=1, BR0=0) faster baud rate should chosen after reset order short time delay. This early UART receive interrupt feature used detect after reset RXD/PD4 line (stuck '0') not.
AVOIDING SPURIOUS INTERRUPT DURING RESET
"THE PRESENT NOTE WHICH GUIDANCE ONLY AIMS PROVIDING CUSTOMERS WITH INFORMATION REGARDING THEIR PRODUCTS ORDER THEM SAVE TIME. RESULT, STMICROELECTRONICS SHALL HELD LIABLE DIRECT, INDIRECT CONSEQUENTIAL DAMAGES WITH RESPECT CLAIMS ARISING FROM CONTENT SUCH NOTE AND/OR MADE CUSTOMERS INFORMATION CONTAINED HEREIN CONNEXION WITH THEIR PRODUCTS."
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics ©1998 STMicroelectronics Rights Reserved. Purchase Components STMicroelectronics conveys license under Philips Patent. Rights these components system granted provided that system conforms Standard Specification defined Philips. STMicroelectronics Group Companies Australia Brazil Canada China France Germany Italy Japan Korea Malaysia Malta Mexico Morocco Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U.S.A. http://www.st.com

8-bit Micro Application Team AVOIDING SPURIOUS INTERRUPT DURING R

Top Searches for this datasheet

Other recent searches