HEF4069UB gates inverter Product specification File under Integra

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HEF4069UB gates inverter Product specification File under Integra

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IC04 LOCMOS HE4000B Logic Family Specifications HEF, IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,
HEF4069UB gates inverter
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
inverter
DESCRIPTION HEF4069UB general purpose inverter. Each inverters single stage.
HEF4069UB gates
Fig.2 Pinning diagram.
HEF4069UBP(N): HEF4069UBD(F): HEF4069UBT(D):
14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) 14-lead plastic (SOT108-1)
Package Designator North America Fig.1 Functional diagram.
FAMILY DATA, LIMITS category GATES Family Specifications VIH/VIL unbuffered stages
Fig.3 Schematic diagram (one inverter).
January 1995
Philips Semiconductors
Product specification
inverter
CHARACTERISTICS Tamb input transition times Propagation delays HIGH HIGH Output transition times HIGH HIGH tTLH tTHL tPLH tPHL SYMBOL TYP. MAX.
HEF4069UB gates
TYPICAL EXTRAPOLATION FORMULA (0,55 ns/pF) (0,23 ns/pF) (0,16 ns/pF) (0,55 ns/pF) (0,23 ns/pF) (0,16 ns/pF) (1,0 ns/pF) (0,42 ns/pF) (0,28 ns/pF) (1,0 ns/pF) (0,42 ns/pF) (0,28 ns/pF)
Dynamic power dissipation package
TYPICAL FORMULA (µW) (foCL) VDD2 (foCL) (foCL) VDD2 VDD2 where input freq. (MHz) output freq. (MHz) load capacitance (pF) (foCL) outputs supply voltage
January 1995
Philips Semiconductors
Product specification
inverter
HEF4069UB gates
Fig.4
Typical transfer characteristics; (drain current);
Fig.5
Typical transfer characteristics; (drain current);
Fig.6
Typical transfer characteristics; (drain current);
January 1995
Philips Semiconductors
Product specification
inverter
APPLICATION INFORMATION Some examples applications HEF4069UB shown below.
HEF4069UB gates
Fig.7 astable relaxation oscillator given. oscillation frequency mainly determined R1C1, provided R2C2 R1C1.
function minimize influence forward voltage across protection diodes frequency; stray (parasitic) capacitance. period given which R1C1 R1C1 where signal threshold level inverter. period fairly independent VDD, temperature. duty factor, however, influenced VST.
Fig.7
Astable relaxation oscillator using HEF4069UB inverters; diodes BAW62; parasitic capacitance. Waveforms points marked circuit diagram.
January 1995
Philips Semiconductors
Product specification
inverter
HEF4069UB gates
This inverter added amplify oscillator output voltage level sufficient drive other LOCMOS circuits.
Fig.8 Crystal oscillator frequencies MHz, using HEF4069UB inverters.
Fig.9
Voltage gain (VO/VI) function supply voltage.
Fig.10 Supply current function supply voltage.
also example analogue amplifier using HEF4069UB.
Fig.11 Test set-up measuring graphs Figs
January 1995
Philips Semiconductors
Product specification
inverter
HEF4069UB gates
Fig.12 Test set-up measuring forward transconductance dio/dvi constant (see also graph Fig.13).
average, average average where: observed standard deviation.
Fig.13 Typical forward transconductance function supply voltage Tamb
January 1995

HEF4069UB gates inverter Product specification File under Integra

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