L64733C/734 chipset designed satellite broadcast digital compliant wit
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L64733C/L64734 Tuner Satellite Receiver Chipset
L64733C/734 chipset designed satellite broadcast digital compliant with European digital video broadcast (DVB-S) standard, well technical specifications systems. L64733C/734 chipset forms complete "L-band-to-bits" system. typical application L64733C/734 chipset satellite digital reception accordance with standard. Figure shows L64733C/734 chipset satellite receiver implemented typical satellite receiver set-top decoder. Figure Set-Top Block Diagram
VCXO
FLASH
SDRAM-B
SDRAM-A
Expansion Analog Audio Analog CVBS Analog Analog Digital Video
Satellite Signal
L64733C Tuner
L64734 Demodulator
AMPs SC2000 Single-Chip Source Decoder
Serial
IEEE 1284
Smart Cards
RS232-C Interface
CODEC
GPIO Pins
L64733C Tuner directly down-converts satellite signal from L-band baseband; includes on-chip synthesizer. Using frequency information programmed into configuration registers, L64734 Satellite Receiver generates control signals L64733C synthesizer. L64734 also controls programming low-pass filters
February 2001
Copyright 2000, 2001 Logic Corporation. rights reserved.
L64733C generates dual automatic gain control (AGC) voltages two-stage automatic gain control L64733C. simplified chipset block diagram shown Figure Figure
Select Input Output
Switch
L64733C/734 Simplified Block Diagram
L64733C
Mixer, Down Conversion
Baseband Filter
Control Signals Control Modules Synthesizer Filter
IOUT QOUT L64734
Dual
Demodulator
Host Microcontroller
Microcontroller Interface
Error Correction
Descrambler
MPEG Output
Figure shows more detailed chipset block diagram. L64733C accepts L-Band signal input from satellite noise block (LNB) feed. L64733C handles fully loaded raster transponder signals from 2175 MHz. internally matched requires matching network between cable connector L64733C input pins, except DC-blocking capacitor. L64733C uses L64734 INSEL signal select appropriate function (Normal Loop-Through Mode).
L64733C/L64734 Tuner Satellite Receiver Chipset
Figure
Detailed Chipset Block Diagram
L64733C Xtal Switch Phase Detect. Charge Pump external Loop Filter
4-7.26 Tank Circuit LOBUF LODIV
Quadrature Down-Converter
÷32/33 ÷1/2
FDOUB INSEL
PSOUT
PLLIN
FLCLK
QOUT
AGC1
AGC2
L64734 Synthesizer Control Module Control Carrier Loop Control BPSK/QPSK Demodulator Timing Loop Control Filter Control Module
Dual Interpolator/Decimation Filter Matched Filter
Output Control
Microcontroller Data Address (from L64734 on-chip PLL) Decoder Pipeline External Microcontroller Interface
Microcontroller Data Address Channel Output (MPEG-2 Transport Stream)
Descrambler
ReedSolomon Decoder
Convolutional Deinterleaver
ReedSolomon Synchronizer
Viterbi Decoder
Viterbi Synchronizer
L64733C/L64734 Tuner Satellite Receiver Chipset
IOUT
signal sent variable gain stage controlled L64734 AGC1 signal. L64734 adjusts AGC1 conjunction with AGC2 maximize signal while maintaining proper levels baseband outputs (IOUT QOUT). signal then mixers quadrature demodulator. mixers with local oscillator signals that offset degrees from another. quadrature demodulator converts frequency signal directly baseband while splitting signal into quadrature signal paths. baseband signals pass through pair variable gain amplifiers, controlled through AGC2 L64734. signals then pass through pair seventh-order filters antialiasing. filter shape seventh-order Butterworth, followed single-pole delay equalizer. L64734 FLCLK signal controls filter cutoff frequency, which related baud rate. filtered baseband output signals differential output stages IOUTp, IOUTn, QOUTp, QOUTn. baseband outputs L64733C sent L64734 digitized analog-to-digital converter (ADC). Then, they sent BPSK/QPSK demodulator, filtered, sent L64734 forward error correction (FEC) decoder pipeline, which outputs MPEG-2 transport stream. frequency synthesizer functionality split between L64733C L64734. Synthesizer Control Module resides L64734 generates control signals L64733C Tuner frequency synthesizer. Synthesizer Control Module also contains programmable counters synthesizer feedback loop. L64733C provides analog functions frequency synthesizer, local oscillator, crystal reference oscillator. Tuning oscillator signals generated mixers 925-2175 range, with 0.625 step size when using crystal reference. on-chip tuning frequency 543-1088 MHz. tune channels from 925-1086 MHz, L64734 disables frequency doubler block) L64733C. tune channels from 1086-2175 MHz, L64734 enables frequency doubler. L64733C improve half-harmonic rejection. requires special programming frequency doubler control (FDOUB), which
L64733C/L64734 Tuner Satellite Receiver Chipset
3-state operation (see "Synthesizer Control Interface" section page 20). requires external resonant tank circuit, which includes varactor diodes vary frequency oscillation. signal Prescaler block before being passed deferentially through PSOUTp PSOUTn pins L64734. L64734 MODp MODn differential signals control divider ratio Prescaler block. L64734 dynamically changes divide ratio ensure that tuning step size affected divider. L64734 contains programmable counters further divide signal frequency before back L64733C through PLLINp PLLINn pins. crystal reference oscillator frequency divided eight phase detector. phase detector generates current signal proportional difference phase between PLLINp, PLLINn, divided crystal frequency. charge pump circuit generates current that controls pins external transistor buffer L64733C against tuning voltage current passed through discrete loop filter converted tuning voltage that drives external varactor diodes tank circuit. frequency controlled loop formed. Changing frequency divider ratios L64734 registers varies frequency. Figure page more details regarding external circuitry VCO, crystal oscillator, charge pump, tank circuitry, frequency-controlled loop. chipset provides maximum integration flexibility system designers minimum cost. number external components required build system minimal because synthesizer, variable rate filters, clock carrier loops integrated into devices.
L64733C/L64734 Tuner Satellite Receiver Chipset
Features Benefits
following subsections provide list system chipset features.
System Features
Direct down-conversion Integrated programmable cut-off low-pass filters variable-rate operation Dual optimizing performance with respect intermodulation noise Integrated synthesizer Integrated quadrature amplitude phase imbalance compensation Loop-Through
Chipset Features
system specifications support BPSK/QPSK demodulation rates from Mbaud Matched filter (square root raised cosine filter with roll factor 35%) Antialiasing filters operation from MBaud without switching external filters need low-pass filters On-chip digital clock synchronization On-chip digital carrier synchronization, featuring frequency sweep capability signal acquisition Autoacquisition demodulator mode tuner control through on-chip microcontroller Integrated Phase-Locked Loop (PLL) clock synthesis, allowing fundamental mode crystal Fast channel switching mode Power estimation Programmable Viterbi decoder module rates 1/2, 2/3, 3/4, 5/6, 6/7,
L64733C/L64734 Tuner Satellite Receiver Chipset
(204/188), (146/130) Reed-Solomon decoder Autosynchronization Viterbi decoder Programmable synchronization deinterleaver, Reed-Solomon decoder, descrambler error monitoring channel performance measurements Deinterleaver (DVB DSS) Serial host interface compatible with Logic Serial Control interface Power-down mode On-chip dual differential 6-bit ADCs Supports Synchronous Parallel Interface protocol data output
Chipset Interconnections
Figure illustrates signals between L64733C L64734.
L64733C/L64734 Tuner Satellite Receiver Chipset
Figure
Chipset Interconnection Diagram
L64734 AGC1 AGC2 CPG1 CPG2 FDOUB FLCLK INSEL MODp MODn PLLINp PLLINn XTLOUT AGC1 AGC2 XCTR[0] XCTR[1] FDOUB FLCLK INSEL MODp MODn PLLINp PLLINn XOIN PSOUTp PSOUTn IVINp IVINn QVINp QVINn Prescaler Signals
L64733C
Control Signals
Control Signals
Prescaler Signals
PSOUTp PSOUTn IOUTp IOUTn QOUTp QOUTn
Channel Data Signals
Channel Data Signals
L64733C Signal Descriptions
This section describes L64733C signals. Figure shows interface diagram L64733C. suffix (for example, ERROROUTn) designates active signal. Names differential signals designated with suffix noninverting side (for example, QOUTp), with suffix inverting side (for example, QOUTn).
L64733C/L64734 Tuner Satellite Receiver Chipset
Figure
L64733C Interface Diagram
RFINn AGC1 AGC2 CPG1 CPG2 FDOUB FLCLK IDCp IDCn INSEL LOBUF LODIV MODp MODn PLLINp PLLINn QDCp QDCn
Signals
RFINp RFOUT XTLn XTLp XTLOUT CFLT TANKn TANKp VRLO IOUTn IOUTp QOUTn QOUTp PSOUTn PSOUTp
Oscillator Signals
Control Signals
Channel Data Signals
Prescaler Signals
Charge Pump Signals
shown Figure L64733C following major interfaces:
Oscillator Channel Data Prescaler Control Charge Pump
following signal descriptions listed according major interface groups.
Signals
L64733C accept input signal loop RFOUT, determined on-chip switch.
L64733C/L64734 Tuner Satellite Receiver Chipset
RFINp, RFINn Input Input RFIN differential signals form input. Connect RFINp signal through series capacitor video connector RFINn signal through series resistor capacitor ground. RFOUT Output Output RFOUT signal output that active when INSEL input deasserted. When active, signal RFOUT copy RFIN signal.
Oscillator Signals
L64733C internal oscillators, crystal oscillator tank oscillator. CFLT Bias Voltage Bypass Bidirectional Connect CFLT shown Figure page
TANKp, TANKn Oscillator Tank Port Input Connect TANKp TANKn pins shown Figure page VRLO XTLp, XTLn Local Oscillator Regulator Bypass Bidirectional Connect VRLO shown Figure page Crystal Oscillator Port Input Connect XTLp XTLn pins shown Figure page Crystal Output This signal provides buffered clock reference frequency driving L64734 XOIN pin.
XTLOUT
Channel Data Signals
following signals channel data signals from L64733C L64734. IOUTp, IOUTn Channel Baseband Data Output IOUT differential signals form in-phase data provided L64734.
L64733C/L64734 Tuner Satellite Receiver Chipset
QOUTp, QOUTn Channel Baseband Data Output QOUT differential signals form quadrature-phase data provided L64734.
Prescaler Signals
following signals prescaler outputs from L64733C L64734. PSOUTp, PSOUTn Prescaler Output When LOBUF signal LOW, PSOUT differential signals L64733C prescaler outputs. When LOBUF HIGH, Local Oscillator (LO) buffer feeds PSOUT differential signals. programmable counters L64734 clocked rising edge PSOUT signal.
Control Signals
following signals, some which generated L64734 control mode operation L64733C AGC1 Automatic Gain Control Input AGC1 signal high-impedance input from L64734 that controls circuitry. AGC1 voltage range Automatic Gain Control Input AGC2 signal high-impedance input from L64734 that controls circuitry. Charge Pump Gain CPG[2:1] signals charge pump gain according table below.
Charge Pump Current (typ), CPG1 CPG2 HIGH -0.1 -0.3 -0.6 -1.8
AGC2
CPG[2:1]
Input
L64733C/L64734 Tuner Satellite Receiver Chipset
FDOUB
Frequency Doubler Input When FDOUB asserted, L64733C local oscillator frequency internally doubled mixers. When FDOUB deasserted, oscillator frequency doubled before being mixers. register group (APR 79), controls L64734 FDOUB output pin, which enables disables frequency doubler L64733C. FDOUB shown table below, where Fswitch frequency which frequency doubler enabled disabled.
Frequency MHz-Fswitch Fswitch-1680 1680-2175 FDOUB 79[6] 79[2] FDOUB 3-state HIGH
This method control preserves compatibility with L64733B, which affected 3-stating FDOUB pin. FLCLK Filter Clock Input FLCLK signal amplitude, self-biased clock input. frequency FLCLK signal multiplied baseband filter's frequency. I-Channel Offset Correction Input Connect larger capacitor between IDCp IDCn signals. Port Input Select Input When INSEL signal asserted, L64733C normal mode. When INSEL signal deasserted, L64733C Loop-Through mode. this mode, RFIN signal looped through RFOUT signal L64733C local oscillator shut off. Local Oscillator Buffer Select Input Asserting LOBUF causes external mode effect, local oscillator (LO) buffer enabled, signal sent PSOUT pins according division ratio selected with LODIV signal. When
IDCp, IDCn
INSEL
LOBUF
L64733C/L64734 Tuner Satellite Receiver Chipset
LOBUF deasserted, internal mode effect, PSOUT pins driven from 32/33 prescaler. LODIV Local Oscillator Buffer Division Ratio Input When LODIV signal asserted, local oscillator (LO) buffer division ratio when deasserted, ratio
MODp, MODn Prescaler Modulus Input differential signals form Positive Emitter Coupled Logic (PECL) input that sets prescaler modulus. When MODp signal positive with respect MODn signal, prescaler modulus (divide 32). When MODn signal positive with respect MODp signal, prescaler modulus (divide 33). PLLINp, PLLINn Phase Detector Input PLLIN differential signals form phase detector input connected L64734 PLLINp PLLINn output signals. L64734 PLLINp PLLINn descriptions "Synthesizer Control Interface" section. QDCp, QDCn Q-Channel Offset Correction Input Connect larger capacitor between QDCp QDCn signals.
Charge Pump Signals
following signals outputs from L64733C charge pump. Charge Pump Output Connect signal shown Figure page Feedback Charge Pump Transistor Drive Output Connect signal shown Figure page
L64734 Signal Descriptions
This section describes L64734 signals. Figure shows interface diagram L64734.
L64733C/L64734 Tuner Satellite Receiver Chipset
Figure
L64734 Interface Diagram
IBYPASS[5:0] IVINn IVINp QBYPASS[5:0] QVINn QVINp XOIN XOOUT LCLK PCLK PLLAGND PLLVDD PLLVSS IDDTN RESET XCTR_IN XCTR[3:0] AGC1 AGC2 FLCLK INSEL BCLKOUT CO[7:0] COEn DVALIDOUT ERROROUTn FSTARTOUT INTn SADR[1:0] SCLK SDATA FDOUB MODp MODn PLLINp PLLINn PSOUTp PSOUTn VREF_LVDS RESO_LVDS FBUFVDD FBUFVSS IBIAS ADCVDDI ADCVDDQ ADCVSSI ADCVSSQ
Channel Interface
Channel Data Output Interface
Channel Clock Interface
Microcontroller Interface
Interface
Synthesizer Control Interface
Control Signals Interface
Control Interface Tuner Control Interface
Interface
shown Figure L64734 following major interfaces:
Channel Channel Clock Control Signals Control Channel Data Output Microcontroller Synthesizer Control Tuner Control
L64733C/L64734 Tuner Satellite Receiver Chipset
following signal descriptions listed according major interface groups.
Channel Interface
Channel Interface input path L64734 satellite receiver. signals IVIN QVIN streams from satellite tuner circuit. signal strobes data signals. IBYPASS[5:0] Channel Data Input IBYPASS[5:0] signals form digital received channel data input bus, which supplies Stream L64734 when bypassed. setting particular register bits L64734 controls bypass. IVINp, IVINn Channel Data Input IVINp IVINn differential signals form analog received channel data input bus, which supplies stream L64734.
QBYPASS[5:0] Channel Data Input QBYPASS[5:0] signals form digital received channel data input bus, which supplies Stream L64734 when bypassed. setting particular register bits L64734 controls bypass. QVINp, QVINn Channel Data Input QVINp QVINn differential signals form analog received channel data input bus, which supplies stream L64734.
Channel Clock Interface
Channel Clock Interface consists clock crystal oscillator signals. IVIN/QVIN Input Clock Input positive, edge-triggered clock that strobes input data L64734.
L64733C/L64734 Tuner Satellite Receiver Chipset
XOIN
Crystal Oscillator Input XOIN provides crystal oscillator external reference clock input. Normally, crystal connected XOIN pin. Crystal Oscillator Output XOOUT crystal oscillator output pin.
XOOUT
Phase-Locked Loop (PLL) Interface
internal generates signals operate ADC, Demodulator, modules. LCLK Decimated Clock Output Output L64734 internal clock generation module generates LCLK signal. LCLK derived from dividing value CLK_DIV2 register parameter. Input Input signal input internal voltage-controlled oscillator. Normally, connected output external filter circuit. Clock Output Output L64734 internal clock synthesis module generates PCLK signal. reference crystal connected between XOIN XOOUT pins drives PLL. clock synthesis module configured generate PCLK rate that appropriate data rates. Analog Ground Input PLLAGND analog ground module normally connected system ground plane. Power Input PLLVDD power supply module normally connected system power (VDD) plane. Ground Input PLLVSS ground module normally connected system ground plane.
PCLK
PLLAGND
PLLVDD
PLLVSS
L64733C/L64734 Tuner Satellite Receiver Chipset
Control Signals Interface
Control Signals Interface controls operation L64734 associated with particular interface. IDDTN Test Input IDDTN Logic internal test pin. IDDTN normal operation. Reset Input This active-HIGH signal resets internal data paths. Reset timing asynchronous device clocks. Reset does affect configuration registers. Control Input Input XCTR_IN external input control pin. sensed reading XCTR_IN register bit. Control Output/Sync Status Flag Output XCTR[3] signal indicates synchronization status three synchronization modules L64734 XCTR[3] field Group three modules Viterbi Decoder, Reed-Solomon Deinterleaver (DI/RS), Descrambler. each three synchronization outputs, asserted XCTR[3] signal indicates that synchronization achieved sync module chosen using SSS[1:0] register bits. When deasserted, signal indicates out-of-synchronization condition. Output Control Output XCTR[2:0] pins external output control pins. They programming particular register bits. XCTR[2] mapped CPG1 XCTR[0] multiplexed with CPG2 when used with L64733C Tuner When on-chip serializer generates serial 3-wire protocol XCTR[2:0] pins, mapping XCTR[2] XCTR[1] SCL, XCTR[0] SDA.
RESET
XCTR_IN
XCTR[3]
XCTR[2:0]
Analog-to-Digital Converter (ADC) Interface
module converts incoming IVIN QVIN signals into internal 6-bit digital representation processing. following pins support module.
L64733C/L64734 Tuner Satellite Receiver Chipset
ADCVDDI/Q
Power Input ADCVDDI/Q analog power supply pins module normally connected system power (VDD) plane. Analog Ground Input ADCVSSI/Q analog ground pins module normally connected system ground plane. Analog Supply Input FBUFVDD analog supply on-chip reference voltage generator. This normally connected system power (VDD) plane. Analog Ground Input FBUFVSS analog ground on-chip reference voltage generator. This normally connected system ground (VSS) plane. Bias Current Output This bias current module. Connect this output resistor, connect other side resistor ground.
ADCVSSI/Q
FBUFVDD
FBUFVSS
IBIAS
Control Interface
Control Interface contains signals used power control. AGC1, AGC2 Power Control Output AGC1 AGC2 signals positive modulated output used power control. These signals each drive external passive filter that feeds gain control stage dual-stage AGC. single stage AGC, AGC1 used, same functionality PWRP L64724.
Channel Data Output Interface
Channel Data Output Interface output path from L64734. typically connected input transport demultiplexer set-top decoder application.
L64733C/L64734 Tuner Satellite Receiver Chipset
BCLKOUT
Byte Clock Output BCLKOUT output signal strobe that indicates valid data bytes CO[7:0] when L64734 Parallel Channel Output mode. BCLKOUT signal cycles once every valid output data byte used transport demultiplexer latch output data from L64734 BCLKOUT rate. BCLKOUT signal must disregarded Serial Channel Output mode. Channel Data Output CO[7:0] signals form decoded output data port. When (Group APR17), L64734 operates Parallel Channel Output mode. this mode, L64734 outputs channel data 8-bit wide parallel data CO[7:0] signals. Serial Channel Output mode L64734 outputs channel data serial data CO[0]. data latched each clock cycle. chronological ordering Serial Channel output mode oldest, newest. Channel Output Enable Input When asserted, COEn signal enables ERROROUTn, CO[7:0], DVALIDOUT, BCLKOUT, FSTARTOUT signals. Operation receiver continues regardless state COEn signal. Valid Data Output DVALIDOUT signal indicates that CO[7:0] signals contain corrected channel data. data valid CO[7:0] signals when DVALIDOUT signal asserted. DVALIDOUT asserted during propagated check bytes. DVALIDOUT signal deasserted after FEC_RST register (Group one.
CO[7:0]
COEn
DVALIDOUT
ERROROUTn Error Detection Flag Output L64734 asserts ERROROUTn signal beginning each frame that contains uncorrectable error, deasserts frame error condition removed. ERROROUTn signal aligned with output data stream asserted after FEC_RST register set.
L64733C/L64734 Tuner Satellite Receiver Chipset
FSTARTOUT Frame Start Output Output L64734 asserts FSTARTOUT signal during first every frame with valid data Serial Channel Output mode during first byte Parallel Channel Output mode. FSTARTOUT valid only when DVALIDOUT signal asserted. FSTARTOUT signal deasserted after FEC_RST register set.
Microcontroller Interface
Microcontroller Interface connects L64734 external microcontroller. INTn Interrupt Output L64734 asserts INTn when internal unmasked interrupt flag set. INTn signal remains asserted during interrupt condition, interrupt flag masked. Serial Address Input SADR[1:0] signals programmable bits serial address L64734. Serial Clock Bidirectional SCLK serial clock two-wire serial protocol. Serial Data Bidirectional SDATA serial data two-wire serial protocol.
SADR[1:0]
SCLK SDATA
Synthesizer Control Interface
Synthesizer Control Interface allows L64734 control L64733C frequency synthesizer. FDOUB Frequency Doubler Output, 3-State register Group controls L64734 FDOUB output pin, which enables disables frequency doubler L64733C.
L64733C/L64734 Tuner Satellite Receiver Chipset
FDOUB shown below; Fswitch frequency that disables enables frequency doubler.
Frequency MHz-Fswitch Fswitch-1680 1680-2175 FDOUB 79[6] 79[2] FDOUB 3-state HIGH
MODp, MODn Modulus Selector Output MODp MODn signals low-voltage differential signals from L64734 modulus selector programmable counter (A). PSOUT clocks these signals. When MODp signal positive with respect MODn signal, divide-by-32 selected dual modulus prescaler L64733C Tuner When MODp negative with respect MODn, divide-by-33 selected. counter programmed count down from particular value register programming. PLLINp, PLLINn Differential Counter Output PLLINp PLLINn signals low-voltage differential signals from L64734 programmable synthesizer counter (M). PSOUT clocks these signals. PLLINp positive with respect PLLINn PSOUT cycle. repetition rate reference crystal. counter programmed count down from particular value register programming. PSOUTp, PSOUTn Prescaler Output Output PSOUTp PSOUTn signals differential signals L64734 from L64733C. programmable counters L64734 clocked rising edge PSOUT signal. external mode (LOBUF HIGH), these signals come from buffer, which LODIV signal sets divider ratio. RESO_LVDS LVDS Buffers Precision Resistor Output RESO_LVDS output must connected resistor (6.8 which controls swing LVDSOUT
L64733C/L64734 Tuner Satellite Receiver Chipset
buffers used drive differential signals MODp, MODn, PLLINp, PLLINn. Connect other side resistor ground. VREF_LVDS LVDS Buffers Reference Voltage Input VREF_LVDS input voltage level that controls common mode voltage LVDSOUT buffers used drive differential signals MODp, MODn, PLLINp, PLLINn.
Tuner Control Interface
Tuner Control Interface contains signals that control L64733C Tuner FLCLK Filter Control Clock Output This output programmable integer value divider clocked PCLK (the demodulator sampling clock). division ratio programmed with register bits. FLCLK frequency multiplied cutoff programmable pass filters L64733C. Input Select Output When INSEL asserted, L64733C tuner selects normal mode. When INSEL deasserted, L64733C selects Loop-Through mode.
INSEL
Typical Operating Circuit
Figure diagram typical operating circuit chipset, implemented with L64733C-48 (48-pin package), including external components. external components shown. L64733/34 Evaluation Board User's Guide complete schematic details.
L64733C/L64734 Tuner Satellite Receiver Chipset
Figure
Typical Operating Circuit
Stripline Inductors Varactors
SADR[1] SADR[0] SDATA SCLK INTn RESET PSOUTn PSOUTp PLLINn PLLINp RESO_LVD VREF_LVD
BC847
PSOUTp PSOUTn GND1 GND1 TANKn VRLO TANKp GND1
L64733C-48
L64734
CFLT XTLn XTLp GND1 RFINn RFINp GND1 GNDSUB1 QDCn INSEL AGC2 AGC1 CPG2 XTLOUT CPG1 RFOUT GND1 LOBUF IDCp
Filter
PLLINn PLLINp MODn MODp LODIV IOUTp IOUTn QOUTp QOUTn FDOUB
L64733C/L64734 Tuner Satellite Receiver Chipset
0.01
ADCVDDI IVINp IVINn ADCVSSI FBUFVDD IBIAS FBUFVSS ADCVDDQ QVINp QVINn ADCVSSQ FDOUB FLCLK INSEL AGC2 AGC1 XCTR[1] XCTR[0] XCTR[2] XCTR[3] XCTR_IN
PLLVSS PLLAGND PLLVDD PCLK LCLK CO[0] CO[1] CO[2] CO[3] CO[4] CO[5] CO[6] CO[7] BCLKOUT DVALIDOUT FSTARTOUT ERROROUTn
XOOUT XOIN QBYPASS[0 QBYPASS[1 QBYPASS[2 QBYPASS[3 QBYPASS[4 QBYPASS[5
Notes:
ground connections L64733C provided metal plate under rather than direct connection ground pins PCB. external components shown. Refer L64733/34 Evaluation Board User's Guide complete details.
Specifications
This section contains electrical, timing, mechanical specifications L64733C/734 chipset.
L64733C Electrical Specifications
Table lists absolute maximum values. Exceeding values listed cause damage L64733C. Table gives recommended operating supply voltage temperature. Table gives characteristics; Table gives characteristics; Table Table summarize pins 44-pin packages, respectively. Table L64733C Absolute Maximum Rating (Referenced VSS)
Limits1 -0.5 +7.0 +150 +165 +300 Units mW/°C
Symbol Parameter supply voltage Continuous power dissipation Derating above Operating temperature Junction temperature Storage Temperature Lead temperature (soldering sec)
Note that ratings this table those beyond which permanent device damage likely occur. these values limits normal device operation.
Table
Recommended Operating Conditions
Limits1 Units
Symbol Parameter Supply Voltage Operating Ambient Temperature Range (Commercial)
normal device operation, adhere limits this table. Sustained operation device conditions exceeding these values, even they within absolute maximum rating limits, result permanent device damage impaired device reliability. Device functionality stated limits guaranteed recommended operating conditions exceeded.
L64733C/L64734 Tuner Satellite Receiver Chipset
Table
Parameter
Characteristics L64733C
Condition Units
Power Supply Power Supply Voltage Power Supply Current specs 4.75 5.25
Digital Control Inputs CPG1, CPG2, INSEL, FDOUB, LOBUF, LODIV Input Logic Level High Input Logic Level Input Bias Current
Slew-Limited Digital Clock Inputs FLCLK FLCLK Input Level FLCLK Input Level High FLCLK Input Resistance/Leakage Current series resistor between L64734 FLCLK pin. L64734 generates normal CMOS levels 1.85 1.45
Fast Digital Clock Inputs MODp, MODn, PLLINp, PLLINn MODp, MODn, PLLINp, PLLINn Common Mode Input Range (VCM) MODp, MODn, PLLINp, PLLINn Input Voltage MODp, MODn, PLLINp, PLLINn Input Voltage High MODp, MODn, PLLINp, PLLINn Input Current MODp, MODn, PLLINp, PLLINn differential swing around VCM. Need external 100- termination. MODp, MODn, PLLINp, PLLINn differential swing around VCM. Need external 100- termination MODp, MODn, PLLINp, PLLINn 1.08 1.32
-100
Digital Clock Outputs PSOUTp, PSOUTn PSOUTp, PSOUTn Common Mode Output Range (VCM) PSOUTp, PSOUTn Output Voltage PSOUTp, PSOUTn differential swing around VCM. Driving PECL Load (±10 µA), LOBUF 2.16 -215 2.64 -150
(Sheet
L64733C/L64734 Tuner Satellite Receiver Chipset
Table
Parameter
Characteristics L64733C (Cont.)
Condition PSOUTp, PSOUTn differential swing around VCM. Driving PECL Load (±10 µA), LOBUF PSOUTp, PSOUTn differential swing around VCM, driving differential LOBUF PSOUTp, PSOUTn differential swing around VCM, driving differential. LOBUF asserted. Units
PSOUTp, PSOUTn Output Voltage High PSOUTp, PSOUTn Output Voltage PSOUTp, PSOUTn Output Voltage High
-140
-100
Synthesizer/Local Oscillator Buffer Prescaler Ratio High Buffer Division Ratio LOBUF High, LODIV LOBUF High, LODIV High Reference Divider Ratio Charge Pump Output High Current CPG1, CPG2 CPG1, CPG2 CPG1, CPG2 CPG1, CPG2 Charge Pump Output Current CPG1, CPG2 CPG1, CPG2 CPG1, CPG2 CPG1, CPG2 Charge Pump Output Leakage Current Charge Pump Positive-to-Negative Current Matching Charge Pump Output Transistor Base Current Drive (Sheet self-biased. 0.08 0.24 0.48 1.44 -0.12 -0.36 -0.72 -2.16 -0.1 -0.3 -0.6 -1.8 0.12 0.36 0.72 2.16 -0.08 -0.24 -0.48 -1.44
L64733C/L64734 Tuner Satellite Receiver Chipset
Table
Parameter
Characteristics L64733C (Cont.)
Condition Units
Analog Control Inputs AGC1, AGC2 Input Bias Current
Baseband Outputs IOUTp, IOUTn, QOUTp, QOUTn Output Swing IOUTp, IOUTn, QOUTp, QOUTn Common Mode Voltage IOUTp, IOUTn, QOUTp, QOUTn Offset Voltage (Sheet Loaded with differential across IOUTp, IOUTn, QOUTp, QOUTn 0.65 0.85
Table
Parameter
Characteristics L64733C
Condition Units
Front RFIN Input Freq. Range RFIN Single-Carrier Input Power1 AGC1 Range AGC2 Range RFIN referred (front-end contributions) Meets following specs level needed produce 0.59 VPP. AGC1 AGC2 AGC1 gain input level (0.59 output), AGC2 maximum gain (VAGC2 signals MHz, @2175 @1550MHz @925 10.5 11.5 10.5 2175
Baseband Compression Point RFIN Referred (Sheet
IOUTp, IOUTn, QOUTp, QOUTn have signal within filter bandwidth PRFIN dBm,
15.5
L64733C/L64734 Tuner Satellite Receiver Chipset
Table
Parameter Noise Figure
Characteristics L64733C (Cont.)
Condition maximum gain AGC1, AGC2, 2150 Complex source" subject board, connector parasitics. 2150 MHz, subject board layout LO-generated harmonic RFIN-generated harmonic 10.8 Units
RFIN Return Loss Leakage Power RFIN Second Harmonic Rejection Half-Harmonic Rejection Harmonic Rejection2 Loop Through Gain
@2175 @1550MHz @925 PRFIN @2175 @1550MHz @925
12.0
RFIN referred (when Loop-Through enabled) Noise Figure Return Loss Baseband
Subject board connector parasitics
IOUTp, IOUTn, QOUTp, differential load, IOUTp, IOUTn, QOUTn Differential Output QOUTp, QOUTn. Expect from Voltage Swing each IOUTp, IOUTn, QOUTp, side, IOUTp, IOUTn, QOUTp, QOUTn Output Impedance QOUTn. Baseband Highpass 0.22 caps connected from IDCp Point IDCn, QDCp QDCn. Nominal Cutoff Frequency Range Nominal point filter
14.5 FFLCLK
(Sheet
L64733C/L64734 Tuner Satellite Receiver Chipset
Table
Parameter
Characteristics L64733C (Cont.)
Condition Deviation from ideal 7th-order Butterworth, measure 0.7. Include front-end tilt effects Measured point. @31.4 -0.5 Units
Baseband Frequency Response Cutoff Frequency Accuracy Quadrature Gain Error Quadrature Phase Error Synthesizer Crystal Frequency Range XTLOUT Voltage Levels XTLOUT Level MODp, MODn Delay
-5.5
Includes effects from baseband filters Measure
Measured parallel with 0.75 Must assert level within this time period ensure that next PSOUT period gives correct count. Delay with respect rising edge PSOUT (previous count). With respect rising edge PSOUT. This means that PSOUT need continue asserted after given correct count.
7.26
nsec
PLLINp, PLLINn MODp, MODn Hold Time
nsec
Local Oscillator Tuning Range Phase Noise, Including offset. Depends loop Doubler. Subject tank gain. implementation. offset. Depends loop gain. offset Buffer Frequency FDOUB Range when overdriven external (Sheet symbol rates below MS/s, maximum input power might subject shifting down roughly log(15/Rs[MS/s]) channel bandwidth reduction. harmonic rejection MHz. 1180 2175 dBc/Hz dBc/Hz dBc/Hz
L64733C/L64734 Tuner Satellite Receiver Chipset
Table
Mnemonic AGC1 AGC2 CFLT CPG[2:1] FDOUB FLCLK IDCp IDCn INSEL IOUTp IOUTn LOBUF LODIV MODp MODn PLLINp PLLINn PSOUTp PSOUTn QDCp
L64733C-48 Description Summary
Description Automatic Gain Control Automatic Gain Control Bias Voltage Bypass Charge Pump Charge Pump Gain Feedback Charge Pump Transistor Drive Frequency Doubler Filter Clock Ground (seven pins total) I-Channel Offset Correction (noninverting) I-Channel Offset Correction (inverting) Port Input Select I-Channel Baseband Data (noninverting) I-Channel Baseband Data (inverting) Local Oscillator Buffer Select Local Oscillator Buffer Division Ratio Select Prescaler Modulus (noninverting) Prescaler Modulus (inverting) Phase Detector (noninverting) Phase Detector (inverting) Prescaler (noninverting) Prescaler (inverting) Q-Channel Offset Correction (noninverting) Type Input Input Bidirectional Output Input Output Input Input Input Input Input Input Output Output Input Input Input Input Input Input Output Output Input
(Sheet
L64733C/L64734 Tuner Satellite Receiver Chipset
Table
Mnemonic QDCn QOUTp QOUTn RFINp RFINn RFOUT TANKp TANKn VRLO XTLp XTLn XTLOUT
L64733C-48 Description Summary (Cont.)
Description Q-Channel Offset Correction (inverting) Q-Channel Baseband Data (noninverting) Q-Channel Baseband Data (inverting) Input (noninverting) Input (inverting) Output (Loop-Through) Oscillator Tank Port (noninverting) Oscillator Tank Port (inverting) Power (six pins total) Local Oscillator Regulator Bypass Crystal Oscillator Port (noninverting) Crystal Oscillator Port (inverting) Crystal Type Input Output Output Input Input Output Input Input Input Bidirectional Input Input Output
(Sheet
L64733C/L64734 Tuner Satellite Receiver Chipset
Table
Mnemonic AGC1 AGC2 CFLT CPG[2:1] FDOUB FLCLK IDCp IDCn INSEL IOUTp IOUTn LOBUF LODIV MODp MODn PLLINp PLLINn PSOUTp PSOUTn QDCp
L64733C-44 Description Summary
Description Automatic Gain Control Automatic Gain Control Bias Voltage Bypass Charge Pump Charge Pump Gain Feedback Charge Pump Transistor Drive Frequency Doubler Filter Clock Ground (three pins total) I-Channel Offset Correction (noninverting) I-Channel Offset Correction (inverting) Port Input Select I-Channel Baseband Data (noninverting) I-Channel Baseband Data (inverting) Local Oscillator Buffer Select Local Oscillator Buffer Division Ratio Select Prescaler Modulus (noninverting) Prescaler Modulus (inverting) Phase Detector (noninverting) Phase Detector (inverting) Prescaler (noninverting) Prescaler (inverting) Q-Channel Offset Correction (noninverting) Type Input Input Bidirectional Output Input Output Input Input Input Input Input Input Output Output Input Input Input Input Input Input Output Output Input
(Sheet
L64733C/L64734 Tuner Satellite Receiver Chipset
Table
Mnemonic QDCn QOUTp QOUTn RFINp RFINn RFOUT TANKp TANKn VRLO XTLp XTLn XTLOUT
L64733C-44 Description Summary (Cont.)
Description Q-Channel Offset Correction (inverting) Q-Channel Baseband Data (noninverting) Q-Channel Baseband Data (inverting) Input (noninverting) Input (inverting) Output (Loop-Through) Oscillator Tank Port (noninverting) Oscillator Tank Port (inverting) Power (six pins total) Local Oscillator Regulator Bypass Crystal Oscillator Port (noninverting) Crystal Oscillator Port (inverting) Crystal Type Input Output Output Input Input Output Input Input Input Bidirectional Input Input Output
(Sheet
L64734 Electrical Specifications
This section contains electrical parameters L64734. Table lists absolute maximum values. Exceeding values listed cause damage L64734. Table gives recommended operating supply voltage temperature conditions. Table shows capacitance, Table gives characteristics, Table summarizes pins.
L64733C/L64734 Tuner Satellite Receiver Chipset
Table
L64734 Absolute Maximum Rating (Referenced VSS)
Limits1 -0.3 -1.0 -1.0 +125 Units
Symbol Parameter TSTG Supply Voltage LVTTL Input Voltage Compatible Input Voltage Input Current Storage Temperature Range (Plastic)
Note that ratings this table those beyond which permanent device damage likely occur. these values limits normal device operation.
Table
L64734 Recommended Operating Conditions
Limits1 +3.14 3.47 +125 Units °C/watt
Symbol Parameter Supply Voltage Operating Ambient Temperature Range (Commercial) Junction Temperature Junction Case Thermal Resistance2
normal device operation, adhere limits this table. Sustained operation device conditions exceeding these values, even they within absolute maximum rating limits, result permanent device damage impaired device reliability. Device functionality stated limits guaranteed recommended operating conditions exceeded. junction case thermal resistance valid measurements isothermal environment including board package.
Table
Symbol COUT
L64734 Capacitance
Parameter1 Input Capacitance Output Capacitance Units
Measurement conditions clock frequency MHz.
L64733C/L64734 Tuner Satellite Receiver Chipset
Table
Symbol
Characteristics L64734
Parameter Supply Voltage Input Voltage Input Voltage HIGH LVTTL Com/Ind/Mil Temp Range compatible Condition1 Max, -1.0, -2.0, -4.0, -6.0, -8.0, -12.0 1.0, 2.0, 4.0, 6.0, 8.0, 12.0 Max, VOUT PSOUTp PSOUTn -215 -215 -384 -384 Units
IIPU IIPD VIH_PECL
Switching Threshold Input Current Leakage Input Current Leakage with Pull-up Input Current Leakage with Pull-down Output Voltage HIGH Output Voltage 3-State Output Leakage Current Quiescent Supply Current
Dynamic Supply Current MHz, Midpoint PSOUTp, PSOUTn inputs Input Voltage High Level (DC)
(Sheet
L64733C/L64734 Tuner Satellite Receiver Chipset
Table
Symbol VIL_PECL IIL_PECL IIH_PECL
Characteristics L64734 (Cont.)
Parameter Input Voltage Level (DC) Input Current Input High Current Condition1 PSOUTp PSOUTn PLLINp/PLLINn, MODp/MODn signals PLLINp/PLLINn, MODp/MODn signals 1.253 1.030 1.373 1.032 1.437 1.059 Units
VRESO_LVDS Output Voltage RESO_LVDS VOH_LVDS VOL_LVDS Output Voltage High Level (DC) Output Voltage Level (DC)
(Sheet Specified ambient temperature over specified range.
Table
Mnemonic ADCVDDI/Q ADCVSSI/Q AGC1, AGC2 BCLKOUT CO[7:0] COEn DVALIDOUT
L64734 Description Summary
Description Power Analog Ground Power Control Byte Clock IVIN/QVIN Input Clock Channel Data Channel Output Enable Valid Data Error Detection Flag Analog Supply Analog Ground Type Input Input Outputs Output Input Output Input Output Output Input Input
ERROROUTn FBUFVDD FBUFVSS (Sheet
L64733C/L64734 Tuner Satellite Receiver Chipset
Table
Mnemonic FDOUB FLCLK FSTARTOUT IBIAS IBYPASS[5:0] IDDTN INSEL INTn IVINn, IVINp LCLK
L64734 Description Summary (Cont.)
Description Frequency Doubler Filter Control Clock Frame Start Output Bias Current Channel Data (ADC bypassed) Test Input Select Interrupt Channel Data Decimated Clock Output Input Modulus Selector Clock Output Analog Ground Differential Counter Power Ground Type Output, 3-State Output Output Output Inputs Input Output Output Input Output Input Outputs Output Input Outputs Input Input Outputs Input Input Input Output Input Bidirectional
MODp, MODn PCLK PLLAGND PLLINn, PLLINp PLLVDD PLLVSS
PSOUTp, PSOUTn Prescaler Output QBYPASS[5:0] QVINn, QVINp RESET RESO_LVDS SADR[1:0] SCLK (Sheet Channel Data (ADC bypassed) Channel Data Reset LVDS Buffers Precision Resistor Serial Address Serial Clock
L64733C/L64734 Tuner Satellite Receiver Chipset
Table
Mnemonic SDATA VREF_LVDS XCTR_IN XCTR[3:0] XOIN XOOUT
L64734 Description Summary (Cont.)
Description Serial Data LVDS Buffers Reference Voltage Control Input Control Output/Sync Status Flag Crystal Oscillator Crystal Oscillator Type Bidirectional Input Input Output Input Output
(Sheet
This section includes timing information L64734. During testing, HIGH inputs driven inputs driven transitions between HIGH, LOW, invalid states, timing measurements made shown Figure Figure Test Load Waveform Standard Outputs
Test Point
Output
3-state outputs, timing measurements made from point which output turns OFF. output when voltage greater than less than output when voltage less than greater than shown Figure
L64733C/L64734 Tuner Satellite Receiver Chipset
Figure
Test Point
Test Load Waveforms 3-State Outputs
Iref
Output
Vref Vref -0.5
Iref
Synchronous timing shown Figure Synchronous inputs must have setup hold relationship with respect clock signal that samples them. Synchronous outputs have delay from clock edge that asserts them. Figure L64734 Synchronous Timing
PCLK INPUTS OUTPUTS
reset pulse requirements shown Figure Figure L64734 RESET Timing Diagram
RESET
Figure shows relationship L64734 3-state signals COEn signal.
L64733C/L64734 Tuner Satellite Receiver Chipset
Figure
COEn
L64734 3-State Delay Timing
FSTARTOUT ERROROUTn DVALIDOUT BCLKOUT
Figure shows relationship L64733C PSOUTp PSOUTn prescaler signals signals back L64733C from L64734 control synthesizer. Figure L64734 Synchronous Timing Synthesizer Control
PSOUTp PSOUTn PLLINp, MODp PLLINn, MODn
numbers first column Table refer timing parameters shown preceding figures. parameters timing tables apply capacitive load
L64733C/L64734 Tuner Satellite Receiver Chipset
Table
L64734 Timing Parameters
Parameter tCYCLE tPWH tPWL tODS tODP tRWH TDLY tCYCLE_PS tPWH_PS tPWL_PS
Description Clock Cycle PCLK Clock Pulse Width HIGH Clock Pulse Width Input Setup Time Input Hold Output Delay from PCLK, serial mode Output Delay from BCLKOUT, parallel mode Reset Pulse Width HIGH Wake-Up Time Delay from COEn Clock Cycle PSOUTp, PSOUTn clock PSOUT Clock Pulse Width HIGH PSOUT Clock Pulse Width
Units PCLK cycles cycles cycles
11.1 33.31
Minimum (sampling clock MHz).
L64733C/L64734 Tuner Satellite Receiver Chipset
L64733C/734 Chipset Ordering Information
L64733C-48 available 48-pin TQFP package, L64733C-44 available 44-pin MLF2 package, L64734 available 100-pin PQFP package. They ordered set. Table gives ordering information chipset. Table L64733C/734 Chipset Ordering Information
Package Type Operating Range Commercial
Order Number
733x 734y version 48-pin TQFP (L64733C-48) 44-pin MLF2 (L64733C-44) version 100-pin PQFP (L64734)
tables figures that follow provide pinouts mechanical drawings each package chipset.
L64733C/L64734 Tuner Satellite Receiver Chipset
L64733C-48 Pinout Packaging Information
following subsections provide pinout packaging information 48-pin L64733C chip.
L64733C-48 Pinouts
Figure gives pinout 48-pin TQFP L64733C-48 package. Figure L64733C 48-Pin TQFP Pinout
PSOUTp PSOUTn TANKn VRLO TANKp
CFLT XTLn XTLp RFINn RFINp GNDSUB QDCn QDCp
L64733C/L64734 Tuner Satellite Receiver Chipset
View
PLLINn PLLINp MODn MODp LODIV IOUTp IOUTn QOUTp QOUTn FDOUB FLCLK
INSEL AGC2 AGC1 CPG2 XTLOUT CPG1 RFOUT LOBUF IDCp IDCn
L64733C-48 Mechanical Drawing
Figure mechanical drawing 48-pin TQFP L64733C-48 package. Figure L64733C-48 48-pin TQFP Mechanical Drawing
VIEW D1/2 E1/2 MIN. BOTTOM VIEW
MAX. EXPOSED CORNER DETAIL
EVEN LEAD SIDES DETAIL
PLACES 11-13° MIN. DATUM PLANE -H0.08 MIN. 0-7° 0.20 MIN. 0.09/0.20 0.09/0.16 1.00 REF. DETAIL DETAIL
DETAIL
0.08/0.20 0.25 GAUGE PLANE
WITH LEAD FINISH
BASE METAL
Notes: dimensioning tolerancing conform Ansi Y14.5-1982. Datum plane located mold parting line coincident with lead, where lead exits plastic body bottom parting line. Dimensions include mold protrusion. allowable mold protrusion 0.254 dimensions. package smaller than bottom package 0.15 millimeters. Dimension does include dambar protrusion. Allowable dambar protrusion shall 0.08 total excess dimension maximum material condition. Controlling dimension: millimeter. Maximum allowable thickness assembled this package family 0.30 millimeters. This outline conforms Jedec Publication Registration MO-136, variations Exposed shall coplanar with bottom package within mils (0.05 mm). Metal area exposed shall within nominal size.
JEDEC VARIATION DIMENSIONS MILLIMETERS MIN. 0.05 0.95 NOM. 0.10 1.00 9.00 BSC. 7.00 BSC. 9.00 BSC. 7.00 BSC. 0.60 BSC. 0.22 0.20 MAX. 1.20 0.15 1.05
0.45 0.14 0.17 0.17
0.75
0.27 0.23
L64733C/L64734 Tuner Satellite Receiver Chipset
L64733C-44 Pinout Packaging Information
following subsections provide pinout packaging information 44-pin L64733C chip.
L6433C-44 Pinout
Figure gives pinout 44-pin L64733-44 package. Figure L64733 44-Pin Pinout
VTUNE VRLO PSOUTn PSOUTp
L64733C/L64734 Tuner Satellite Receiver Chipset
IDCn IDCp LOCK CPG1/VCO0 XTALOUT CPG2/VCO1 AGC1 AGC2 ICPHI/VCO2
XTALn XTALp CFLT RFINn RFINp QDCn QDCP
L6473 View
PLLINn PLLINp MODn MODp IOUTp IOUTn QOUTp QOUTn FDIV FLCLK
L64733C-44 Mechanical Drawings
Figure mechanical drawing 44-pin L64733-44 package. Figure L64733C-44 44-pin Mechanical Drawing
L64733C/L64734 Tuner Satellite Receiver Chipset
Figure
L64753-44 44-pin Mechanical Drawing (Cont.)
L64733C/L64734 Tuner Satellite Receiver Chipset
L64734 Pinout Packaging Information
following subsections provide pinout packaging information L64734.
L64734 Pinouts
Figure gives pinout 100-pin PQFP L64734 package. Figure L64734 100-Pin PQFP Pinout
PLLVSS PLLAGND PLLVDD PCLK LCLK CO[0] CO[1] CO[2] CO[3] CO[4] CO[5] CO[6] CO[7] BCLKOUT DVALIDOUT FSTARTOUT ERROROUTn COEn IDDTN
ADCVDDI IVINp IVINn ADCVSSI FBUFVDD IBIAS FBUFVSS ADCVDDQ QVINp QVINn ADCVSSQ FDOUB FLCLK INSEL AGC2 AGC1 XCTR[1] XCTR[0] XCTR[2] XCTR[3] XCTR_IN IBYPASS[5]
SADR[1] SADR[0] SDATA SCLK INTn RESET PSOUTn PSOUTp PLLINn PLLINp RESO_LVDS VREF_LVDS MODn MODp
View
XOOUT XOIN QBYPASS[0] QBYPASS[1] QBYPASS[2] QBYPASS[3] QBYPASS[4] QBYPASS[5] IBYPASS[0] IBYPASS[1] IBYPASS[2] IBYPASS[3] IBYPASS[4]
L64733C/L64734 Tuner Satellite Receiver Chipset
L64734 Mechanical Drawings
Figure Figure show mechanical drawings 100-pin PQFP L64734 package. Figure 100-pin PQFP (UD) Mechanical Drawing
MD97.UD-1
Important:
This drawing latest version. board layout manufacturing, obtain most recent engineering drawings from your Logic marketing representative.
L64733C/L64734 Tuner Satellite Receiver Chipset
Figure
100-pin PQFP (UD) Mechanical Drawing (Cont.)
MD97.UD-2
Important:
This drawing latest version. board layout manufacturing, obtain most recent engineering drawings from your Logic marketing representative requesting outline drawing package code
L64733C/L64734 Tuner Satellite Receiver Chipset
Notes
L64733C/L64734 Tuner Satellite Receiver Chipset
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