Logic's L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
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L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Logic's L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101) highly integrated set-top control communication device, combining most logic needed digital broadcast system (DBS) cable set-top onto single chip. L64118's embedded 32-bit TinyRISCMIPS core provides processing power support transport system data, well general-purpose system control. L64118 interfaces directly Logic's L64704 L64724 (satellite), L64768 (cable) single-chip channel decoders, well L64105 MPEG-2 decoder. MPEG-2 transport system demultiplexer handle Packet Identifications (PIDs) simultaneously, including audio, video, generalpurpose data services. integrates Digital Video Broadcasting (DVB)compliant descrambler block, substantially increasing security set-top box. L64118's synchronous External System (EBus) communicates with external peripherals. L64118 communicates with peripherals through serial, parallel, SmartCard, infrared ports. Several generalpurpose pins provided that system designers expand system's capabilities. L64118 supports industry-standard SDRAM memory Mbytes, using Mbit SDRAMs. SDRAM interface supports PC66/100-compliant SDRAMS. L64118 offered Logic's G10®-p cell-based technology packaged 256-pin PBGA (IF) package.
February 1999
Copyright 1997, 1998 Logic Corporation. rights reserved.
Figure
Typical Set-Top Using L64118
Fast Parallel Port
Modem
I/Os Optional Mbyte SDRAM
Blaster/ Receiver
SmartCards
Port
IEEE1284 Line Driver
RS232 Line Driver
VCXO 27MHz
SDRAM Mbyte (max.)
SDRAM
Satellite/Cable Tuner
L64724 /L64768
L64118
L64105
External System
16/32
Optional FLASH Mbyte
FLASH Mbyte Teletext Interface
NTSC S-VIDEO L-SPEAKER R-SPEAKER
NTSC Encoder
CCIR601VIDEO ACLK PCM-AUDIO
L64118's embedded 32-bit MIPS (TR4101) runs MHz. chip's block bit, while interface external memory (through SDRAM controller) bit. MIPS16 MIPS32 instructions. 32-bit operations allow high-performance operation, while 16-bit operations allow code optimization memory savings. Since most transport processing filtering implemented hardware, much CPU's processing power devoted system processing.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
L64118 processes transport data packets Processing Unit (PPU) according MPEG-2 standard draft 13818-1, making Packetized Elementary Stream (PES), Program Specific Information (PSI), Service Information (SI), Private data available system. also buffers transfers audio video data packets external decoder device. L64118 interfaces directly Logic's L64105 MPEG-2 decoder. outputs demultiplexed audio video streams processing L64105. This decoder's extended channel buffer feature lets part L64118 SDRAM space store data directed L64105. benefit this that lets free memory L64105 increases On-Screen Display (OSD) capability. L64118 also interfaces directly Logic's family single-chip channel decoders (L64704, L64724, L64768), which allows channel data transferred parallel serial modes. L64118 implements automatic sync locking mechanism with programmable hysteresis function reliable locking onto MPEG-2 (0x47) transport packet sync bytes. External System (EBus) general-purpose, 32-bit wide system bus. controlled L64118 communication with external components system. This provides system designer with interface that permits glueless connection devices such FLASH, ROMs, external peripherals. L64118's peripheral interface blocks connect external systems directly set-top box. RS232 ports connect modem, terminal directly chip. IEEE1284 parallel port lets connect fast peripheral devices transfer filtered transport packets. IEEE1284 parallel port includes on-chip controller expediting data transfers between memory from, port. L64118 includes infrared transmitter (blaster) port applications such (remotely) programming VCR, well independent infrared receiver ports, which used program set-top using remote controller.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
system clock drives L64118 internal demultiplexer block, well most peripheral modules. block generates from system clock drive logic. L64118 includes four channels (one dedicated IEEE1284 port, three independent) that used transfer data between peripheral ports memory, from memory location another, from memory external system device.
Features
L64118 provides additional system features set-top application, including:
Channel
Compliance with ISO/IEC 13818-1 (MPEG-2) Transport specifications Sustained rates Mbits/s serial 13.0 Mbytes/s parallel transport stream input interface Direct interface Logic single-chip channel decoder devices, such L64704, L64768, L64724
Demux
filtering user-programmable PIDs) Hardware-assisted section filtering general-purpose PIDs (PSI, Private) Each filter includes match bytes mask bytes Each select filters simultaneously
Support Program Clock Reference (PCR) CRC32 parallel sections filtering process Descrambler core compliant common scrambling specifications Support transport-level PES-level descrambling Seamless support scrambled unscrambled data Support pairs 64-bit keys
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
256-byte transport buffers supporting audio video streams programmable cyclic buffers SDRAM memory assignable section filter index Support additional programmable cyclic buffer SDRAM post data adaptation fields Program Clock Reference (PCR) recovery locking Automatic detecting switching audio video PIDs splice points Audio oversampling (256 times oversampling) clock generation
Subsystems
Integration system: 32-bit TR4101 TinyRISC MIPS16 MIPS-II instruction compatible Four Kbyte Data (direct mapped) Eight Kbyte (two-way associative) instruction cache Basic Cache Controller unit (BBCC) Multiply/Divide Unit (MDU) Debugger Building Module (DBX) 32-bit Timers Interrupt Controller In-Circuit Emulator (ICE) port
interrupt handling modes: Interrupt Compatibility mode supports interrupt ports main interrupt levels. This mode compatible with L64108 interrupt structure. Interrupt Extension mode supports interrupt ports with software index each interrupt source. This mode reduce interrupt latency.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Peripherals
Programmable audio clock generator oversampling audio (ACLK) Three RS232 serial channels IEEE1284 parallel interface port (shared with port) ISO7816 SmartCard interfaces Infrared (IR) receivers transmitter Auxiliary (Aux) fast input/output port with multiple configurations settings (shared with IEEE1284 port) Teletext serial interface port with direct interface NTSC encoders I2C-compatible interface port supporting multimaster slave modes interfacing external devices Four channels (one dedicated IEEE1284 port, three independent) Synchronous extension 32-bit external addressing 8-/16-/32-bit data width Multiplexed address/data well eight demultiplexed address pins Synchronous output clock
general-purpose pins programmable chip-select output signals (five dedicated multiplexed) Enhanced serial modem
SDRAM Controller
SDRAM Controller supports Mbit SDRAM devices SDRAM Controller support Mbytes
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
General
On-chip MHz) with internal loop filter JTAG support 256-pin Plastic Ball Grid Array (PBGA) Package Commercial temperature range °C-70 ambient Low-power, 10%) process
Architectural Overview
components L64118 integrated provide complete system solution demultiplexing processing incoming MPEG-2 Transport Stream packets. Figure shows three main blocks L64118: TR4101 associated core building blocks, transport (demultiplexer) block, peripheral device interfaces. Additionally, L64118 three main buses:
Basic (BBus) BBus internal 32-bit that connects core building blocks with internal memory peripherals through CPU-to-Peripheral (C2P) bridge.
Peripheral (PBus) PBus internal peripheral bus; links SDRAM memory, internal peripheral devices, demultiplexer using bridge.
External System (EBus) EBus general-purpose 32-bit synchronous system that lets L64118 communicate with external components system. EBus connects BBus through EBus controller.
following subsections provide overview chip's main blocks.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Figure
L64118 Internal Block Diagram
TR4101 TinyRISC Core Controller Cache Controller BBus Cache Interrupt Controller EBus Controller Timers External System
Transport Stream
Block
PBus Internal Peripheral (PBus)
ICEport 1284 Parallel Port Controller Parallel Port Port
Transport Block
Register File Channel Decoder Interface Descrambler
Processor
Dispatcher Serial Ports
VCx0
Clock Recovery
SDRAM Controller SDRAM
I2CCompatible Interface
Teletext Interface
SmartCard Interface
Peripherals
Audio Clock Generator
ACLK
Video Buffer
Audio Buffer
Video Audio
L64105 Interface
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
TinyRISC MIPS Core
With powerful MIPS CPU, L64118 support system's general-purpose control requirements, including:
Complete set-top system initialization testing Security handling Communication ports protocol processing Remote control handling recovery locking Audio/video synchronization lip-syncing
also supports transport system data software processing data posted SDRAM transport processing block. This includes operations such
table maintenance (Program Association Table (PAT), Conditional Access Table (CAT), Program Table (PMT), Network Information Table (NIT)) Private Section filtering Subtitle processing overlay Closed caption teletext Electronic Program Guide
MIPS L64118 more than enough processing power implement tasks listed above. core programmed with 32-bit instructions. 32-bit operations allow high-performance operation; using 16-bit architecture permits reduced code size, saving memory. Both 32-bit instructions used same design.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
L64118's TR4101 MIPS part Logic's CoreWare® technology. chip integrates complete subsystem, including:
(TR4101) Cache memory instruction Kbyte) data Kbyte) cache Basic Cache Controller (BBCC) Timers (including watchdog timer) Interrupt Controller Debugger Building Module (DBX) Multiply/Divide Unit (MDU) port (full-duplex, serial receive transmit port) CPU-to-Peripheral (C2P)
L64118's embedded 32-bit MIPS runs MHz. This clock rate permits peak processing rate MIPS. chip's internal core implemented 32-bit architecture, execute both 16-bit 32-bit instructions. L64118 16-bit data interface external SDRAM, 32-bit data interface external system (EBus). operates Endian1 mode. Since most transport processing filtering implemented hardware, much CPU's processing power devoted system processing. chip includes address decoding logic directly interfacing external memory (FLASH, SDRAM) without requiring external glue logic. interface between subsystem rest L64118 implemented unit. module translates 32-bit data accesses 16-bit data accesses Peripheral Bus, which connects other blocks. PBus synchronous system clock.
Transport Demultiplexer Block
transport demultiplexer block processes transport stream data coming from channel interface. input L64118 transport block interfaces channel decoder; output interfaces
Big-Endian means that address multiple-byte data type address most significant byte.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
SDRAM controller module. block includes processor unit (PPU) that compliant with JSAT meets requirements many other service providers, including Canal+, SkyPerfect, BSkyB. unit process PIDs simultaneously. provides extensive filtering PSI, Private Sections. PSI, Private Sections filtered according user-programmable match/mask PIDs. Section data that passes filtering stored cyclic buffers offchip memory) associated with each PID. Each section each filtered against filters. (Every section undergoes CRC32 check. enable controls checking section types.) onchip descrambler unit increases system security. audio video data reduced streams delivered decoder.
SDRAM Controller
SDRAM controller resource arbitration logic makes efficient SDRAM bandwidth. This chip's low-cost system implementation approach dictates usage external SDRAM both transport general system functions. L64118 supports various SDRAM configurations using Mbit Mbit devices, total memory size Mbytes external SDRAM. SDRAM controller arbitrates access external SDRAM. This logic provides maximum possible SDRAM bandwidth on-chip without increasing need buffers other resources.
External System (EBus)
External System general-purpose 32-bit system used communication with external components system. This provides system designer with interface that permits glueless connection devices like FLASH, ROMs, external peripherals. EBus comprises 32-bit wide interface with multiplexed address data. Eight address bits available demultiplexed bits easy interface devices that need full address space. addition demultiplexed mode configured provide 24-bit address 16-bit data bus.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
EBus controller registers user program customized timing each address space used given system. address spaces supported, each with dedicated chip select output. main features EBus are:
32-bit physical addressing space 32-bit data width Synchronized clock Five external interrupt ports
EBus supports following main signals:
32-bit multiplexed address/data 8-bit demultiplexed (low order) address bits EACKn (Address latch enable) Five dedicated chip-selects multiplexed (with memory strobe) chip select 4-bit byte enable output clock
Peripherals
L64118 integrates several serial parallel ports, providing high degree connectivity various types peripherals. communication ports include:
Three 8251 RS232 serial communication ports connect set-top dumb monitor, modem, modem communicates between subscriber main station, back channel. serial includes V24-compatible UART glueless connection modem datapump ICs.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
IEEE1284 parallel communication port fast communication with workstation. L64118 includes on-chip controller dedicated data transfers between IEEE1284 parallel communication port main memory. I2C-compatible serial communication port communicate with devices using data links. This type common video encoders, audio DACs, remote control devices, tuners. independent SmartCard ports ISO-7816-3 compliant SmartCard ports interface through SmartCard coupler, support asynchronous protocol. ports also feature VCC, control. Teletext port that interfaces NTSC encoder allows direct insertion teletext data into NTSC video encoder device. teletext data usually transmitted using special-purpose PID. data then extracted Transport processor posted SDRAM. Finally, L64118 controller transfers teletext data Teletext port upon request from video encoder device. Teletext port includes FIFO between real-time timing required output pins internal data transfer. parallel port outputting/inputting transport packets from/to internal demultiplexer. port's direction controlled through configuration through AUXTX input pin. port programmed deliver receive transport packets various points within demultiplexer's pipeline. This port multiplexed with signals from IEEE1284 port. Infrared port with single blaster with identical output pins identical, independent, receiver modules. (transmitter) used communicate with off-board elements (e.g., program VCR). receivers, IR1, support remote control STB. Forty-seven general-purpose pins (GPIOs) configurable used control monitor subset processor functions, thus easing system integration minimizing external glue logic. Forty-one these I/Os multiplexed, dedicated GPIOs.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Controller
L64118 integrates four-channel controller that reduces major portion load might incur during data transfer between peripheral ports, memory, elements residing EBus. channel dedicated data transfers between IEEE1284 port main memory. other three channels generalpurpose. general-purpose channel (Channel supports transfers between PBus Ebus devices. typical applications, channel assigned SmartCard, channel serial port, memory memory data transfers.
Addressing
MIPS architecture uses types addresses: virtual addresses (used program), physical addresses (that appear address bus). This allows support kernel user modes, while combining cacheable noncacheable addresses. Virtual addresses partitioned into four, fixed-size segments: kuseg, kseg0, kseg1, kseg2, according Table Table Memory Segment Address Mapping
Segment kuseg kseg0 (cache) kseg1 (noncache) kseg2 (not used) Size Gbytes Mbytes Mbytes Gbytes
Virtual Address [31:29] 0b000-0b011 0b100 0b101 0b110-0b111
kuseg addresses accessible user kernel mode; they user-mode programs, while also providing direct access (requiring system call) those same addresses kernel mode. Because L64118 does have Memory Management Unit (MMU), kuseg addresses mapped unchanged physical addresses. L64118 does kseg2; thus, kseg2 addresses cannot used
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
programmer. Noncacheable kseg1 addresses used accessing peripheral registers code that requires noncacheability (for example, initialization code that executed before caches have been flushed). Cacheable kseg0 addresses used other code. on-chip performs virtual physical address translation; resultant 32-bit physical addresses output internal BBus. Peripheral (C2P) bridge module maps 32-bit BBus address internal 24-bit PBus address. EBus interface module (which resides internal BBus) maps 32-bit BBus address 24/321-bit EBus address, according mode which EBus interface configured width area being accessed. L64118 supports Mbyte physical address space (depending size SDRAM supported system). Virtual addresses kseg0 kseg1 always mapped same physical addresses, namely lowest Mbytes physical memory. programmer differentiate between cacheable noncacheable addresses using virtual address either kseg0 kseg1 (e.g., PSI/PES data stored noncacheable location, since they posted processor). part subsystem, L64118 small module (the Stub) that maps kseg0 kseg1 segments same physical address. does this clearing three most significant bits address kseg0 kseg1 segments presented internal bus). Segments kuseg kseg2 unaffected Stub. Note that L64118 operates only Big-Endian mode; Ebus must operate Big-Endian mode. strap option GPIO[42] (sampled during reset) determines physical connection EBus.
EBus uses either 24-bit address 32-bit address, depending address space being accessed.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
address space L64118 partitioned into following areas:
CPU/Peripheral This address space contains control status registers core building blocks. Configuration Register Space space contains registers that define configuration each peripheral PBus. partitioned into Kbyte segments, where each segment corresponds Configuration register entry each PBus component. Table Attribute Register Space Attribute register space contains Attribute register each peripheral PBus. This space partitioned into Kbyte segments, where each segment corresponds Attribute register entry each PBus component. Table Internal internal space contains registers functions each peripheral PBus. partitioned into Kbyte segments, where each segment corresponds entry PBus component. Table External External contains operating system, user's application programs (kseg0), configuration code, initialized data (kseg1). External space EBus external space used user-defined external memory external devices residing EBus. divided into three subspaces, each supporting devices with different width bits).
Primary SDRAM lowest 2/8/16 Mbytes addressable space mapped external SDRAM through internal SDRAM controller. Table "PBus EBus Address Mapping,"
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Table
PBus EBus Address Mapping
PBus Address 0x0000.0000-0x1F.FFFF 0x0100.0000-0x017F.FFFF 0x0100.0000-0x01FF.FFFF
EBus Mbytes SDRAM Mbytes SDRAM Mbytes SDRAM
Note that PBus addresses driven EBus, rather routed SDRAM controller. Mbyte eight Mbyte mode software compatible with L64108 code, since External Space (ES2) L64108 located PBus address 0x0080.0000 default). Table summarizes L64118 address space. Table L64118 Address Mapping
PBus/EBus Physical Base Address used used 0xF4.0000 (PBus) 0xF0.0000 (PBus) 0xE0.0000 (PBus) 0xC0.0000 (EBus demux mode) 0x00.0000 (EBus demux mode)3 0x00.0000 (EBus demux mode)5 0x1000.0000 (EBus mode)7
Virtual Base Address Noncache kseg1 0xBFFF.0000 0xBFF8.0000 0xBFF4.0000 Cache kseg0 BBus Base Address 0x1FFF.0000 0x1FF8.0000 0x1FF4.0000 Address Space Name CPU/Peripheral (Reserved1) used Internal Configuration Registers Internal Attribute Registers Internal External
Size (Mbytes) 0.50 0.50 0.25
0xBFF0.0000 0xBFE0.0000 0xBFC0.0000
0x9FC0.0000
0x1FF0.0000 0x1FE0.0000 0x1FC0.0000
0.25
0xB800.00002
0x9800.0000
0x1800.0000
8-bit devices External Space 16-bit devices External Space 32-bit devices External Space
0xB400.00004
0x9400.0000
0x1400.0000
0xB000.00006
0x9000.0000
0x1000.0000
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Table
L64118 Address Mapping (Cont.)
PBus/EBus Physical Base Address 0x0000.0000 (PBus) 0x0100.0000 (PBus)
Virtual Base Address Noncache kseg1 0xA000.0000 Cache kseg0 0x8000.0000 BBus Base Address 0x0000.0000 Address Space Name Primary SDRAM when Mbytes SDRAM used Primary SDRAM when Mbytes SDRAM used
Size (Mbytes)
0xA000.0000
0x8000.0000
0x0000.0000
These transactions appear PBus. This space used only when accesses BBus components (BBCC, Timer, C2P, INTC, ICEport). Within this range, used 8-bit devices, specific address ranges selected (and mode which they accessed) using Ebus address compare registers. Bits [23:0] BBus address reflected onto EBus Address eight-bit devices. Within this range used 16-bit devices, specific address ranges selected (and mode which they accessed) using EBus Address Compare registers. Bits [23:0] BBus address reflected onto EBus Address 16-bit devices. Within this range used 32-bit devices, specific address ranges selected (and mode which they accessed) using EBus Address Compare registers. Same address used EBus BBus when 32-bit devices accessed.
Signals
This section describes signals used L64118. Figure shows L64118 non-GPIO mode signals functional groups Figure shows L64118 GPIO mode signals. signals described group. Within each group, signals listed alphabetic order.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Figure
L64118 Signal Summary (Non-GPIO Modes)
SA[11:0] SBA[1:0] SBD[15:0] SCASn SDCLK SDQMH SDQML SRASn SWEn AREQn AVALID AVD[7:0] AVERRn VREQn VVALID ACLK AVDD AVSS IREF SC0_C4 SC0_C8 SC0_CLK SC0_DETECT SC0_I/O SC0_RSTn SC0_VCC_ENn SC0_VPP_ENn SC1_CLK SC1_DETECT SC1_I/O SC1_RSTn SC1_VCC_ENn SC1_VPP_ENn
CCLK Channel Interface CDATA[7:0] CERRn CVALID SCLK MPEG (PCR) SDET Phase-Locked Loop Infrared Port PLLVDD PLLVSS IRBL IRRX0 IRRX1 IRTX
SDRAM Interface
External System
AD[31:0] ADDR[7:0] BEn[3:0] CPU_CLK CSn[4:0] CSn[5]/MEMSTBn EACKn INTn[4:0] ECLK IDDTN ZTESTn CTSn0 CTSn1/ICECLK DSRn0 DTRn0 RCLK RTSn0 RTSn1 RXD0 RXD1/ICE_RX RXD2 TCLK TXD0 TXD1/ICE_TX TXD2
Audio/Video Decoder Port
Audio Clock Generator
L64118 Symbol
SmartCard0 Port
Test Signals
SmartCard1 Port
Serial Port/ ICEPort
I2C-compatible Port Teletext Port
IEEE1149.1 JTAG Port TRSTn ACKn/AUXNM AUTOFDn/AUXV BUSY/AUXSB FAULTn/AUXCLK INITn/AUXPID[2] IEEE 1284 Parallel PDATA[7:0] Auxiliary Port PERROR/AUXPID[0] SELECT/AUXPID[1] SELECTINn/AUX_ADP/AUX_ERR STROBEn/AUX_TX PDATA_DIR/OP_MODE[2] OP_MODE[1:0] RESETn Miscellaneous
TTXDATA TTXREQ GPIO[49:48,46:45,43:42] General-Purpose I/Os
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Figure
L64118 Signal Summary (GPIO Mode)
SA[11:0] SBA[1:0] SBD[15:0] SCASn SDCLK GPIO6 SDQML SRASn SWEn AREQn AVALID AVD[7:0] AVERRn VREQn VVALID ACLK AVDD AVSS IREF L64118 Symbol SC0_C4 SC0_C8 GPIO33 GPIO31 SC0_I/O GPIO30 GPIO32 GPIO34 GPIO38 GPIO36 SC1_I/O GPIO35 GPIO37 GPIO39 TRSTn ACKn/AUXNM GPIO14 GPIO15 GPIO24 GPIO25 GPIO[23:16] GPIO26 GPIO27 GPIO28 GPIO29
CCLK Channel Interface CDATA[7:0] CERRn CVALID SCLK MPEG (PCR) SDET Phase-Locked Loop Infrared Port PLLVDD PLLVSS GPIO47 GPIO40 GPIO41 GPIO44
SDRAM Interface
AD[31:0] ADDR[7:0] BEn[1:0] GPIO[3:2] CPU_CLK External System CSn[3:0] GPIO1 CSn[5]/MEMSTBn EACKn INTn[4:0] ECLK Test IDDTN Signals ZTESTn GPIO7 CTSn1/ICECLK GPIO9 GPIO8 RCLK GPIO10 RTSn1 GPIO11 Serial Port/ ICEPort RXD1/ICE_RX RXD2 TCLK TXD0 TXD1/ICE_TX TXD2 I2C-compatible Port Teletext Port
Audio/Video Decoder Port
Audio Clock Generator
SmartCard0 Port
SmartCard1 Port
IEEE1149.1 JTAG Port
IEEE 1284 Parallel Auxiliary Port
GPIO13 GPIO12 GPIO[49:48,46:45,43:42] General-Purpose I/Os
PDATA_DIR/OP_MODE[2] OP_MODE[1:0] RESETn
Miscellaneous
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Table lists default values output bidirectional signals. Note that during reset, bidirectional signals (and some output signals) floating. Table Default Values L64118 Output Bidirectional Signals After Reset1
Default Value asserted inactive (LOW) driving unknown value driving unknown value asserted asserted asserted driving unknown value asserted asserted asserted asserted asserted asserted asserted floating asserted asserted drives assertion floating asserted Notes
Signal ACKn/AUXNM ACLK AD[31:0] ADDR[7:0] AUTOFDn/AUXV AVALID AVD[7:0] AVERRn BEn[3:0] BUSY/AUXSB CSn[4:0] CSn[5]/MEMSTBn DTRn0 FAULTn/AUXSB GPIO42, INITn/AUXPID[0] IRTX PDATA_DIR/ OP_MODE[2] PDATA[7:0]
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Table
Default Values L64118 Output Bidirectional Signals After Reset1 (Cont.)
Default Value asserted driving unknown value driving unknown value floating pulled external pull-up resistor asserted asserted floating pulled external pull-up resistor asserted asserted asserted pulled using external pull-up resistor pulled using external pull-up resistor toggling asserted asserted asserted asserted serves input Notes
Signal RTSn0/1 SA[11:0] SBA[1:0] SBD[15:0] SC0_C4, SC0_C8 SCASn SCx_CLK SCx_DETECT SCx_IO SCx_RSTn SCx_VPP_ENn SCx_VCC_ENn SDCLK SDQMH SDQML SRASn SWEn
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Table
Default Values L64118 Output Bidirectional Signals After Reset1 (Cont.)
Default Value floating asserted asserted Notes behaves input
Signal TTXREQ/GPIO12 TTXDATA TXD0/2 TXD1/ICE_TX VVALID
asserted asserted
cycles after reset (RESETn driven HIGH), L64118 initiates transaction EBus, changing some default values this table.
Channel Interface Port
These signals provide physical connection Channel Interface devices, such Logic's L64724 L64768. This port supports both parallel serial connections. CCLK Channel Clock Input When CVALID asserted HIGH, L64118 latches CDATA[7:0] rising edge CCLK. serial mode, L64118 uses only CDATA[0]. serial mode, maximum clock rate MHz; parallel mode, MHz. CCLK must toggle during reset ensure proper reset channel interface block. Channel Data Input These signals deliver channel information L64118. When CVALID asserted, chip latches data every rising edge CCLK. When L64118 parallel input mode, CDATA[7:0] signals deliver data. When L64118 serial mode, only CDATA[0] delivers data.
CDATA[7:0]
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
CERRn
Channel Data Error Input This active input signal indicates that uncorrected error occurred preceding channel interface. When CVALID asserted, CERRn latched rising edge CCLK. Channel Data Valid Input This active HIGH input signal indicates that CDATA[7:0] CERRn carrying valid data. When CVALID asserted, rising edge CCLK latches CDATA[7:0] signals into L64118.
CVALID
MPEG Program Clock Reference (PCR) Recovery
These signals recover Program Clock Reference (PCR). They interface external VCxO, which provides clock decoder. SCLK System Clock Input This input provides clock signal L64118. must driven external VCxO (the voltage control input controlled SDET external filter). System Clock Sigma-Delta Control Voltage Output This converter output signal from 16-bit Sigma-Delta modulator inside L64118 drives simple low-pass filter produce analog control voltage external VCxO.
SDET
Phase-Locked Loop (PLL)
These signals supply power ground internal PLL, which generates internal clock from external SCLK input. internal clock then divided generate internal clock used other internal modules. Isolate PLLVDD PLLVSS signals from digital noise digital logic using layout bypass filtering techniques. PLLVDD Analog Input This provides separate filtered circuit through PLLVDD that switching noise from digital portion chip affect stability.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
PLLVSS
Analog Input This provides separate ground circuit through PLLVSS that switching noise from digital portion chip does affect stability.
External System (EBus)
EBus comprises 32-bit wide interface with multiplexed address data. Eight address bits available demultiplexed bits easy interface devices that need full address space. transactions synchronous output CPU_CLK. subset these signals programmed general-purpose signals setting General-Purpose Mode register. AD[31:0] Multiplexed Address/Data Bidirectional AD[31:0] multiplexed address/data bus. L64118 programmed drive full address this access start. After this address phase presents write data write external device drives data read. Demuxed Address Output ADDR[7:0] provides eight bits demultiplexed address bits. This allows some designs remove external address latch multiplexed address/data hold address throughout transaction. EBus uses byte addressing. 16-bit devices must ignore ADDR[0]. 32-bit devices must ignore ADDR[1:0]. Address Latch Enable Output This active HIGH signal controls latches demultiplexing address from bus. Byte Enables Output four byte enable outputs asserted during read write transaction EBus control which four byte lanes enabled. byte lane selection dependent width transaction (word, halfword, byte) data width external device (32, bits).
ADDR[7:0]
BEn[1:0]
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
byte enables always correspond same physical lines bus: BEn[1] corresponds AD[15:8], BEn[0] AD[7:0]. BEn[2] Byte Enable Output four byte enable outputs asserted during read write transaction EBus control which four byte lanes enabled. byte lane selection dependent width transaction (word, halfword, byte) data width external device (32, bits). byte enables always correspond same physical lines bus: BEn[2] corresponds AD[23:16]. GPIO2 Bidirectional BEn[2] serve general-purpose signal (GPIO2) setting General-Purpose Mode register. BEn[3] Byte Enable Output four byte enable outputs asserted during read write transaction EBus, control which four byte lanes enabled. byte lane selection dependent width transaction (word, halfword, byte) data width external device (32, bits). byte enables always correspond same physical lines bus: BEn[3] corresponds AD[31:24]. GPIO3 Bidirectional BEn[3] serve general-purpose signal (GPIO4) setting General-Purpose Mode register. CPU_CLK EBus Output Clock Output This output clock generated dividing on-chip clock two. This clock serves reference signal transactions EBus. timing relationship between SDCLK output clock, SCLK input CPU_CLK output unknown.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
CSn[3:0]
Programmable Chip Selects Output Each chip select programmed assert specific address area. These pins used select specific external devices according on-chip address decoding. They make interfacing various peripherals easier, they remove need external address decoders. Programmable Chip Select Output This similar function other five chip select output pins. used select specific external devices according on-chip address decoding. GPIO1 Bidirectional CSn[4] serve general-purpose signal (GPIO1) setting General-Purpose Mode register.
CSn[4]
CSn[5]/MEMSTBn Chip Select[5] Memory Strobe Output This similar function other five chip select output pins holds characteristic being able function MEMSTBn (active memory strobe) signal. MEMSTBn signal general-purpose signal. used indicate that memory transaction progress. asserted both read write cycles. timing this signal programmable. EACKn Target Acknowledge Input This signal indicates L64118 that external device ready complete current read write cycle. transaction will finish both EACKn asserted internal wait state generator expired. This mechanism allows devices extend access beyond number wait states programmed that particular address area. EACKn programmed either active HIGH LOW, using XPOS CEBUSMODE register. EACKn must deasserted before next transaction acknowledge cycle. self-acknowledge devices, external EACKn ignored, transaction completes when wait state generator expires. This controlled XACK CECFGn register.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
INTn4
Interrupt Input This unmaskable interrupt used highest priority system needs. Interrupts Input These four external interrupts programmed level- edge-triggered sensitive. Interrupts INTn[3:0] maskable general-purpose use. When L64118 receives interrupt, internal completes execution current instruction jumps preprogrammed location memory containing handler this interrupt. default, these signals level triggered after reset. Read Output active read strobe asserted during read operations, deasserted during writes. Write Enable Output active write strobe asserted during write operations deasserted during reads.
INTn[3:0]
Miscellaneous Signals
These general signals necessarily associated with specific function module L64118. OP_MODE[1:0] Operational Mode Input These signals, along with OP_MODE[2], used strap options configure various Logic test modes. normal operation, configure OP_MODE[2:0] 0b000. That OP_MODE[1:0] should tied LOW, OP_MODE[2] should pulled with resistor. OP_MODE[2]/PDATA_DIR Operational Mode Input This signal used strap option during reset conjunction with OP_MODE[1:0] pins, must pulled with resistor proper device operation.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Parallel Data Direction Output After reset, this signal serves PDATA_DIR output, which controls parallel data buffers 1284 PDATA[7:0] data lines. When 1284 port used port, this driven HIGH. RESETn Asynchronous Reset Input Asserting this active signal resets L64118 power state. ensure complete reset L64118, RESETn must asserted least SCLK cycles.
Test Signals
These signals Logic test purposes. They must tied constant value normal operational mode. ECLK IDDTN ZTESTn Connect This Logic manufacturing test pin. Connect This Logic manufacturing test pin. Connect This Logic manufacturing test pin. deasserted HIGH normal chip operation. Input Input Input
Serial Port/ICEPort
These signals connect L64118 external modem, terminal, other host that includes RS232 interface. L64118 contains three serial ports that comply with asynchronous specification RS232 standard. on-chip baud rate generators support standard rate serial communication. Three SIO1 signals configured serve internal ICEport module. CTSn0 Clear Send Port Input When reset LOW, this signal indicates that external receiver ready data transfer through TxD0/RxD0. Transmit Enable Command register HIGH when CTSn0 reset LOW, data from Transmit register Port serialized through TxD0.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
GPIO7 Bidirectional CTSn0 serve general-purpose signal (GPIO7) setting General-Purpose Mode register. CTSn1/ICECLK Clear Send Port1 Input This serve either Clear Send signal SIO1, ICEport clock input ICEport module. strap option GPIO[43] controls this pin's functionality usage. GPIO[43] sampled HIGH during reset, this serves CTSn1. When reset LOW, this signal indicates that external receiver ready data transfer through TxD1/RxD1. Transmit Enable Command register HIGH when CTSn1 reset LOW, data from Transmit register Port serialized through TxD1. Serial Clock Input When serial mode enabled, this functions ICECLK, synchronous port clock input. DSRn0 Data Ready Port Input When reset LOW, this general-purpose input control signal indicates that external terminal device ready data transfer. polarity DSRn0 latched Port Status register read. GPIO9 Bidirectional DSRn0 serve general-purpose signal (GPIO9) setting General-Purpose Mode register. DTRn0 Data Terminal Ready Port Output When this general-purpose output control signal reset LOW, data external terminal device ready transmitted. DTRn0 reset programming Command register. default, this signal asserted after reset. GPIO8 Bidirectional DTRn0 serve general-purpose signal (GPIO8) setting General-Purpose Mode register.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
RCLK
Receive Serial Data Clock Input This signal used receive clock input enhanced UART mode. Request Send Port Output When this general-purpose, programmable control signal reset LOW, Port ready send data through TxD1. This signal reset programming Command register. default, this signal asserted after reset. GPIO10 Bidirectional RTSn0 serve general-purpose signal (GPIO10) setting General-Purpose Mode register.
RTSn0
RTSn1
Request Send Port1 Output When this general-purpose, programmable control signal reset LOW, Port ready send data through TxD1. This signal reset programming Command register. Receive Data Port Input This signal provides serial data from external RS232 device. protocol similar that TxD0. receive baud rate programmed Baud Rate register. data received RXD0 latched Receive register Port GPIO11 Bidirectional RXD0 serve general-purpose signal (GPIO11) setting General-Purpose Mode register.
RXD0
RXD1/ICE_RX Receive Data Port Input This serves either Receive port signal SIO1, ICEport receive input ICEport module. strap option GPIO[43] controls this pin's functionality usage. GPIO[43] sampled HIGH during reset, this serves RXD1. that case, this signal provides serial data from external RS232 device.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
protocol this similar that TxD1. receive baud rate determined programming Baud Rate register. data received RXD1 latched Receive register Port GPIO[43] sampled during reset, then this serves receive port ICEport L64118. Receive Data Serial Port Input When serial mode enabled, this functions ICE_RX, receive data port input. RXD2 Receive Data Port Input This signal provides serial data from external RS232 device. protocol this similar that TxD2. receive baud rate determined programming Baud Rate register. data received RXD2 latched Receive register Port Transmit Serial Data Clock Input This signal used transmit clock enhanced UART mode. Transmit Data Port Output This signal outputs data compliance with RS232 protocol's asynchronous specification. transmit baud rate determined programming Baud Rate register. Data transmitted TXD0 comes from Transmit register Port default, this signal asserted after reset. Transmit Data Port Output This serve either Transmit Data port signal SIO1, ICEport receive input ICEport module. strap option GPIO[43] controls this pin's functionality usage. GPIO[43] sampled HIGH during reset, this serves TXD1. When TXD1, this signal outputs data compliance with RS232 protocol's asynchronous specification. data rate this determined programming Baud Rate register. Data transmitted TXD1 comes from Transmit register Port
TCLK
TXD0
TXD1/ICE_TX
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Transmit Data Serial ICEPort Output GPIO[43] sampled during reset, this serves ICE_TX, serial transmit data output port. default, this signal asserted after reset. TXD2 Transmit Data Port Output This signal outputs data compliance with RS232 protocol's asynchronous specification. data rate this determined programming Baud Rate register. Data transmitted TXD2 comes from Transmit register Port default, this signal asserted after reset.
SDRAM Interface
following group signals provides interface between L64118 external SDRAM devices. SDRAM interface works with PC66/100 compliant SDRAMs. L64118 SDRAM interface runs capable accessing Mbyte memory configurations using Mbit Mbit devices. This interface 16-bit data (SBD[15:0]). upper lower byte mask signals (SDQMH SDQML) control halfword byte accesses. SBA[1:0] outputs support two- four-bank SDRAM devices. L64118 automatically performs SDRAM refreshes. L64118 does support Chip Select (CSn) Clock Enable (CKE) signals. these SDRAM signals active HIGH, respectively, SDRAM device(s) used. SA[11:0] SDRAM Address Output These signals carry 12-bit SDRAM address bus. number column address bits used programmable SDRAM Configuration register. SDRAM Bank Select Output These signals allow access SDRAM devices with either four banks. number bank select bits used programmable SDRAM Configuration register.
SBA[1:0]
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
SBD[15:0]
SDRAM Data Bidirectional This data driven SDRAM during read operation, driven L64118 during write operation. 3-stated after reset when there memory accesses. Column Address Strobe Output This signal active column address strobe. used conjunction with SRASn SWEn outputs form SDRAM command. SDRAM Clock Output This master SDRAM clock. output signals referenced rising edge SDCLK. programmable SDRAM timing parameters expressed SDCLK periods. High Byte Mask Output This active HIGH signal high byte data mask, which controls high byte input/output buffer external SDRAM. When asserted, disables (masks) high data byte SDRAM data bus. GPIO6 Bidirectional SDQMH serve general-purpose signal (GPIO6) setting General-Purpose Mode register.
SCASn
SDCLK
SDQMH
SDQML
Byte Mask Output This active HIGH signal byte data mask, which controls byte input/output buffer external SDRAM. When asserted, disables (masks) data byte SDRAM data bus. Address Strobe Output This signal active address strobe. SRASn used conjunction with SCASn SWEn outputs form SDRAM command. Write Enable Output This signal active write enable strobe. SWEn used conjunction with SRASn SCASn outputs form SDRAM command.
SRASn
SWEn
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Audio/Video Decoder Port
These signals provide interface between L64118 external MPEG-2 Audio/Video decoder. This interface supports seamless connection between L64118 Logic's L64105 decoders. supports serial data transfer rate Mbits/s serial mode, Mbytes/s parallel mode. actual data rate controlled audio video request signals coming from decoder device. AREQn Audio Data Request Input When asserted, this signal indicates that external decoder requesting audio clocked external decoder. Deassertion AREQn indicates that decoder ready accept audio data. Audio Data Valid Output When asserted, this signal indicates that valid audio data available AVD[7:0] bus. LOW-to-HIGH transition SCLK causes audio data latched external decoder. serial mode, AVALID active HIGH. parallel mode, AVALID latches data rising edge. This signal asserted after reset. Audio Video Compressed Data Bidirectional This provides data external decoder. serial mode, AVD[0] carries data. parallel mode, entire carries byte-wide data. L64118 outputs audio video data from on-chip buffers SDRAM buffers through AVD[7:0]. These signals drive unknown value after reset. Audio Video Data Error Output When asserted, this signal indicates that there uncorrected error stream entering external decoder. L64118 generates AVERRn result detection discontinuity transport packets audio and/or video program being decoded. Usually, discontinuity result loss packets from uncorrected errors. This signal asserted after reset. Video Data Request Input When asserted, this signal indicates that external decoder device requesting video
AVALID
AVD[7:0]
AVERRn
VREQn
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
clocked external decoder. Deassertion VREQn indicates that decoder ready accept video data. VVALID Video Data Valid Output When asserted, this signal indicates that valid video data available line. LOW-to-HIGH transition SCLK causes video data AVD[7:0] latched external decoder. serial mode, VVALID active HIGH. parallel mode, VVALID latches data rising edge. This signal asserted after reset.
Audio Clock Generator
These signals generate oversampling audio clock, which drives L64105 external decoder low-cost audio DAC. audio clock generation circuit provides oversampling audio frequencies locked program clock. fully programmable circuit supports wide range oversampling audio frequencies. implemented using advanced mixed-signal technology. ACLK Audio Clock Output ACLK provides oversampling audio clock that drives L64105 audio clock input system clock input conventional stereo audio DAC. This signal driven after reset. Analog Input AVDD provides power voltage analog circuit audio clock generator. must isolated from Digital (DVDD) ferrite insulator. Analog Ground Input AVSS provides analog ground audio clock generator circuit. should must isolated from digital ground supply (DGND). Current Reference This must connected shown Figure
AVDD
AVSS
IREF
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Figure
IREF Connection Devices
AVDD
16.9
IREF AVSS L64118
IREF
18-bit
Controlled Oscillator
FSC_CNTL DCO_DIV REF_DIV
Digital ACLK
IEEE 1149.1 (JTAG) Port
This group signals drive IEEE1149.1 Test Access Port (TAP). Test Clock Input This clock sample JTAG input data. Test Data This line JTAG input test data. Test Data This line JTAG output test data. Input Output
Test Mode Select Input This line lets select between active JTAG mode. When JTAG mode, I/Os serialized. Active mode normal operation. Test Port Reset Input When asserted LOW, this signal resets internal JTAG controller. does reset chip.
TRSTn
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
IEEE1284 Parallel Port Auxiliary Port
These signals provide parallel connection between L64118 external peripheral device. port complies IEEE1284 standards supports several modes. 1284 mode enabled when AUX_SEL reset (System Mode register, This port also serves auxiliary port receiving transmitting transport bitstreams from various points on-chip demultiplexer pipeline. mode enabled when AUX_SEL (System Mode register, following list shows each pin's functionality IEEE1284 port port signal. Some these pins also serve general-purpose pins. ACKn/AUXNM 1284 Acknowledge Output When L64118 asserts this signal, valid data latched L64118 IEEE1284 input register. default, this signal asserted after reset. Match Output mode, this signal functions AUXNM indicate that data being sent through auxiliary port transport packet that failed filtering. AUTOFDn/AUXV 1284 Autofeed Input 1284 mode, this functions Autofeed input. Data Valid Bidirectional mode, this functions AUXV, which used qualifier indicating that data presented auxiliary data valid. GPIO14 Bidirectional This signal serve general-purpose signal (GPIO14) setting General-Purpose Mode register.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
BUSY/AUXSB 1284 Peripheral Busy Bidirectional 1284 mode, this signal functions BUSY. When this signal HIGH, 1284 port ready data transfer. default, this signal asserted after reset. Sync Byte Bidirectional mode, this signal functions AUXSB indicate that data being sent through auxiliary port first byte (sync byte) transport packet. GPIO15 Bidirectional This signal serve general-purpose signal (GPIO15) setting General-Purpose Mode register. FAULTn/AUXCLK 1284 Peripheral Fault Operation Bidirectional 1284 mode, this signal functions FAULTn. This signal indicates that 1284 port encountered error during operation. Typically, this error overrun, underrun, parity error. Port Clock Bidirectional mode, this signal functions AUXCLK, which reference clock transactions auxiliary port. When port configured output port, this signal output with programmable frequencies 13.5, 6.75 3.375 MHz. When port configured input port, this signal input with frequency based input transport stream data rate. GPIO24 Bidirectional This signal also serve general-purpose signal (GPIO24) setting General-Purpose Mode register. INIT/AUXPID[2] 1284 Peripheral Initialization Input 1284 mode, this signal functions INITn. When reset LOW, this signal resets IEEE1284 port returns logic compatibility idle state.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Packet Output mode, this signal part three-bit packet that assigned PIDs that output port. GPIO25 Bidirectional This signal also serve general-purpose signal (GPIO25) setting General-Purpose Mode register. PDATA[7:0] Parallel Data Signals 1284 Bidirectional 1284 mode, these signals carry data transferred between host IEEE1284 port. Bidirectional mode, PDATA[7:0] carry transport packets from/to L64118 demultiplexer port. GPIO[23:16] Bidirectional These signals also serve general-purpose (GPIO[23:16]) setting General-Purpose Mode register. default, this signal asserted after reset. PDATA_DIR/OP_MODE[2] 1284 Peripheral Data Direction Output After reset, this signal serves PDATA_DIR output signal that controls parallel data buffers 1284 mode. mode, this driven HIGH. Operational Mode Input This signal used strap option during reset. normal device operation, pull this signal during reset. PERROR/AUXPID[0] 1284 Peripheral Error Output 1284 mode, this signal functions PERROR. When HIGH, this signal indicates that L64118 IEEE1284 port encountered error during data processing. FAULTn asserted whenever PERROR activated.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Packet Output mode, this signal part three-bit packet that assigned PIDs that output port. GPIO26 Bidirectional This signal also serve general-purpose signal (GPIO26) setting General-Purpose Mode register. SELECT/AUXPID[1] 1284 Peripheral Select Output When HIGH, this signal indicates that L64118 IEEE1284 port selected connected host. Packet Output mode, this signal part three-bit packet that assigned PIDs that output port. GPIO27 Bidirectional This signal also serve general-purpose signal (GPIO27) setting General-Purpose Mode register. SELECTINn/AUX_ADP/AUX_ERR 1284 Peripheral Selection Indicator Input 1284 mode, this signal (when asserted LOW) indicates that external host attempting select peripheral. Adaptation Field Flag Output output mode, this signal functions AUX_ADP, which indicates output byte part adaptation field. Error Indicator Input input mode, this signal functions AUX_ERR, which indicates incoming byte part packet that error. GPIO28 Bidirectional This signal also serve general-purpose signal (GPIO28) setting General-Purpose Mode register.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
STROBEn/AUX_TX 1284 Data Strobe Input 1284 mode, this signal functions STROBEn. When LOW, this signal indicates that valid data present PDATA[7:0]. L64118 latches data rising edge STROBEn. Port Direction Input mode, this signal used specify direction port PINACT (bit Control register. AUX_TX HIGH, then port output. AUX_TX LOW, then port input. GPIO29 Bidirectional This signal also serve general-purpose signal (GPIO29) setting General-Purpose Mode register.
I2C-Compatible Port
These signals connect L64118 external device. L64118 uses them initialize external devices system that have this interface. Serial Clock Bidirectional provides clock signal transmitting receiving data through SDA. Serial Data Bidirectional provides data connection I2C-compatible port. Data transmitted received through this line according protocol. This signal should pulled HIGH external pull-up resistor.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Teletext Port
These signals connect L64118 external NTSC/PAL video encoder with Teletext port. TTXDATA Teletext Data Master Output This signal supplies teletext data external video encoder. L64118 outputs teletext data when TTXREQ asserted there enough bits teletext output buffer supply complete teletext line. default, this signal asserted after reset. GPIO13 Bidirectional TTXDATA serve general-purpose signal (GPIO13) setting General-Purpose Mode register. TTXREQ Teletext Data Request Master Input When HIGH, this signal indicates that external video encoder device requests teletext data transferred through TTXDATA. L64118 outputs teletext data TTXDATA long TTXREQ asserted. must program Video Encoder device length assertion TTXREQ compatible with exact number teletext bits line. L64118 Teletext port supports direct connection Teletext port NTSC/PAL video encoders. During normal operation, this input signal. default, this signal asserted after reset. GPIO12 Bidirectional TTXREQ serve general-purpose signal (GPIO12) setting General-Purpose Mode register.
SmartCard Port
These signals provide connection between L64118 external SmartCard devices. These signals used L64118 initialize external devices system with such port. L64118 supports independent SmartCard devices.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
SC0_C4
SmartCard Bidirectional This signal connected SmartCard. This signal should pulled external pull-up resistor after reset. SmartCard Bidirectional This signal connected SmartCard. This signal should pulled external pull-up resistor after reset. SmartCard Clock Output This signal output clock SmartCard GPIO33 Bidirectional SC0_CLK serve general-purpose signal (GPIO33) setting General-Purpose Mode register. default, this signal asserted after reset.
SC0_C8
SC0_CLK
SC0_DETECT SmartCard Detect Input When HIGH, this signal indicates that card inserted slot GPIO31 Bidirectional SC0_DETECT serve general-purpose signal (GPIO31) setting General-Purpose Mode register. default, this signal floats after reset. SC0_I/O SmartCard Bidirectional This signal transfers data (using coupler) between SmartCard SmartCard port L64118. open-drain. This signal must pulled external resistor after reset. SmartCard Reset This signal resets SmartCard Output
SC0_RSTn
GPIO30 Bidirectional SC0_RSTn serve general-purpose signal (GPIO30) setting General-Purpose Mode register. default, this signal asserted after reset.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
SC0_VCC_ENn SmartCard Enable Output This signal turns power supply SmartCard off. When LOW, enables supply. GPIO32 Bidirectional SC0_VCC_ENn serve general-purpose signal (GPIO32) setting General-Purpose Mode register. default, this signal asserted after reset. SC0_VPP_ENn SmartCard Enable Output This signal turns power supply SmartCard off. When LOW, enables supply. GPIO34 Bidirectional SC0_VPP_ENn serve general-purpose signal (GPIO34) setting General-Purpose Mode register. default, this signal asserted after reset. SC1_CLK SmartCard Clock This signal clocks output SmartCard1. Output
GPIO38 Bidirectional SC1_CLK serve general-purpose signal (GPIO38) setting General-Purpose Mode register. default, this signal asserted after reset. SC1_DETECT SmartCard Detect Input When HIGH, this signal indicates that card inserted slot GPIO36 Bidirectional SC1_CLK serve general-purpose signal (GPIO36) setting General-Purpose Mode register. default, this signal floats after reset.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
SC1_I/O
SmartCard Bidirectional This signal transfers data (using coupler) between SmartCard1 SmartCard port L64118. open-drain. This signal must pulled external resistor after reset. SmartCard Reset This signal resets SmartCard1. Output
SC1_RSTn
GPIO35 Bidirectional SC1_RSTn serve general-purpose signal (GPIO35) setting General-Purpose Mode register. default, this signal asserted after reset. SC1_VCC_ENn SmartCard Enable Output This signal turns power supply SmartCard1 off. When LOW, enables supply. GPIO37 Bidirectional SC1_VCC_ENn serve general-purpose signal (GPIO37) setting General-Purpose Mode register. default, this signal asserted after reset. SC1_VPP_ENn SmartCard Enable Output This signal turns power supply SmartCard off. When LOW, enables pin. GPIO39 Bidirectional SC1_VPP_ENn serve general-purpose signal (GPIO39) setting General-Purpose Mode register. default, this signal asserted after reset.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Infrared Port
These signals provide connection between L64118 external infrared receiver transmitter. IRBL Infrared Blaster Output This signal infrared blaster output. This signal configured reflect value infrared transmitter output. GPIO47 Bidirectional IRBL serve general-purpose signal (GPIO47) setting General-Purpose Mode register. default, this signal floats after reset. IRRX0 Infrared Receiver Input This signal serves receive port demodulated signal infrared receivers ports. GPIO40 Bidirectional IRRX0 serve general-purpose signal (GPIO40) setting General-Purpose Mode register. default, this signal floats after reset. IRRX1 Infrared Receiver Input This signal serves receive port demodulated signal infrared receivers ports. GPIO41 Bidirectional IRRX1 serve general-purpose signal (GPIO41) setting General-Purpose Mode register. default, this signal floats after reset.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
IRTX
Infrared Transmitter Output This signal serves infrared transmitter output. GPIO44 Bidirectional IRRX1 serve general-purpose signal (GPIO44) setting General-Purpose Mode register. default, this signal floats after reset.
General-Purpose Pins
general-purpose signals L64118 control monitor various external events. These signals consist eight groups. Group contains dedicated GPIO signals, whereas other groups multiplex GPIO signals with other functions. Note that pins within GPIO group must enabled disabled group; however, individual GPIO pins configured inputs outputs using General-Purpose Control register. GPIO groups associated pins listed Table through Table Table
Name CSn[4] BEn[2] BEn[3] SDQMH
Group EBus Signals
GPIO Signal1 GPIO1 GPIO2 GPIO4 GPIO6
GPIO3 GPIO5 signals available L64118.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Table
Name CTSn0 DTRn0 DSRn0 RTSn0 RXDn0
Group Signals
GPIO Signal GPIO7 GPIO8 GPIO9 GPIO10 GPIO11
Table
Name TTXREQ TTXDATA
Group Teletext Signals
GPIO Signal GPIO12 GPIO13
Table
Name AUTOFDn BUSY PDATA[7:0] FAULTn INITn PERROR SELECT SELECTINn STROBEn
Group (IEEE 1284) Signals
GPIO Signal GPIO14 GPIO15 GPIO[23:16] GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Table
Name SC0_RSTn
Group SmartCard Signals
GPIO Signal GPIO30 GPIO31 GPIO32 GPIO33 GPIO34
SC0_DETECT SC0_VCC_EN SC0_CLK SC0_VPP_ENn
Table
Name SC1_RSTn
Group SmartCard Signals
GPIO Signal GPIO35 GPIO36 GPIO37 GPIO38 GPIO39
SC1_DETECT SC1_VCC_ENn SC1_CLK SC1_VPP_ENn
Table
Name IRRX0 IRRX1 IRTX IRBL
Group Infrared Signals
GPIO Signal GPIO[40] GPIO[41] GPIO[44] GPIO[47]
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Table
Name GPIO[43:42] GPIO[46:45] GPIO[49:48]
Group Dedicated GPIO Signals
GPIO Signal GPIO[43:42] GPIO[46:45] GPIO[49:48]
GPIO[49, Dedicated GPIO Bidirectional These dedicated general-purpose signals. default, these signals float after reset. Note that Logic manufacturing test purposes, GPIO46 must pulled HIGH during reset.
Programming General-Purpose Pins
general-purpose pin, enable entire group writing General-Purpose Mode register; then select input/output each within group writing specific General-Purpose Control register. (Note that group more than general-purpose pins.) After each defined, programmer read value GPIO signal using General-Purpose Data registers, write value GPIO signal General-Purpose Data registers.
Latency GPIO Updates
GPIO pins intended controlling/monitoring external logic software. should consider delay between time when software writes value general-purpose output time value valid output pin. This delay caused transaction time between on-chip processor on-chip peripheral component, delay time general-purpose module. delay that general-purpose module inserts writing output general-purpose more than (for SCLK MHz).
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
When processor reads value from general-purpose configured input pin, there extra delay inserted; however, register holding general-purpose input values updated every (for SCLK MHz).
Electrical Requirements
This section specifies electrical requirements L64118. Five tables list electrical data following categories:
Absolute Maximum Ratings (Table Recommended Operating Conditions (Table Capacitance (Table Characteristics (Table Description Summary (Table
following tables provide maximum ratings, operating conditions, capacitances G10-p implementation L64118. Table
Symbol TSTGP
Absolute Maximum Ratings
Parameter Supply Compatible Input Voltage Input Voltage Input Current Storage Temperature Range (Plastic) Limits1 Unit
Referenced VSS.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Table
Symbol
Recommended Operating Conditions
Parameter Supply Ambient Temperature Limits Unit
Table
Symbol COUT
Capacitance
Parameter1 Input Capacitance Output Capacitance Capacitance Units
Measurement conditions clock frequency MHz.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Table
Symbol
Characteristics
Parameter Voltage Input CMOS Voltage Input High CMOS Compatible Voltage Output 2-mA Output Buffers 4-mA Output Buffers 6-mA Output Buffers Voltage Output High 2-mA Output Buffers 4-mA Output Buffers 6-mA Output Buffers Current Input Leakage2 with Pulldown with Pullup Current 3-State Output Leakage Current P-Channel Output Short Circuit (4-mA Output Buffers)3, Current N-Channel Output Short Circuit (4-mA Output Buffers)3, Quiescent Supply Current Dynamic Supply Current Max, VOUT Max, VOUT Max, VOUT Condition1 Units
IOSP4 IOSN4
Specified equals ambient temperature over specified range. CMOS inputs. more than output shorted time maximum duration second. These values scale proportionally output buffers with different drive strengths.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Table
Description Summary
Drive (mA) Pull-Up/ Down
Mnemonic ACKn/ AUXNM ACLK AD[31:0] ADDR[7:0] AD[15:0] AREQn AUTOFDn/ AUXV GPIO14 AVALID AVD[7:0] AVDD AVERRn AVSS BEn[1:0] BEn[3:2] GPIO[3:2] BUSY/ AUXSB GPIO15 CCLK CDATA[7:0] CERRn CPU_CLK CSn[3:0]
Description 1284 Acknowledge Match Audio Clock EBus Address/Data EBus Address/Data EBus Address/Data Audio Data Request EBus Address Latch Enable 1284 Auto Feed Data Valid General-Purpose Audio Data Valid Audio/Video Data Analog Power Audio/Video Error Analog Ground EBus Byte Enable EBus Byte Enable 1284 Busy Sync Byte General-Purpose Channel Data Clock Channel Data Channel Data Error EBus Clock Output EBus Chip Select
Type1 Output Output Output Bidirectional Bidirectional Bidirectional Input Output Input Bidirectional Bidirectional Output Bidirectional Input Output Input Bidirectional Output Bidirectional Bidirectional
Active2 HIGH
HIGH
Input Input Input Output Output
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Table
Description Summary (Cont.)
Type1 Output Bidirectional Output Input Bidirectional Input Input Input Bidirectional Output Bidirectional Input Input Bidirectional Drive (mA) Active2 HIGH Pull-Up/ Down
Mnemonic CSn[4] GPIO1 CSn[5] MEMSTBn CTSn0 GPIO7 CTSn1 ICECLK CVALID DSRn0 GPIO9 DTRn0 GPIO8 EACKn ECLK FAULTn/ AUXCLK GPIO24 GPIO[42:43] GPIO[46:45] GPIO[48:49] IDDTN INITn/ AUXPID[2] GPIO25 INTn[3:0] INTn4 IRBL GPIO47
Description EBus Chip Select General-Purpose EBus Chip Select Memory Strobe Clear Send (SIO General-Purpose Clear Send (SIO Serial Clock Channel Data Enable Data Send Ready (SIO General-Purpose Data Terminal Ready (SIO General-Purpose EBus Data Acknowledge Test Clock 1284 Fault Port Clock General-Purpose General-Purpose General-Purpose General-Purpose Test 1284 Initialization Packet General-Purpose Interrupt Interrupt Blaster General-Purpose
Bidirectional Bidirectional Bidirectional Input Input Output Bidirectional Input Bidirectional (open drain) Output Bidirectional
HIGH
HIGH
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Table
Description Summary (Cont.)
Drive (mA) Pull-Up/ Down
Mnemonic IREF IRRX0 GPIO40 IRRX1 GPIO41 IRTX GPIO44 OP_MODE[1:0] PDATA[7:0] PDATA_DIR OP_MODE[2] PERROR/ AUXPID[0] GPIO26 PLLVDD PLLVSS RCLK RESETn
Description Current Reference Receiver Port General-Purpose Receiver Port General-Purpose Transmitter Port General-Purpose Operational Mode 1284 Data 1284 Data Direction Operational Mode[2] 1284 Peripheral Error Packet General-Purpose Analog Analog UART Receive Clock (SIO EBus Read Strobe Reset
Type1 Input Bidirectional Input Bidirectional Output Bidirectional Input Bidirectional Output Input Output Output Bidirectional Input Input Input Output Input (Schmitt trigger) Output Bidirectional Output Input Bidirectional Input Input Output
Active2 HIGH
RTSn0 GPIO10 RTSn1 RXD0 GPIO11 RXD1/ ICE_RX RXD2 SA[11:0]
Request Send (SIO General-Purpose Request Send (SIO Receive Data (SIO General-Purpose Receive Data (SIO Receive Data Serial Port Receive Data (SIO SDRAM Address
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Table
Description Summary (Cont.)
Type1 Output Output Bidirectional Bidirectional (open drain) Bidirectional (open drain) Output Bidirectional Input Bidirectional Bidirectional (open drain) Output Bidirectional Output Bidirectional Output Bidirectional Output Bidirectional Input Bidirectional Bidirectional (open drain) Output Bidirectional Output Bidirectional Output Bidirectional Drive (mA) Active2 HIGH HIGH Pull-Up/ Down
Mnemonic SBA[0] SBA[1] SBD[15:0] SC0_C4 SC0_C8 SC0_CLK GPIO33 SC0_DETECT GPIO31 SC0_I/O SC0_RSTn GPIO30 SC0_VCC_ENn GPIO32 SC0_VPP_ENn GPIO34 SC1_CLK GPIO38 SC1_DETECT GPIO36 SC1_I/O SC1_RSTn GPIO35 SC1_VCC_ENn GPIO37 SC1_VPP_ENn GPIO39
Description SDRAM Bank Select SDRAM Bank Select SDRAM Data SmartCard SmartCard SmartCard Clock General-Purpose SmartCard Detect General-Purpose SmartCard Data SmartCard Reset General-Purpose SmartCard Enable General-Purpose SmartCard Enable General-Purpose SmartCard Clock General-Purpose SmartCard Detect General-Purpose SmartCard Data SmartCard Reset General-Purpose SmartCard Enable General-Purpose SmartCard Enable General-Purpose
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Table
Description Summary (Cont.)
Drive (mA) Pull-Up/ Down
Mnemonic SCASn SCLK SDCLK SDET SDQMH GPIO6 SDQML SELECT/ AUXPID[1] GPIO27 SELECTINn/ AUX_ADP/ AUX_ERR GPIO28 SRASn STROBEn/ AUX_TX GPIO29 SWEn TCLK
Description SDRAM Column Address Strobe Clock System Clock MHz) Data SDRAM Master Clock Sigma-Delta Control Voltage Output SDRAM Data Mask High Byte General-Purpose SDRAM Data Mask Byte 1284 Selection Packet 1284 Selection Indicator Adaptation Field Flag Error Indicator General-Purpose SDRAM Address Strobe 1284 Data Strobe Port Direction General-Purpose SDRAM Write Enable UART Transmit Clock (SIO JTAG Scan Clock JTAG Scan JTAG Scan JTAG Mode
Type1 Output Bidirectional (open drain) Input Bidirectional (open drain) Output Output (open drain) Output Bidirectional Output Output Output Bidirectional Input Output Input Bidirectional Output Input Input Bidirectional Output Input Input Input Output (3-State) Input
Active2 HIGH
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Table
Description Summary (Cont.)
Type1 Input Output Bidirectional Input Bidirectional Output Output Output Input Output Output Input Drive (mA) Active2 HIGH HIGH HIGH Pull-Up/ Down
Mnemonic TRST TTXDATA GPIO13 TTXREQ GPIO12 TXD0 TXD1 ICE_TX TXD2 VREQn VVALID ZTESTn
Description JTAG Reset Teletext Data General-Purpose Teletext Request General-Purpose Transmit Data (SIO Transmit Data (SIO Transmit Data Serial ICEPort Transmit Data (SIO Power Video Data Request Ground Video Data Valid EBus Write Strobe Test
only type listed, applies possible configurations. only active state (LOW HIGH) listed, applies possible configurations. internal pull-up resistor value from 50-100 internal pull-down resistor value from 50-100
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Packaging Pinouts
Figure shows signal solder balls L64118. This diagram shows location, ball number, signal each solder ball 256-pin Plastic Ball Grid Array (PBGA) package (package code IF). This pinout drawing followed
listing solder balls numerical order L64118 (Table listing solder balls alphabetic order L64118 (Table mechanical drawings that provide dimensions L64118 (Figure Note: drawings this section same origin. other words, solder ball Figure Figure same.
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
IRTX GPIO48 IRRX1 TXD2 AVD[7] AVD[1] TRST SDET AVD[6] AVD[5] AVD[3] RXD2 IRBL GPIO45/ CDATA[0] CDATA[4] RCLK MODE[1] AVD[0] AVALID VREQn SC0_ RSTn SC0_ SC1_ RSTn SC1_ VCC_ SC1_CLK AD[14] AD[13] SC0_ DETECT SC0_C4 SC0_VPP_ AVERRn GPIO42 CERRn CDATA[6] CDATA[7] CDATA[1] CDATA[5] ECLK CDATA[3] CDATA[2] GPIO46 GPIO49 SCLK AVD[2] CVALID CCLK IDDTN AVD[4] VVALID AREQn PLLVSS MODE[0] SC0_IO SC0_ VCC_ SC1_ VPP_ SC0_C8 SC1_ DETECT AD[15] SA[0] SC1_IO AD[12] AD[11] AD[10] AD[9] SA[10] AD[8] AD[7] AD[6] AD[5]
Figure
ACLK
GPIO43
IRRX0
PLLVDD
IREF
AVDD
SA[1]
ZTESTn
AVSS
SA[4]
SA[2]
SDCLK
SA[6]
SA[5]
SA[3]
SA[9]
SA[8]
SA[7]
SRASn
SBA[1]
SBA[0]
SA[11]
L64118 256-Pin PBGA Pinout
SDQMH
SWEn
SCASn
AD[3]
AD[4]
AD[2]
SDQML
SBD[14] SBD[15]
ADDR[1] ADDR[0] ADDR[5] ADDR[4]
AD[0] ADDR[3]
AD[1] ADDR[2]
SBD[13]
SBD[12] SBD[11]
SBD[10]
SBD[9]
SBD[8]
SBD[7]
AD[16]
ADDR[7]
ADDR[6]
SBD[6]
SBD[5]
SBD[4]
SBD[1]
AD[23]
AD[20]
AD[18]
AD[17]
SBD[3]
SBD[2]
SBD[0]
AD[24]
AD[21]
AD[19]
RXD1 PERROR
TTXREQ TTXDATA DSRn0
TXD0
AD[29]
AD[27]
AD[25]
AD[22]
SELECT PDATA[0] PDATA[4]
CTSn0
DTRn0
PDATA[7] STROBEn
CSn2
CPU_CLK
AD[30]
AD[26]
FAULTn ACKn PDATA[2] PDATA[5]
TCLK
SELECTINn INITn
INTn2
CSn1
CSn5/ MEMSTBn INTn1 CSn0 CSn4
BEn2
EACKn
AD[28]
RTSn0
CTSn1
BEn3
BEn0
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
TXD1 BUSY PDATA[1] PDATA[3] PDATA[6] AUTOFDn INTn4 INTn3 INTn0 CSn3 RESETn BEn1 AD[31]
RXD0
PDATA_ DIR/OP_ MODE[2]
RTSn1
Table
Solder Ball
L64118 Solder Ball Matrix List
Signal Solder Ball
Signal
Solder Signal Ball
SA[7] AD[11] AD[10] AD[9] SBA[1] SBA[0] SA[11] SA[10] AD[8] AD[7] AD[6] AD[5] SDQMH SWEn SCASn SRASn AD[3] AD[4] AD[2] SDQML SBD[14] SBD[15] ADDR[1] ADDR[0] AD[0] AD[1] SBD[13] SBD[12] SBD[11] SBD[10] ADDR[5] ADDR[4] ADDR[3] ADDR[2] SBD[9] SBD[8] SBD[7] AD[16] ADDR[7] ADDR[6] SBD[6] SBD[5] SBD[4] SBD[1] AD[23] AD[20] AD[18]
Solder Ball
Signal Solder Signal Ball
AD[28] RTSn0 CTSn1 FAULTn ACKn PDATA[2] PDATA[5] INITn INTn1 CSn0 CSn4 BEn3 BEn0 RXD0 PDATA_DIR/ OP_MODE[2] RTSn1 TXD1 BUSY PDATA[1] PDATA[3] PDATA[6] AUTOFDn INTn4 INTn3 INTn0 CSn3 RESETn BEn1 AD[31]
ACLK GPIO43 IRTX IRBL GPIO48 GPIO45/RCLK CDATA[0] CDATA[4] TRST SDET AVD[6] AVD[5] AVD[3] RXD2 AVERRn SC0_VPP_ENn IRRX0 GPIO42 CERRn CDATA[6] CDATA[7] CDATA[1] CDATA[5] TXD2 AVD[7] OP_MODE[1] AVD[1] IRRX1 SC0_DETECT PLLVDD ECLK CDATA[3] CDATA[2] GPIO46 GPIO49 SCLK AVD[2]
AVD[0] AVALID VREQn SC0_RSTn SC0_C4 IREF AVDD CVALID CCLK IDDTN OP_MODE[0] AVD[4] VVALID AREQn SC0_IO SC0_CLK SC0_C8 SA[1] ZTESTn AVSS PLLVSS SC0_VCC_ENn SC1_VPP_ENn SC1_RSTn SC1_DETECT SA[4] SA[2] SDCLK SC1_CLK SC1_VCC_ENn AD[15] SA[6] SA[5] SA[3] SA[0] SC1_IO AD[14] AD[13] AD[12] SA[9] SA[8]
AD[17] SBD[3] SBD[2] SBD[0] AD[24] AD[21] AD[19] TTXREQ TTXDATA DSRn0 TXD0 AD[29] AD[27] AD[25] AD[22] CTSn0 DTRn0 RXD1 PERROR PDATA[7] STROBEn CSn2 CPU_CLK AD[30] AD[26] TCLK SELECT PDATA[0] PDATA[4] SELECTINn INTn2 CSn1 CSn5/MEMSTBn BEn2 EACKn
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Table
Signal
ACKn ACLK AD[0] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[1] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[2] AD[30] AD[31] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] ADDR[0] ADDR[1] ADDR[2] ADDR[3] ADDR[4] ADDR[5] ADDR[6] ADDR[7] AREQn AUTOFDn AVALID AVD[0] AVD[1] AVD[2] AVD[3] AVD[4] AVD[5] AVD[6]
L64118 Alphabetical Signal List
Solder Ball
Signal
Solder Ball
Signal
Solder Ball
Signal
Solder Signal Ball
Solder Ball
AVD[7] AVDD AVERRn AVSS BEn0 BEn1 BEn2 BEn3 BUSY CCLK CDATA[0] CDATA[1] CDATA[2] CDATA[3] CDATA[4] CDATA[5] CDATA[6] CDATA[7] CERRn CPU_CLK CSn0 CSn1 CSn2 CSn3 CSn4 CSn5/MEMSTBn CTSn0 CTSn1 CVALID DSRn0 DTRn0 EACKn ECLK FAULTn GPIO42 GPIO43 GPIO45/RCLK GPIO46 GPIO48 GPIO49 IDDTN INITn INTn0 INTn1 INTn2 INTn3 INTn4 IRBL IREF IRRX0 IRRX1 IRTX
OP_MODE[0] OP_MODE[1] PDATA[0] PDATA[1] PDATA[2] PDATA[3] PDATA[4] PDATA[5] PDATA[6] PDATA[7] PDATA_DIR/ OP_MODE[2] PERROR PLLVDD PLLVSS RESETn RTSn0 RTSn1 RXD0 RXD1
RXD2 SA[0] SA[10] SA[11] SA[1] SA[2] SA[3] SA[4] SA[5] SA[6] SA[7] SA[8] SA[9] SBA[0] SBA[1] SBD[0] SBD[10] SBD[11] SBD[12] SBD[13] SBD[14] SBD[15] SBD[1] SBD[2] SBD[3] SBD[4] SBD[5] SBD[6] SBD[7] SBD[8] SBD[9] SC0_C4 SC0_C8 SC0_CLK SC0_DETECT SC0_IO SC0_RSTn SC0_VCC_ENn SC0_VPP_ENn SC1_CLK SC1_DETECT SC1_IO SC1_RSTn SC1_VCC_ENn SC1_VPP_ENn SCASn SCLK SDCLK SDET SDQMH SDQML
SELECT SELECTINn SRASn STROBEn SWEn TCLK TRST TTXDATA TTXREQ TXD0 TXD1 TXD2 VREQn VVALID ZTESTn
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Figure 256-Pin PBGA Package (IF) Mechanical Drawing
MD98.IF
Important:
This drawing latest version. board layout manufacturing, obtain most recent engineering drawings from your Logic marketing representative requesting outline drawing package code
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Notes
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Notes
L64118 MPEG-2 Transport Controller with Embedded MIPS (TR4101)
Sales Offices Design Resource Centers
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Tel: 408.433.8000
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Tel: 81.6.947.5281
Osaka
Sales Offices with
Fax: 81.6.947.5287
Design Resource Centers
receive product literature, call 1-800-574-4286 (U.S. Canada); +32.11.300.531 (Europe); 408.433.7700 (outside U.S., Canada, Europe) Department JDS; visit http://www.lsilogic.com
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This document preliminary. such, contains data derived from functional simulations performance estimates. Logic verified functional descriptions electrical mechanical specifications using production parts. Logic logo design, G10, CoreWare registered trademarks TinyRISC trademark Logic Corporation. other brand product names trademarks their respective companies.
Printed Order I15038 Doc. DB08-000109-01
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