HEF4007UB gates Dual complementary pair inverter Product specific

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HEF4007UB gates Dual complementary pair inverter Product specific

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IC04 LOCMOS HE4000B Logic Family Specifications HEF, IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,
HEF4007UB gates Dual complementary pair inverter
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
Dual complementary pair inverter
DESCRIPTION
HEF4007UB gates
HEF4007UB dual complementary pair inverter with access each device. three n-channel three p-channel enhancement mode transistors.
Fig.1 Schematic diagram.
PINNING SP2, DP1, DN1, SN2, Fig.2 Pinning diagram. DN/P3 HEF4007UBP(N): HEF4007UBD(F): HEF4007UBT(D): 14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) 14-lead plastic (SOT108-1) Package Designator North America FAMILY DATA, LIMITS category GATES Family Specifications VIH/VIL unbuffered stages source connections p-channel transistors drain connections from p-channel transistors drain connections from n-channel transistors source connections n-channel transistors common connection p-channel n-channel transistor drains gate connections n-channel p-channel three transistor pairs
January 1995
Philips Semiconductors
Product specification
Dual complementary pair inverter
CHARACTERISTICS Tamb input transition times Propagation delays HIGH HIGH Output transition times HIGH HIGH tTLH tTHL tPLH tPHL SYMBOL TYP. MAX.
HEF4007UB gates
TYPICAL EXTRAPOLATION FORMULA (0,55 ns/pF) (0,23 ns/pF) (0,16 ns/pF) (0,55 ns/pF) (0,23 ns/pF) (0,16 ns/pF) (1,0 ns/pF) (0,42 ns/pF) (0,28 ns/pF) (1,0 ns/pF) (0,42 ns/pF) (0,28 ns/pF)
Dynamic power dissipation package
TYPICAL FORMULA (µW) 4500 (foCL) VDD2 (foCL) (foCL) VDD2 VDD2 where input freq. (MHz) output freq. (MHz) load capacitance (pF) (foCL) outputs supply voltage
January 1995
Philips Semiconductors
Product specification
Dual complementary pair inverter
HEF4007UB gates
Fig.3
Typical drain current output voltage functions input voltage; Tamb
Fig.4
Typical drain current output voltage functions input voltage; Tamb
Fig.5
Typical drain current output voltage functions input voltage; Tamb
January 1995
Philips Semiconductors
Product specification
Dual complementary pair inverter
APPLICATION INFORMATION Some examples applications HEF4007UB are: High input impedance amplifiers Linear amplifiers (Crystal) oscillators High-current sink source drivers High impedance buffers.
HEF4007UB gates
Fig.6
Voltage gain (Vo/Vi) function supply voltage.
Fig.7
Supply current function supply voltage.
This also example analogue amplifier using HEF4007UB gate.
Fig.8
Test set-up measuring graphs Figs
January 1995
Philips Semiconductors
Product specification
Dual complementary pair inverter
HEF4007UB gates
Fig.9 Test set-up measuring forward transconductance dio/dvi constant (see also graph Fig.10).
average, average average where observed standard deviation.
Fig.10 Typical forward transconductance function supply voltage Tamb
January 1995
Philips Semiconductors
Product specification
Dual complementary pair inverter
Figures show some applications which HEF4007UB used.
HEF4007UB gates
Fig.11 crystal oscillator.
Fig.12 High current sink driver.
Fig.13 High current source driver.
January 1995
Philips Semiconductors
Product specification
Dual complementary pair inverter
FUNCTION TABLE Fig.14. INPUT Notes DISABLE
HEF4007UB gates
OUTPUT open
HIGH state (the more positive voltage) state (the less positive voltage) state immaterial NOTE Rules maintaining electrical isolation between transistors monolithic substrate: number must maintained most positive equally positive) potential with respect other HEF4007UB. number must maintained most negative equally negative) potential with respect other HEF4007UB. Violation these rules will result improper transistor operation and/or possible permanent damage HEF4007UB.
Fig.14 High impedance buffer.
January 1995

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