Communications Clock Jitter Attenuator MK2058-01 VCXO (Voltage Co

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Communications Clock Jitter Attenuator MK2058-01 VCXO (Voltage Co

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MK2058-01
Communications Clock Jitter Attenuator
MK2058-01 VCXO (Voltage Controlled Crystal Oscillator) based clock jitter attenuator designed used system clock distribution applications. This monolithic combined with external inexpensive quartz crystal, used replace more costly hybrid VCXO retiming module. device accepts outputs same clock frequency selectable ranges covering 4kHz 27MHz. dual input also provided. controlling VCXO frequency within phase-locked loop (PLL), output clock phase frequency locked input clock. Through selection external loop filter components, loop bandwidth damping factor tailored meet system clock requirements. loop bandwidth down range possible.
Features
Jitter attenuation Frame Sync other
common telecom clock frequencies Also serves general purpose clock jitter attenuator distributed system clocks recovered data video clocks Input input reference clocks VCXO-based clock generation offers very jitter phase noise generation Output clock phase frequency locked selected input reference clock Fixed input output phase relationship Guaranteed lock input reference over +/-32ppm frequency range (using recommended external pullable crystal) Industrial temperature range power CMOS technology SOIC package Single 3.3V power supply
Block Diagram
ullable xtal
lock lock
etecto arge
Selectable ivider
CHGP
2058-01
Revision 020501
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
MK2058-01 Communications Clock Jitter Attenuator
Assignment
CHGP
Output Clock Selection Table
SEL2 SEL1 SEL0
Input Output Range 8.79 13.2 15.734kHz 13.5 13.5
Crystal Frequency 3072 ICLK ICLK ICLK ICLK 2048 ICLK 1716 ICLK ICLK ICLK ICLK ICLK ICLK ICLK
Note: input programming: GND, VDD, Floating
Descriptions
Number
Name
CHGP SEL2 SEL1 SEL0 ICLK2 ICLK1 ISEL
Type
Power Power Power Input Power Power Power Output Input Input Input Output Input Input Input Input Power
Crystal Input. Connect this specified crystal. Power Supply. Connect +3.3V. Power Supply. Connect +3.3V. Power Supply. Connect +3.3V. VCXO Control Voltage Input. Connect this CHGP external loop filter shown this data sheet. Ground Ground Ground Charge Pump Output. Connect this external loop filter VIN. Connection Charge Pump Current Setting Resistor. Output Frequency Selection Determines output frequency table above. Internally biased VDD/2. Output Frequency Selection Determines output frequency table above. Internal pull-up. Internal Connection. Clock Output Output Frequency Selection Determines output frequency table above. Internal pull-up. Input Clock Connection Connect input reference clock this pin. Input Clock Connection Connect input reference clock this pin. Input Selection. Used select which reference input clock active. input level selects ICLK1, high input level selects ICLK2. Internal pull-up. Ground Crystal Output. Connect this specified crystal.
2058-01
Revision 020501
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
MK2058-01 Communications Clock Jitter Attenuator
Functional MK2058-01 clock generator that generates output clock directly from internal VCXO, which works conjunction with external quartz crystal. VCXO controlled internal (Phase Locked Loop) circuit, enabling device perform clock regeneration from input reference clock. MK2058-01 configured provide output clock that same frequency input clock. There selectable input output frequency ranges, each which submultiple supported quartz crystal frequency range. Please refer Output Clock Selection Table page Most clock devices (Voltage Controlled Oscillator) output clock generation. using VCXO, MK2058-01 able generate jitter, phase-noise output clock within bandwidth PLL. serves provide jitter attenuation enables stable operation with frequency reference clock. VCXO circuit requires external pullable crystal operation. External loop filter components enable configuration with loop bandwidth.
External Component Schematic
CHGP
External Component Selection
MK2058-01 requires minimum number external components proper operation. Please refer External Component Schematic this page.
Loop Filter Components
Referring External Component Schematic, external loop filter made components RSET, which establishes charge pump current, also affects loop filter dynamics. good loop stability jitter attenuation characteristics following component values used: RSET 11.8 (may caps parallel) questions changes regarding loop filter characteristics, please contact ICS, MicroClock Applications. Loop filter components (including RSET) should mounted close device possible. should high quality ceramic capacitors. type polarized electrolytic capacitor. Ceramic capacitors should have dielectric. Another alternative Panasonic polymer dielectric series. Panasonic part number ECHU1C104JB5. Avoid high-K dielectrics
Decoupling Capacitors
Decoupling capacitors 0.01µF must connected between each GND, close possible. optimum device performance, decoupling capacitor should mounted component side PCB. Avoid vias decoupling circuit. (Decoupling capacitors shown External Component Schematic.)
Series Termination Resistor
Clock traces over inch should series termination. series terminate trace commonly used trace impedance) place resistor series with clock line, close clock output possible. nominal impedance clock output (The optional series termination resistor shown External Component Schematic.)
2058-01
Revision 020501
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
MK2058-01 Communications Clock Jitter Attenuator
like X7R. These other ceramics which have piezoelectric properties allow mechanical vibration system increase output jitter, because mechanical energy converted directly voltage noise VCXO input.
Crystal Load Capacitors
crystal traces should include pads small capacitors from ground, shown External Component Schematic. These capacitors used adjust stray capacitance board match crystal load capacitance. typical telecom reference frequency accurate much less than ppm, MK2058-01 lock properly even board capacitance adjusted with these fixed capacitors. However, MicroClock recommends that adjustment capacitors included minimize effects variation individual crystals, included those induced temperature aging. value these capacitors (typically determined once given board layout, using procedure described section titled "Optimization Crystal Load Capacitors".
Quartz Crystal
MK2058-01 operates phase-locking VCXO circuit input signal selected ICLK input. VCXO consists external crystal integrated VCXO oscillator circuit. achieve best performance reliability, crystal device with recommended parameters (shown below) must used, layout guidelines discussed following section shown must followed. frequency oscillation quartz crystal determined load capacitors connected MK2058-01 incorporates variable load capacitors on-chip which "pull", change, frequency crystal. crystals specified with MK2058-01 designed have zero frequency error when total on-chip stray capacitance 14pF. achieve this, layout should short traces between MK2058-01 crystal. complete description recommended crystal parameters shown below. Recommended Crystal Parameters: Operating Temperature Range Commercial Applications Industrial Applications Initial Accuracy 25°C Temperature Stability Aging Load Capacitance Shunt Capacitance, C0/C1 Ratio Equivalent Series Resistance 70°C 85°C Note
Layout Recommendation
proper board layout critical successful MK2058-01. particular, loop filter network very sensitive noise leakage. must well cleaned dried before testing. Traces must short possible must mounted next device. output clock should have series termination connected close pin, particularly clock trace over inch. Additional improvements will come from keeping components same side board, minimizing vias through other signal layers, routing other signals away from MK2058-01. also refer MAN05 additional suggestions layout crystal section.
Optimization Crystal Load Capacitors
determine crystal adjustment capacitor values, will need board your final layout, frequency counter capable less than resolution accuracy, power supplies, some samples crystals which plan production, along with measured initial accuracy each crystal specified crystal load capacitance, determine value crystal capacitors:
Note Nominal crystal load capacitance specification varies with frequency. Contact MicroClock applications department (408)297-1201. obtain list qualified crystal devices that meet these requirements, please contact MicroClock applications department.
2058-01
Revision 020501
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
MK2058-01 Communications Clock Jitter Attenuator
Connect MK2058-01 3.3V. Connect MK2058-01 second power supply. Adjust voltage Measure record frequency output. Adjust voltage 3.3V. Measure record frequency same output. calculate centering error:
stray capacitance will need redone with layout reduce stray capacitance. (The crystal re-specified lower load capacitance instead. Contact MicroClock details.) centering error more than positive, identical fixed centering capacitors from each crystal ground. value each these caps given External Capacitor (centering error)/(trim sensitivity) Trim sensitivity parameter which supplied your crystal vendor. know value, assume ppm/pF. After changes, repeat measurement verify that remaining error acceptably (less than ±15ppm). MicroClock Applications department perform this procedure your board. Call 408-295-9800, will arrange send board (stuffed unstuffed) your crystals. will calculate value capacitors needed.
3.0V Error error xtal
Where: ftarget nominal crystal frequency errorxtal =actual initial accuracy ppm) crystal being measured centering error less than ppm, adjustment needed. centering error more than negative, board much
Absolute Maximum Ratings
Stresses above ratings listed below cause permanent damage MK2058-01. These ratings, which standard values commercially rated parts, stress ratings only. Functional operation device these other conditions above those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect product reliability. Electrical parameters guaranteed only over recommended operating temperature range.
Item
Supply Voltage, Inputs Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature
Rating
-0.5V VDD+0.5V +85°C +150°C 175°C 260°C
2058-01
Revision 020501
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
MK2058-01 Communications Clock Jitter Attenuator
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured respect GND)
Min.
+3.15
Typ.
+3.3
Max.
+3.45
Units
Electrical Characteristics
Unless stated otherwise, 3.3V ±5%, Ambient Temperature +85°C
Parameter
Operating Voltage Supply Current Input High Voltage, SEL2 Input Voltage, SEL2 Input High Voltage, ISEL, SEL1:0 Input Voltage, ISEL, SEL1:0 Input High Voltage, ICLK1/2 Input Voltage, ICLK1/2 Input High Current Input Current Input Capacitance, except Output High Voltage (CMOS Level) Output High Voltage Output Voltage Short Circuit Current VIN, VCXO Control Voltage
Symbol
Conditions
Clock outputs unloaded, 3.3V
Min.
3.15
Typ.
Max.
3.45
VDD/2-1
Units
VDD-0.5
VDD/2+1
VDD-0.4
Electrical Characteristics
Unless stated otherwise, 3.3V ±5%, Ambient Temperature +85°
Parameter
VCXO Crystal Pull Range Output Frequency Error Output Duty Cycle high time)
Symbol
FOUT
Conditions
Using Recommended Crystal ICLK exactly 8kHz Measured VDD/2, CL=15pF
Min.
-100
Typ.
Max. Units
+100
2058-01
Revision 020501
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
MK2058-01 Communications Clock Jitter Attenuator
Parameter
Output Rise Time Output Fall Time Skew, Input Output Clock Nominal Output Impedance
Symbol
ZOUT
Conditions
2.0V, CL=15pF 0.8V, CL=15pF Rising edges, CL=15pF
Min.
Typ.
Max. Units
Package Outline Package Dimensions SOIC, Mil. Wide Body)
Package dimensions kept current with JEDEC Publication
Millimeters Symbol Inches
Index
-2.65 1.10 -2.05 2.55 0.33 0.51 0.18 0.32 12.60 13.00 7.40 7.60 1.27 Basic 10.00 10.65 0.25 0.75 0.40 1.27
-0.104 0.0040 -0.081 0.100 0.013 0.020 0.007 0.013 0.496 0.512 0.291 0.299 0.050 Basic 0.394 0.419 0.010 0.029 0.016 0.050
Ordering Information
Part Order Number
MK2058-01SI MK2058-01SITR
Marking
MK2058-01SI MK2058-01SI
Shipping packaging
Tubes Tape Reel
Package
SOIC SOIC
Temperature
+85° +85°
2058-01
Revision 020501
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com

Communications Clock Jitter Attenuator MK2058-01 VCXO (Voltage Co

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