MH8S72BBFD-7, 603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous D

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MH8S72BBFD-7, 603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous D

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MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
PRELIMINARY
Some contents subject change without notice.
DESCRIPTION
MH8S72BBFD 8388608 word 72-bit Synchronous DRAM module. This consist nine industry standard Synchronous DRAMs TSOP. mounting TSOP card edge dual in-line package provides application where high densities large quantities memory required. This socket-type memory module ,suitable easy interchange addition module.
85pin
1pin
FEATURES
Type name Max. Frequency Access Time [component level]
94pin 95pin
10pin 11pin
MH8S72BBFD-7 MH8S72BBFD-8
100MHz 100MHz
Utilizes industry standard Synchronous DRAMs TSOP package industry standard Resistered buffer TSSOP package industry standard TSSOP package Single 3.3V 0.3V supply LVTTL Interface Burst length 1/2/4/8/Full Page(programmable) Burst Write Single Write(programmable) Auto precharge bank precharge controlled Auto refresh Self refresh 4096 refresh cycles every 64ms Discrete module design conform PC/100 specification. (module Spec. Rev. 1.2A)
Back side
Front side
124pin 125pin
40pin 41pin
APPLICATION
Main memory unit computers, Microcomputer memory.
168pin
84pin
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
NAME DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 /WE0 DQMB0 DQMB1
NAME DQMB2 DQMB3 DQ16 DQ17 DQ18 DQ19 DQ20 CKE1 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 TEST
NAME DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 /CAS DQMB4 DQMB5 /RAS
NAME CKE0 DQMB6 DQMB7 DQ48 DQ49 DQ50 DQ51 DQ52 REGE DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
Connection
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
RDQMB0
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
/RS0 RDQMB4
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
RDQMB1
RDQMB5
RDQMB6
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
/RS2 RDQMB2
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
RDQMB7
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
RDQMB3
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
SERIAL
DQMB0 DQMB7 BA0-BA1 A0-A11 /RAS /CAS CKE0 REGE
/RS0 /RS2 RDQMB0 RDQMB7 BA0-BAN:D0-D8 RBA0-RBA1 A0-A11:D0-D8 RA0-RA11 /RAS: D0-D8 R/RAS /CAS: D0-D8 R/CAS RCKE0 /WE:D0-D8 R/WE
Terminated
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
FUNCTION
Input Master Clock:All other inputs referenced rising edge Clock Enable:CKE controls internal clock.When low,internal clock following cycle ceased. also used select auto self refresh. After self refresh mode started, becomes asynchronous input.Self refresh maintained long low. Chip Select: When high,any command means Operation. Combination /RAS,/CAS,/W defines basic commands. A0-11 specify Row/Column Address conjunction with BA.The Address specified A0-11.The Column Address specified A0-8.A10 also used indicate precharge option.When high read write command, auto precharge performed. When high precharge command, both banks precharged. Bank Address:BA0,1 simply BA.BA0,1 specifies bank which command applied.BA must with ACT,PRE,READ,WRITE commands
CKE0
Input
/S0,2 /RAS,/CAS,/W
Input Input
A0-11
Input
BA0-1 DQ0-63 CB0-7
Input
Data Data referenced rising edge Input/Output Mask/Output Disable:When DQMB high burst write.Din current cycle masked.When DQMB high burst read,Dout disabled next cycle.
DQM0-7
Input
Vdd,Vss
Power Supply Power Supply memory mounted module. Register enable:When REGE low,All control signals address buffered. (Buffer mode) When REGE high,All control address latched. (Latch mode)
REGE
Output
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
BASIC FUNCTIONS
MH8S72BBFD provides basic read write, bank(row)precharge,and auto self refresh. Each command defined control signals /RAS,/CAS rising edge. addition signals,/S,CKE used chip select,refresh option,and precharge option,respectively. know detailed definition commands please command truth table.
/RAS /CAS
Chip Select L=select, H=deselect Command Command Command Refresh Option @refresh command Precharge Option @precharge read/write command define basic commands
Activate(ACT) [/RAS /CAS command activates idle bank indicated Read(READ) [/RAS =H,/CAS READ command starts burst read from active bank indicated BA.First output data appears after /CAS latency. When this command,the bank deactivated after burst read(auto-precharge,READA). Write(WRITE) [/RAS /CAS WRITE command starts burst write active bank indicated Total data length written burst length. When this command, bank deactivated after burst write(auto-precharge,WRITEA). Precharge(PRE) [/RAS /CAS =H,/WE command deactivates active bank indicated This command also terminates burst read write operation. When this command, both banks deactivated(precharge all, PREA). Auto-Refresh(REFA) [/RAS =/CAS =CKE PEFA command starts auto-refresh cycle. Refresh address including bank address generated internally. After this command, banks precharged automatically.
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
COMMAND TRUTH TABLE
COMMAND Deselect Operation Adress Entry Bank Activate Single Bank Precharge Precharge Bank Column Address Entry Write Column Address Entry Write with AutoPrecharge Column Address Entry Read Column Address Entry Read with Auto Precharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register MNEMONIC DESEL PREA WRITE /RAS /CAS A0-9
WRITEA
READ
READA REFA REFS REFSX TERM
=High Level, Level, Valid, Don't Care, cycle number NOTE: 1.A7-9 A0-6 Mode Address
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
FUNCTION TRUTH TABLE
Current State IDLE ACTIVE READ /RAS /CAS BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 Address Command DESEL TBST PRE/PREA REFA DESEL TBST READ/READA WRITE/ WRITEA PRE/PREA REFA DESEL TBST ILLEGAL*2 Bank Active,Latch NOP*4 Auto-Refresh*5 Mode Register Set*5 Begin Read,Latch Determine Auto-Precharge Begin Write,Latch Determine Auto-Precharge Bank Active/ILLEGAL*2 Precharge/Precharge ILLEGAL ILLEGAL NOP(Continue Burst END) NOP(Continue Burst END) Terminate Burst Terminate Burst,Latch READ/READA Begin Read,Determine Auto-Precharge*3 Terminate Burst,Latch BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add WRITE/WRITEA Begin Write,Determine AutoPrecharge*3 PRE/PREA REFA Bank Active/ILLEGAL*2 Terminate Burst,Precharge ILLEGAL ILLEGAL Action
READ/WRITE ILLEGAL*2
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
FUNCTION TRUTH TABLE(continued)
Current State WRITE /RAS /CAS Address BA,CA,A10 Action NOP(Continue Burst END) NOP(Continue Burst END) Terminate Burst Terminate Burst,Latch READ/READA Begin Read,Determine AutoPrecharge*3 Terminate Burst,Latch WRITE/ Begin Write,Determine AutoWRITEA Precharge*3 Bank Active/ILLEGAL*2 PRE/PREA REFA DESEL TBST READ/READA WRITE/ WRITEA PRE/PREA REFA DESEL TBST READ/READA WRITE/ WRITEA PRE/PREA REFA Terminate Burst,Precharge ILLEGAL ILLEGAL NOP(Continue Burst END) NOP(Continue Burst END) ILLEGAL ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP(Continue Burst END) NOP(Continue Burst END) ILLEGAL ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL Command DESEL TBST
READ with AUTO PRECHARGE WRITE with AUTO PRECHARGE
BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
FUNCTION TRUTH TABLE(continued)
Current State CHARGING ACTIVATING WRITE RECOVERING /RAS /CAS BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add Address Command DESEL TBST PRE/PREA REFA DESEL TBST PRE/PREA REFA DESEL TBST PRE/PREA REFA Action NOP(Idle after tRP) NOP(Idle after tRP) ILLEGAL*2 ILLEGAL*2 NOP*4(Idle after tRP) ILLEGAL ILLEGAL NOP(Row Active after tRCD NOP(Row Active after tRCD ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
READ/WRITE ILLEGAL*2
READ/WRITE ILLEGAL*2
READ/WRITE ILLEGAL*2
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
FUNCTION TRUTH TABLE(continued)
Current State REFRESHING MODE REGISTER SETTING /RAS /CAS BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add Address Command DESEL TBST Action NOP(Idle after tRC) NOP(Idle after tRC) ILLEGAL
READ/WRITE ILLEGAL PRE/PREA REFA DESEL TBST ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(Idle after tRSC) NOP(Idle after tRSC) ILLEGAL
READ/WRITE ILLEGAL PRE/PREA REFA ILLEGAL ILLEGAL ILLEGAL ILLEGAL
ABBREVIATIONS: Hige Level, Level, Don't Care Bank Address, Address, Column Address, Operation NOTES: entries assume that High during preceding clock cycle current clock cycle. ILLEGAL bank specified state; function legal bank indicated depending state that bank. Must satisfy contention, turn around, write recovery requirements. bank precharging idle state.May precharge bank indicated ILLEGAL bank idle. ILLEGAL Device operation date-integrity guaranteed.
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
FUNCTION TRUTH TABLE
Current State SELF REFRESH*1 POWER DOWN BANKS IDLE*2 STATE other than listed above /RAS /CAS INVALID Exit Self-Refresh(Idle after tRC) Exit Self-Refresh(Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self-Refresh) INVALID Exit Power Down Idle NOP(Maintain Self-Refresh) Refer Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer Current State Power Down Refer Function Truth Table Begin Suspend Next Cycle*3 Exit Suspend Next Cycle*3 Maintain Suspend Action
ABBREVIATIONS: High Level, Level, Don't Care NOTES: High transition will re-enable other inputs asynchronously. minimum setup time must satisfied before command other than EXIT. Power-Down Self-Refresh entered only form banks idle State. Must legal command.
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
POWER SEQUENCE
Before starting normal operation, following power sequence necessary prevent SDRAM from damaged malfunctioning. Apply power start clock. Attempt maintain high, DQMB high condition inputs. Maintain stable power, stable cock, input conditions minimum 500µs. Issue precharge commands banks. (PRE PREA) After banks become idle state (after tRP), issue more auto-refresh commands. Issue mode register command initialize mode register. After these sequence, SDRAM idle state ready normal operation.
MODE REGISTER
Burst Length, Burst Type /CAS Latency programmed setting mode register(MRS). mode register stores these date until next command, which issue when both banks idle state. After tRSC from command, SDRAM ready command.
/RAS /CAS LTMODE BA0,1 A11-0 SEQUENTIAL INTERLEAVED
LATENCY MODE
/CAS LATENCY BURST SINGLE
BURST LENGTH
BURST TYPE
WRITE MODE
R:Reserved Future Full Page
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Command Address /CAS Latency
Read Write
Burst Length Burst Type
Burst Length
Initial Address Sequential
Column Addressing Interleaved
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
ABSOLUTE MAXIMUM RATINGS
Symbol Topr Tstg Parameter Supply Voltage Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Ta=25°C Condition with respect with respect with respect Ratings -0.5 -0.5 -0.5 Unit
RECOMMENDED OPERATING CONDITION
(Ta=0 70°C, unless otherwise noted) Symbol Parameter Min. Supply Voltage Supply Voltage High-Level Input Voltage inputs Low-Level Input Voltage inputs -0.3 Limits Typ. Max. Vdd+0.3 Unit
CAPACITANCE
(Ta=0 70°C, 0.3V, unless otherwise noted) Symbol CI(A) CI(C) CI(K) CI/O Parameter Input Capacitance, address Input Capacitance, control Input Capacitance, Input Capacitance, Test Condition f=1MHz Vi=25mVrms Limits(max.) Unit
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
AVERAGE SUPPLY CURRENT from
(Ta=0 ~70°C, 0.3V, unless otherwise noted)
Parameter
operating current bank active (discrete)
Symbol Icc1 Icc2P
Test Condition tRC=min.tCLK=min, BL=1, IOL=min
Limits (max) 1015 1060 1375
Unit
precharge stanby current power-down mode precharge stanby current power-down mode active stanby current power-down mode active stanby current power-down mode
bank active (discrete)
CKE=VILmax,tCLK=15ns Icc2PS CKE=CLK=VILmax(fixed) Icc2N CKE=/CS=VIHmin,tCLK=15ns(Note) Icc2NS CKE=VIHmin,CLK=VILmax(fixed) Icc3P CKE=VILmax,tCLK=15ns Icc3PS CKE=CLK=VILmax(fixed) Icc3N CKE=/CS=VIHmin,tCLK=15ns Icc3NS CKE=VIHmin,CLK=VILmax(fixed) Icc4 tCLK=min, BL=4, CL=3,IOL=0mAall banks active(discerte) tRC=min, tCLK=min Icc5 Icc6 <0.2V
burst current auto-refresh current self-refresh current
Note:Input signals changed time during 30ns.
OPERATING CONDITIONS CHARACTERISTICS
(Ta=0 70°C, 0.3V, unless otherwise noted)
Symbol VOH(DC) VOL(DC) VOH(AC VOL(AC) Parameter High-Level Output Voltage(DC) Low-Level Output Voltage(DC) Off-stare Output Current High-Level Output Voltage(AC) Input Current Low-Level Output Voltage(AC) Test Condition IOH=-2mA IOL=2mA floating CL=50pF, VO=0 IOH=-2mAIOL=2mA VIH=0 Vdd+0.3V CL=50pF, Limits Unit Min. Max.
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
TIMING REQUIREMENTS
(Ta=0 70°C, 0.3V, unless otherwise noted) Input Pulse Levels: 0.8V 2.0V Input Timing Measurement Level: 1.4V LATCH MODE Limits Symbol Parameter Min. tCLK tRCD tRAS tRRD tCCD tRSC tSRX tREF cycle time CL=3 CL=4
Max. Min.
Max.
Unit
High pulse width pilse width Transition time Input Setup time(all inputs) Input Hold time(all inputs) cycle time Column Delay Active time Precharge time Write Recovery time Deley time Delay time Mode Register Cycle time Self Refresh Exit time Refresh Interval time
100000
100000
Note:1 timing requirements assumed tT=1ns. longer than 1ns, (tT-1)ns should added parameter.
1.4V
timing referenced input signal crossing through 1.4V.
Signal
1.4V
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
BUFFER MODE Limits Symbol Parameter Min. tCLK tRCD tRAS tRRD tCCD tRSC tSRX tREF cycle time CL=2 CL=3
Max. Min.
Max.
Unit
High pulse width pilse width Transition time Input Setup time(all inputs) Input Hold time(all inputs) cycle time Column Delay Active time Precharge time Write Recovery time Deley time Delay time Mode Register Cycle time Self Refresh Exit time Refresh Interval time
100000
100000
Note:1 timing requirements assumed tT=1ns. longer than 1ns, (tT-1)ns should added parameter.
SWITCHING CHARACTERISTICS
(Ta=0 70°C, 0.3V, unless otherwise noted) LATCH MODE Limits Symbol Parameter Min. tOLZ tOHZ Access time from Output Hold time from Delay time, output impedance from Delay time, output high impedance from CL=3 CL=4 Max.
Min. Max.
Unit
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
BUFFER MODE Limits Symbol Parameter Min. tOLZ tOHZ Access time from Output Hold time from Delay time, output impedance from Delay time, output high impedance from CL=2 CL=3 Max.
Min. Max.
Unit
Output Load Condition
VTT=1.4V VOUT 50pF Output Timing Measurement Reference Point 1.4V 1.4V
1.4V
tOHZ
1.4V
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
WRITE CYCLE (single bank)
BL=4,Buffer mode(REGE="L")
tRAS
/RAS
tRCD tRCD
/CAS
A0-9
BA0,1 REGE
ACT#0
WRITE#0
PRE#0
ACT#0
WRITE#0
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
WRITE CYCLE (dual bank)
BL=4,Buffer mode(REGE="L")
tRRD tRRD
tRAS
tRCD
/RAS
tRCD
/CAS
A0-9
BA0,1
REGE
ACT#0
WRITE#0 ACT#1
PRE#0 WRITE#1
ACT#0
ACT#2 WRITE#0 PRE#1
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
WRITE CYCLE (single bank)
BL=4,Lacth mode(REGE="H")
tRAS
/RAS
tRCD tRCD
/CAS
A0-9
BA0,1 REGE
ACT#0
WRITE#0
PRE#0
ACT#0
WRITE#0
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
WRITE CYCLE (dual bank)
BL=4,Latch mode(REGE="H")
tRRD tRRD
tRAS
tRCD
/RAS
tRCD
/CAS
A0-9
BA0,1 REGE
ACT#0
WRITE#0 ACT#1
PRE#0 WRITE#1
ACT#0
ACT#2 WRITE#0 PRE#1
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
READ CYCLE (single bank)
BL=4,CL=3,Buffer mode(REGE="L")
tRAS
/RAS
tRCD tRCD
/CAS
read latency
A0-9
BA0,1 REGE
CL=3
ACT#0 READ#0
PRE#0
ACT#0
READ#0
READ allows full data
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
READ CYCLE (dual bank)
BL=4,CL=3,Buffer mode(REGE="L")
tRRD tRAS tRCD tRRD
/RAS
tRCD
/CAS
read latency
A0-9 BA0,1
REGE
CL=3 CL=3
ACT#0 READ#0 ACT#1
PRE#0 READ#1
ACT#0 PRE#1
READ#0 ACT#2
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
READ CYCLE (single bank)
BL=4, CL=3,Latch mode(REGE="H")
tRAS
/RAS
tRCD tRCD
/CAS
read latency
A0-9
BA0,1 REGE
CL=3
ACT#0 READ#0
PRE#0
ACT#0
READ#0
READ allows full data
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
READ CYCLE (dual bank)
BL=4,CL=3,Latch mode(REGE="H")
tRRD tRAS tRCD tRRD
/RAS
tRCD
/CAS
read latency
A0-9 BA0,1
REGE
CL=3 CL=3
ACT#0 READ#0 ACT#1
PRE#0 READ#1
ACT#0 PRE#1
READ#0 ACT#2
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Burst WRITE (multi bank) with AUTO-PRECHARGE BL=4,Buffer mode(REGE="L")
tRRD tRRD
/RAS
tRCD tRCD BL-1+ BL-1+ tRCD
/CAS A0-9
BA0,1
REGE
ACT#0 ACT#1
WRITE#0 with AutoPrecharge
ACT#0 WRITE#1 with AutoPrecharge
WRITE#0 ACT#1
WRITE#1
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Burst WRITE (multi bank) with AUTO-PRECHARGE BL=4,Latch mode(REGE="H")
tRRD tRRD
/RAS
tRCD tRCD BL-1+ BL-1+ tRCD
/CAS A0-9
BA0,1
REGE
ACT#0 ACT#1
WRITE#0 with AutoPrecharge
ACT#0 WRITE#1 with AutoPrecharge
WRITE#0 ACT#1
WRITE#1
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Burst READ (multi bank) with AUTO-PRECHARGE
BL=4,Buffer mode(REGE="L")
tRRD tRRD
/RAS
tRCD tRCD BL+tRP BL+tRP tRCD
/CAS
read latency
A0-9
BA0,1 REGE
CL=3
CL=3
CL=3
ACT#0 ACT#1
READ#0 with Auto-Precharge
ACT#0 READ#1 with Auto-Precharge
READ#0 ACT#1
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Burst READ (multi bank) with AUTO-PRECHARGE
BL=4,Latch mode(REGE="H")
tRRD tRRD
/RAS
tRCD tRCD BL+tRP BL+tRP tRCD
/CAS
read latency
A0-9
BA0,1 REGE
CL=3
CL=3
CL=3
ACT#0 ACT#1
READ#0 with Auto-Precharge
ACT#0 READ#1 with Auto-Precharge
READ#0 ACT#1
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Page Mode Burst Write (multi bank)
BL=4,Buffer mode(REGE="L")
tRRD
/RAS
tRCD
/CAS A0-9
BA0,1 REGE
ACT#0
WRITE#0 ACT#1
WRITE#0 WRITE#1
WRITE#0
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Page Mode Burst Write (multi bank)
BL=4,Latch mode(REGE="H")
tRRD
/RAS
tRCD
/CAS A0-9
BA0,1 REGE
ACT#0
WRITE#0 ACT#1
WRITE#0 WRITE#1
WRITE#0
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Page Mode Burst Read (multi bank)
BL=4,Buffer mode(REGE="L")
tRRD
/RAS
tRCD
/CAS
read latency=2
A0-9
BA0,1 REGE
CL=3
CL=3
CL=3
ACT#0 READ#0 ACT#1
READ#0 READ#1
READ#0
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Page Mode Burst Read (multi bank)
BL=4,Latch mode(REGE="H")
tRRD
/RAS
tRCD
/CAS
read latency=3
A0-9
BA0,1 REGE
CL=3
CL=3
CL=3
ACT#0 READ#0 ACT#1
READ#0 READ#1
READ#0
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Write Interrupted Write Read
BL=4,Buffer mode(REGE="L")
tRRD
/RAS
tRCD tCCD
/CAS A0-9
BA0,1 REGE
CL=3
ACT#0 WRITE#0 WRITE#0 WRITE#0 READ#0 ACT#1 WRITE#1 Burst Write interrupted Write Read active bank. Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Write Interrupted Write Read
BL=4,Latch mode(REGE="H")
tRRD
/RAS
tRCD tCCD
/CAS A0-9
BA0,1 REGE
CL=3
ACT#0 WRITE#0 WRITE#0 WRITE#0 READ#0 ACT#1 WRITE#1 Burst Write interrupted Write Read active bank. Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Read Interrupted Read Write
BL=4,Buffer mode(REGE="L")
tRRD
/RAS
tRCD
/CAS
read latency=2
A0-9
BA0,1 REGE
ACT#0
READ#0 READ#0 READ#0 READ#0 WRITE#0 ACT#1 READ#1 blank prevent contention
Burst Read interrupted Read Write active bank. Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Read Interrupted Read Write
BL=4,Latch mode(REGE="H")
tRRD
/RAS
tRCD
/CAS
read latency=3
A0-9
BA0,1 REGE
ACT#0
READ#0 READ#0 READ#0 READ#0 WRITE#0 ACT#1 READ#1 blank prevent contention
Burst Read interrupted Read Write active bank. Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Write Interrupted Precharge
BL=4,Buffer mode(REGE="L")
tRRD
/RAS
tRCD
/CAS A0-9
BA0,1 REGE
ACT#0 WRITE#0 ACT#1
PRE#0 WRITE#1 PRE#1
ACT#1
WRITE#1
Burst Write interrupted Precharge other bank.
Burst Write interrupted Precharge same bank. Italic parameter indicates minimum case
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Write Interrupted Precharge
BL=4,Latch mode(REGE="H")
tRRD
/RAS
tRCD
/CAS A0-9
BA0,1 REGE
ACT#0 WRITE#0 ACT#1
PRE#0 WRITE#1 PRE#1
ACT#1
WRITE#1
Burst Write interrupted Precharge other bank.
Burst Write interrupted Precharge same bank. Italic parameter indicates minimum case
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Read Interrupted Precharge
BL=4,Buffer mode(REGE="L")
tRRD
/RAS
tRCD tRCD
/CAS
read latency=2
A0-9
BA0,1 REGE
ACT#0
READ#0 ACT#1
PRE#0 READ#1 PRE#1
ACT#1
READ#1
Burst Read interrupted Precharge other bank.
Burst Read interrupted Precharge same bank. Italic parameter indicates minimum case
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Read Interrupted Precharge
BL=4,Latch mode(REGE="H")
tRRD
/RAS
tRCD tRCD
/CAS
read latency=3
A0-9
BA0,1 REGE
ACT#0
READ#0 ACT#1
PRE#0 READ#1 PRE#1
ACT#1
READ#1
Burst Read interrupted Precharge other bank.
Burst Read interrupted Precharge same bank. Italic parameter indicates minimum case
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Mode Register Setting
tRSC
/RAS
tRCD
/CAS A0-9
BA0,1 REGE
Auto-Ref (last cycles)
Mode Register Setting
ACT#0
WRITE#0
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Auto-Refresh @BL=4
/RAS
tRCD
/CAS A0-9
BA0,1 REGE
Auto-Refresh Before Auto-Refresh, banks must idle state.
ACT#0
WRITE#0
After from Auto-Refresh, banks idle state. Italic parameter indicates minimum case
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Self-Refresh
stopped
/RAS /CAS
tSRX
must maintain Self-Refresh
A0-9 BA0,1 REGE
Self-Refresh Entry Before Self-Refresh Entry, banks must idle state.
Self-Refresh Exit After from Self-Refresh Exit, banks idle state.
ACT#0
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Write Mask @BL=4
BL=4,Buffer mode(REGE="L")
/RAS
tRCD
/CAS A0-9
BA0,1 REGE
masked
masked
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Write Mask @BL=4
BL=4,Latch mode(REGE="H")
/RAS
tRCD
/CAS A0-9
BA0,1 REGE
masked
masked
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Read Mask @BL=4 CL=3
BL=4,Buffer mode(REGE="L")
/RAS
tRCD
/CAS
read latency=2
A0-9
BA0,1 REGE
masked
masked
ACT#0
READ#0
READ#0
READ#0
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Read Mask @BL=4 CL=3
BL=4,Latch mode(REGE="H")
/RAS
tRCD
/CAS
read latency=3
A0-9
BA0,1 REGE
masked
masked
ACT#0
READ#0
READ#0
READ#0
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Power Down
/RAS /CAS
Standby Power Down
latency=1
Active Power Down
A0-9
BA0,1 REGE
Precharge
ACT#0
Italic parameter indicates minimum case MIT-DS-0228-0.2 29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Suspend @BL=4 CL=3
BL=4,Buffer mode(REGE="L")
/RAS
tRCD
/CAS
latency=1 latency=1
A0-9
BA0,1 REGE
ACT#0
WRITE#0 READ#0 suspended
suspended Italic parameter indicates minimum case 29/Oct. /1998
MIT-DS-0228-0.2
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Suspend @BL=4 CL=3
BL=4,Latch mode(REGE="H")
/RAS
tRCD
/CAS
latency=2 latency=2
A0-9
BA0,1 REGE
ACT#0
WRITE#0 READ#0 suspended
suspended Italic parameter indicates minimum case 29/Oct. /1998
MIT-DS-0228-0.2
MITSUBISHI ELECTRIC
Byte
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Serial Presence Detect Table
Function described Defines bytes written into serial memory module mfgr Total bytes memory device Fundamental memory type Addresses this assembly Column Addresses this assembly Module Banks this assembly Data Width this assembly. Data Width continuation Voltage interface standard this assembly
SDRAM Cycletime Max. Supported Latency (CL).
enrty data Bytes SDRAM A0-A11 A0-A8 1BANK LVTTL 10ns
DATA(hex)
Cycle time CL=3 SDRAM Access from Clock CL=3 DIMM Configuration type (Non-parity,Parity,ECC) Refresh Rate/Type SDRAM width,Primary DRAM Error Checking SDRAM data width
Minimum Clock Delay,Back Back Random Column Addresses
self refresh(15.625uS) 1/2/4/8/Full page 4bank
buffered,registered
Precharge All,Auto precharge Write1/Read Burst
Burst Lengths Supported Banks Each SDRAM device CAS# Latency Latency Write Latency SDRAM Module Attributes SDRAM Device Attributes:General SDRAM Cycle time(2nd highest latency) Cycle time CL=2
10ns 13ns 20ns 20ns 20ns 50ns
SDRAM Access form Clock(2nd highest latency)
CL=2 SDRAM Cycle time(3rd highest latency)
SDRAM Access form Clock(3rd highest latency)
Precharge Active Minimum Active Active Min. Delay Active Precharge
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Serial Presence Detect Table
Density each bank module Command Address signal input setup time Command Address signal input hold time 64MByte option 1.2A Check Check 64-71 Manufactures Jedec code JEP-108E Manufacturing location MITSUBISHI Miyoshi,Japan Tajima,Japan NC,USA Germany 73-90 Manufactures Part Number MH8S72BBFD-7 MH8S72BBFD-8 91-92 93-94 95-98 99-125 128+ Revision Code Manufacturing date Assembly Serial Number Manufacture Specific Data Intetl specification frequency Intel specification CAS# Latency support Unused storage locations
1CFFFFFFFFFFFFFF
36-61
Data signal input setup time Data signal input hold time Superset Information (may used future) Revision Checksum bytes 0-62
revision year/week code serial number option 100MHz CL=2/3,AP,CK0 CL=3,AP,CK0 open
rrrr yyww ssssssss
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
133.35
11.43
6.35 36.83 24.495 42.18
6.35 54.61 127.35
1.27
38.1 3.9Max
29/Oct. /1998
8.89
4.05Min
MIT-DS-0228-0.2
MITSUBISHI ELECTRIC
4.18Min
1.27
17.78
MH8S72BBFD-7,
603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous DYNAMIC
Keep safety first your circuit designs!
Mitsubishi Electric Corporation puts maximum effort into making semiconductor products better more reliable,but there always possibility that trouble occur with them. Trouble with semiconductors consideration safety when making your circuit designs,with appropriate measures such placement substitutive,auxiliary circuits,(ii) non-flammable material (iii) prevention against malfunction mishap.
Notes regarding these materials
1.These materials intended reference assist customers selection Mitsubishi semiconductor product best suited customer's application;they convey license under intellectual property rights,or other rights,belonging Mitsubishi Electric Corporation third party. 2.Mitsubishi Electric Corporation assumes responsibility damage, infringement third-party's rights,originating product data,diagrams,charts circuit application examples contained these materials. 3.All information contained these materials,including product data, diagrams charts,represent information products time publication these materials,and subject change Mitsubishi Electric Corporation without notice product improvements other reasons. therefore recommended that customers contact Mitsubishi Electric Corporation authorized Mitsubishi Semiconductor product distributor latest product information before purchasing product listed herein. 4.Mitsubishi Electric Corporation semiconductors designed manufactured device system that used under circumstances which human life potentially stake. Please contact Mitsubishi Electric Corporation authorized Mitsubishi Semiconductor product distributor when considering product contained herein special applications,such apparatus systems transportation, undersea repeater use. 5.The prior written approval Mitsubishi Electric Corporation necessary reprint reproduce whole part these materials. 6.If these products technologies subject Japanese export control restrictions,they must exported under license from Japanese government cannot imported into country other than approved destination. diversion reexport contrary export control laws regulations Japan and/or country destination prohibited. 7.Please contact Mitsubishi Electric Corporation authorized Mitsubishi Semiconductor product distributor further details these materials products contained therein.
MIT-DS-0228-0.2
29/Oct. /1998
MITSUBISHI ELECTRIC

MH8S72BBFD-7, 603,979,776-BIT 8,388,608-WORD 72-BIT Synchronous D

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