Melito, Portuese ABSTRACT increasing complexity Power MOSFET tech

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Melito, Portuese ABSTRACT increasing complexity Power MOSFET tech

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APPROACH PARAMETER EXTRACTION SPICE POWER MOSFET MODEL
Melito, Portuese
ABSTRACT increasing complexity Power MOSFET technology inclusion, same chip, more more intelligence together with power switch, requires accurate simulation characteristics power device obtain good correlation between simulation results experimental data. robust design take worst cases into consideration well typical conditions. Also simulation make provision spread device characteristics manufacturing tolerances. This paper describes approach parameter extraction sub-circuit model Power MOSFETs used SPICE circuit simulator which uses powerful analytical simulator developed SGSTHOMSON Microelectronics. This simulator, whose models have been built considering physical structure layout parameters, allows optimisation most important device characteristics also takes into account possible parameter spread process. this reason program output give only average values required parameters also their statistical distribution. INTRODUCTION modelling power MOSFETs, spite contributions from numerous authors, still exhibits some points improved. From user point view choice model topology determined degree accuracy results require, computation time, convergence problems robustness simplicity parameter extraction method. weak points actual models drain-gate capacitance modelling which complicates switching behaviour because high degree non-linearity. leaving apart this drawback which mitigated cost time), usefulness model accuracy often increasing model complexity, (and thus computation
AN473/0692
been limited lack robustness parameter extraction method employed. this paper give contribution solving this weak point. parameter extraction usually performed elaboration experimental measurements, some parameters directly measurable others related physics device simply parameters model device close possible reality. This paper shows different tackle problem which employs powerful package, COSMOS, entirely developed inhouse SGS-THOMSON Microelectronics. number analytical models have been developed allow extraction parameters tied elements sub-circuit very fast rugged. same this package allows extraction worst case parameters because also takes into account manufacturing tolerances. SGS-THOMSON SPICE MODEL POWER MOSFET Figure illustrates components sub- circuit model. Spice MOSFET model main switching element circuit. other elements take into account stray inductances wires (Ls, Lg), poly-silicon gate resistance (Rg), resistance both silicon bonding (Rs, Rd), body-drain capacitance modulation (DBD) leakage current when device breakdown. points need more detailed explanation: additional voltage dependent series drain resistance (Rj, used order model extra resistance epitaxial layer substrate depletion modulation body-drain junction drain-source voltage accounted ideal MOSFET model; high non-linearity gate-drain capacitance typical structure switching from being strongly inverted accumulation state. only difference
Figure Sub-circuit SPICE model Power MOSFET Figure Crss modelling
COSMOS: ANALYTICAL SIMULATOR POWER MOSFET COSMOS born tool optimise Power MOSFET design. becoming more more difficult this because increasing demands users improve performance large number variables involved which interact with each other. This software package provides some tools match most important device characteristics (Ron, BVDSS, Capacitances, Gate-charge etc.) with demands made netlist model parameters (average value worst case) SPICE sub-circuit. Program structure schematic shown figure statistical data manufacturing processes device design (figure collected data base processed analytical models COSMOS which performs various analyses. 3.1.1 Sensitivity Analysis This option allows evaluation influence single layout process parameter desired characteristic device (e.g. Ron, BVDSS, Ciss. Coss, Crss, gate-charge, etc.). 3.1.2 Statistical Analysis statistical input data allows COSMOS output only average value required response also statistical distribution. average value also given divided into various components make optimisation device easier. Figure shows example referred figure intrinsic capacitances.
fact that modulation depletion zone caused only voltage also lateral injection charge coming from channel. This behaviour been modelled making drain-gate gate-source capacitances ideal MOSFET negligible setting zero length overlapping regions between gate other elements. These capacitances have been replaced constant gate-source capacitance, CGS, twoelement gate-drain capacitance, CGD. Figure shows experimental diagram simulation obtained model described above. When drain-gate voltage positive, i.e. V(a) V(b) then containing diode activated modelled diode depletion capacitance. insertion capacitance, parallel with this diode gives only better fitting high values drain- source voltages also improves simulation values VDS. When drain-gate voltage negative capacitance modelled disabling this activating other one.
Figure COSMOS structure
Figure COSMOS outputs, example: Average values Descriptive statistics
Response
Sensitivity analysis (single parameter)
Screening Independent Response variables project (xi, Analytical Solver Statistical Analysis Contour plots Surfaces worst case Distributions
Model param. SPICE Parameter Extraction sub-circuit
Figure Layout process parameters
Parameter Cell dimension Cell spacing Gate-drain area related gate oxide Gate-drain area related field oxide Gate-p+ area related gate oxide Gate-p+ area related field oxide Gate-Source metal area Deep Body area Channel width measured poly mask Parameter Gate oxide thickness Field oxide thickness P-Vapox Thickness Oxide charge Qss) Channel length Channel doping (peak) layer doping layer width deep body deep body
Figure COSMOS output capacitances
3.1.3 Screening Response Surfaces. possible screen between most important variables influencing requested response (figure obtain response surfaces related simultaneous variation more input factors (figure 3.1.4 Spice Parameters Extraction This option, which discussed more detail later, allows extraction values elements SPICE sub-circuit model. Models COSMOS models derived from classical ones [1][2][3], they have been improved taking into account some effects that disregarded most recent technology. 3.2.1 lateral depletion body, built-in voltage VDS, which leads reduction region available current flow, must considered only high voltage devices also voltage ones. increased packing density makes this depletion significant with respect dimensions bodies thus resulting magnification JFET effect. Moreover, extremely values Area High Density devices requires that model considers only silicon contribution also those metallization. Other effects such mobility variation caused Figure COSMOS output screening example surface scattering electric fields [4][5] influence doping non-uniformity channel also considered. 3.2.2 BVDSS power MOSFET both breakdown voltage optimisation directly related. They depend doping (Nd) epitaxial layer thickness (Wd) which optimisation opposite ways. problem finding pair, that minimise fixed BVDSS. latter computed taking into account body doping profile, eventual reach-through condition efficiency edge termination employed. graphics tools program make this search optimum conditions easier: fact obtain maps (vs. level lines BV-Ron coordinate system. 3.2.3 Capacitance models intrinsic capacitances Power MOSFET have been developed taking into account only doping non-uniformity also influence charge associated with body lateral depletion. COSMOS SPICE PREPROCESSOR modern design electronic devices means that mark must with first shot minimise costs terms time money. This achieved only having powerful simulators that make sure that manufacturing first device very close target. COSMOS, figure Figure COSMOS output response surface example
placed between process simulator (e.g. SUPREM, SUPRA) circuit simulator (e.g. SPICE) allowing device optimisation match characteristics requested specific application. Generation statistical distribution parameters worst case extraction. Starting from distribution experimental data process variables from design tolerances, inherent speed analytical method allows production random statistically relevant input variables, using Box-Muller transformation [6]. This turn, used generate distribution desired output responses. This possible also parameters sub-circuit model SPICE. MODEL cards related typical values worst cases generated taking into account mean boundary values distributions above discussed. typical output file shown appendix CONCLUSION implementation analytical models validated numerical simulator powerful tool studying device performance optimisation. COSMOS allows very fast computation Figure Total approach Power MOSFET design influence more parameters final characteristics device. Moreover gives average worst case models SPICE allowing device designer have fast feedback thus reducing time needed designing. REFERENCES Modelling On-Resistance LDMOS, VDMOS, VMOS Power Transistors, S.C. J.D. Plummer, IEEE Transactions Electronic Devices, Vol. February 1980. Threshold Punch-through Behaviour Laterally Non-uniformally Doped Short-Channel MOSFETs, C.T. Wang D.H. Navon, IEEE Transactions Electronic Devices, Vol. July 1983. Simple Theory Predict Threshold Voltage Short-Channel lGFET's, L.D. Yau, IEEE Transactions Electronic Devices, Solid State Electronics, 17,1974. Physically Based Mobility Model Numerical Simulation Non-Planar Devices, Lombardi, Manzini, Saporito, Vanzi, IEEE Transactions Computer-Aided Design, Vol. November 1988. HFlELDS: Highly Flexible Semiconductor Device Analysis Program, Baccarani al., Nasecode June 1985. Numerical Recipes, W.K. Press, B.P. Flannery, S.A. Tenkolsky, W.T. Vetterling, Cambridge University Press,
0.0000E+00 KAPPA 0.180 491.335 THETA 0.020 .MODEL 0.0000E+00 0.3980E-09 1.060 0.630 .MODEL 0.0000E+00 0.5l00E-09 0.670 0.380 .MODEL 0.1950E-ll 72.10 1.10 0.1250E-07 0.2275E-01 .MODEL 0.2000E-11 0.0000E+00 Models
APPENDIX TYPICAL SPICE OUTPUT FILE Sub-circuit IRFZ20 .SUBCKT PWRMOS 0.7500E-08 0.7500E-08 0.4500E-08 0.1000E+02 0.4000E-02 0.5017E-01 0.2071E-01 0.1430E-09 0.5023E-09 0.0000E+00 0.1800E-05 W=0.4593 POLY(2) 0.03 1.0E-06 D1100 1.0E+06 1.0E+06 .ENDS PWRMOS Models IRFZ20 MODEL NMOS LEVEL 0.8500E-07 3.134 0.821 NSUB 0.1150E+18 0.0000E+00
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Melito, Portuese ABSTRACT increasing complexity Power MOSFET tech

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