M10B416256A FAST PAGE MODE FEATURES organization FAST PAGE a

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M10B416256A FAST PAGE MODE FEATURES organization FAST PAGE a

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EliteMT
M10B416256A FAST PAGE MODE
FEATURES
organization FAST PAGE access mode Byte/Word Read/Write operation Single 10%) power supply TTL-compatible inputs outputs 512-cycle refresh Refresh modes only, BEFORE (CBR) HIDDEN JEDEC standard pinout Parameter tRAC tCAC
ORDERING INFORMATION PACKAGE
40-pin 400mil 40-pin 400mil TSOP (TypeII)
PRODUCT M10B416256A-50J/60J M10B416256A-50T/60T
PACKING TYPE TSOPII
GENERAL DESCRIPTION
M10B416256A randomly accessed solid state memory, organized 262,144 bits device. offers FAST Page Mode, 10%) single power supply. Access time (-50, -60) package type (SOJ, TSOP optional features this family. these family have before -only refresh Hidden refresh capabilities. access modes supported this device Byte access Word access. only leave other staying high will result BYTE access. WORD access happens when CASL CASH used. CASL transiting during READ WRITE cycle will output input data into lower byte (IO0~IO7), CASH transiting will output input data into upper byte (IO8~15).
ASSIGNMENT
View
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
TSOP (TypeII) View
I/O1 I/O1 I/O1 I/O1 I/O1 I/O1 I/O9 I/O8
Elite Memory Technology
Publication Date Dec. 2000 Revision 1/15
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FUNCTIONAL BLOCK DIAGRAM
M10B416256A
CASL CASH CONTROL LOGIC
DATA-IN BUFFER IO15
CLOCK GENERATOR
DATA-OUT BUFFER COLUMN DECODER
COLUMN ADDRESS BUFFER
REFRESH CONTROLER
SENSE AMPLIFIERS GATING
ROW. ADDRESS BUFFERS(9) DECODER MEMORY ARRAY REFRESH COUNTER
GENERATOR
DESCRIPTIONS
16~19,22~26 2~5,7~10,31~34,36~39 1,6,20 21,35,40 11,12,15,30 NAME A0~A8
CASH CASL
TYPE Input Input Input Input Input Input Input Output Supply Ground
DESCRIPTION Address Input Address A0~A8 Column Address A0~A8 Address Strobe Column Address Strobe Upper Byte Control Column Address Strobe Lower Byte Control Write Enable Output Enable Data Input Output Power, Ground Connect
I/O0 I/O15
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Publication Date Dec. 2000 Revision 2/15
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ABSOLUTE MAXIMUM RATINGS
Voltage Relative Operating Temperature, (ambient) Storage Temperature (plastic) .-55 +150 Power Dissipation 0.8W Short Circuit Output Current 50mA
M10B416256A
Permanent device damage occur "Absolute Maximum Ratings" exceeded. This stress rating only, functional operation device above those conditions indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS unless otherwise noted)
PARAMETER Supply Voltage Supply Voltage Input High Voltage Input Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Voltage Note 1.All Voltages referenced VOUT Output(s) disable CONDITIONS SYMBOL -1.0 UNITS NOTES
PARAMETER Operating Current Standby Current
CONDITIONS
cycling =min
SYMBOL ICC1 ICC2
UNITS NOTES
interface DOUT =High-Z CMOS interface, VCC-0.2V
only refresh Current
=VIH,
ICC3 ICC4 ICC5 ICC6
FAST Page Mode Current Standby Current
Before Refresh Current
Note specified output open condition. Address changed twice less while =VIL Address changed once less while =VIH
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Publication Date Dec. 2000 Revision 3/15
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CAPACITANCE 10%)
PARAMETER Input Capacitance (address) Input Capacitance CASH CASL Output capacitance (I/O0~I/O15) SYMBOL
M10B416256A
UNIT
ELECTRICAL CHARACTERISTICS 10%, (note
Test Conditions Input timing reference levels Output reference level VOL= 0.8V, VOH=2.0V Output Load 2TTL gate (50pF) Assumed PARAMETER Read Write Cycle Time Read Write Cycle Time Fast-Page-Mode Read Write Cycle Time Fast-Page-Mode Read-Write Cycle Time Access Time From Access Time From Access Time From Access Time From Column Address Access Time From Precharge
Pulse Width Pulse Width (Fast Page Mode) Hold Time Precharge Time Pulse Width Hold Time Precharge Time Delay Time Precharge Time
SYMBOL tRWC tPCM tRAC tCAC tOAC tACP tRAS tRASC tRSH tCAS tCSH tRCD tCRP tASR tRAH tRAD tASC tCAH tRAL
100K
100K
UNIT
Notes
5,20 13,20
7,18
Address Setup Time Address Hold Time
Column Address Delay Time
Column Address Setup Time Column Address Hold Time Column Address Hold Time (Reference Column Address Lead Time
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Publication Date Dec. 2000 Revision 4/15
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(Continued)
PARAMETER Read Command Setup Time Read Command Hold Time Reference Read Command Hold Time Reference
Output Low-Z
M10B416256A
SYMBOL tRCS tRCH tRRH tCLZ tOFF1 tOFF2 tWCS tWCH tWCR tRWL tCWL tDHR tRWD tAWD tCWD tREF tRPC tCSR tCHR tOEH tORD tCLCH tRSR tRHR
UNIT
Notes
15,18 9,15,19 10,17,20 17,25 11,15,18 15,24 15,19 12,20 12,20
Output Buffer Turn-off Delay From
Output Buffer Turn-off Write Command Setup Time Write Command Hold Time Write Command Hold Time(Reference Write Command Pulse Width Write Command Lead Time Write Command Lead Time Data-in Setup Time Data-in Hold Time Data-in Hold Time (Reference
Delay Time
11,18
Column Address Delay Time
Delay Time
Transition Time (rise fall) Refresh Period (512 cycles)
Precharge Time Setup Time(CBR REFRESH) Hold Time(CBR REFRESH) Hold Time From During Read-ModeWrite Cycle Setup Prior During Hidden Refresh Cycle
1,18 1,19
Last Going First Returning High Read Setup Time Reference Read Hold Time Reference
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Publication Date Dec. 2000 Revision 5/15
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Notes Enables on-chip refresh address counters. VIH(min) VIL(max) reference levels measuring timing input signals. Transition times measured between VIL. addition meet transition rate specification, input signals must transit between monotonic manner. Assume that tRCD tRCD(max). tRCD greater than maximum recommended value shown this table, tRAC will increase amount that tRCD exceeds value shown. Assume that tRCD tRCD (max) falling edge data-out will maintained from previous cycle. initiate cycle clear data-out buffer,
must pulsed high.
M10B416256A
back indeterminate. held high taken after goes result LATE WRITE -controlled) cycle. Those parameters referenced leading edge EARLY WRITE cycles leading edge LATE WRITE READ-MODIFY- WRITE cycles. During READ cycle, then taken HIGH before goes high, goes open, tied permanently low, LATE WRITE READ-MODIFYWRITE operation possible. initial pause 100ms required after power-up followed eight refresh cycles only CBR) before proper device operation assured. eight cycle wake-ups should repeated time tREF refresh requirement exceeded. WRITE command defined going low. LATE WRITE READ-MODIFY-WRITE cycles must have both tOFF2 tOEH high during WRITE cycle) order ensure that output buffers will open during WRITE cycles. I/Os open during READ cycles once tOFF1 tOFF2 occur. Referenced earlier falling edge.
Operation within tRCD limit ensures that tRCD (max) met, tRCD (max) specified reference point only tRCD greater than specified tRCD (max) limit, access time controlled tCAC. Operation within tRAD limit ensures that tRAD(max) met. tRAD(max) specified reference point only tRAD greater than specified tRAD (max) limit, access time controlled tAA. Either tRCH tRRH must satisfied READ cycle. tOFF1(max) defines time which output achieves open circuit condition reference VOL. tWCS, tRWD, tAWD tCWD restrictive operating parameters LATE WRITE READ-MODIFYWRITE cycle only. tWCS tWCS(min) cycle EARLY WRITE cycle data output will remain open circuit throughout entire cycle. tRWD tRWD(min) tAWD tAWD(min) tCWD tCWD(min) cycle READ-WRITE data output will contain data read from selected cell. neither above conditions met, state access time until
Referenced latter rising edge. Output parameter (I/O) referenced corresponding input, IO0~7 CASL IO8~15 CASH Last falling edge first rising edge. Last rising edge next cycle' last rising edge. Last rising edge first falling edge. Referenced latter falling edge. controlled regardless CASL CASH
Elite Memory Technology
Publication Date Dec. 2000 Revision 6/15
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TRUTH TABLE
ADDRESSES
CASL CASH
M10B416256A
FUNCTION Standby Read Word Read Lower Byte Read Upper Byte Write Word (Early Write) Write Lower Byte (Early)
High-Z Data-Out
NOTES
Lower Byte, Data-Out Upper Byte, Data-Out Data-In Lower Byte, Data-In Upper Byte, High-Z Lower Byte, High-Z Upper Byte, Data-In Data-Out, Data-In Data-Out Data-Out Data-In Data-In Data-Out, Data-In Data-Out, Data-In Data-Out High-Z
Write Upper Byte (Early) Read-Write Fast-Page-Mode Cycle Read Cycle Fast-Page-Mode Cycle Write Cycle Fast-Page-Mode Cycle Read-Write Cycle Hidden Refresh
-Only Refresh
Refresh
High-Z
*Note These WRITE cycles also BYTE WRITE cycles (either CASL CASH active). These READ cycles also BYTE READ cycles (either CASL CASH active). Only must active CASL CASH
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Publication Date Dec. 2000 Revision 7/15
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READ CYCLE
tRAS
M10B416256A
tRRH
tRAD tASR
tRAH
tRAL tCAH
COLUMN
tRCH
tRAC tCAC tCLZ
OPEN
tOFF1
VALID DATA
EARLY WRITE CYCLE
tRAS
tCRP
CASL,CASH
tASR tRAD tRAH
tRAL tCAH
tWCH
tWCS
DON'T CARE UNDEFINED
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Publication Date Dec. 2000 Revision 8/15
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READ WRITE CYCLE (LATE WRITE READ-MODIFY-WRITE CYCLES)
tRWC
M10B416256A
tCSH tRSH tCRP
CASL
tRCD
ADDR
tRCS
tCWD tAWD
tCWL
tCLZ
VALID
tOAC
tOFF2
tOEH
FAST-PAGE-MODE READ CYCLE
tRASC
tCSH
CASL,CASH
tRCD ,tCLC
tRSH
tASR tRAH
ADDR
COLUMN
tRCS tRCS
tRCS tRCH tRCH
tRCH
OPEN
VALID DATA
tCLZ
tACP
tCLZ
DATA VALID DATA
tOAC
tOFF2
tOFF2
DON'T CARE
UNDEFINED
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Publication Date Dec. 2000 Revision 9/15
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FAST-PAGE-MODE EARLY-WRITE CYCLE
M10B416256A
tCSH
CASL
tRCD
tRSH tCAS, tCLCH
tASR
tASC tASC tASC
LUMN
COLUMN
COLUMN
tWCS
tWCH
tWCR tDHR
tRWL
VALID DATA
VALID DATA
FAST-PAGE-MODE READ-WRITE CYCLE (LATE WRITE READ-MODIFY-WRITE CYCLES)
tCSH tCRP
tRCD
tPCM
tRSH
ADDR
tASC
COLUMN
tRCS tCWL tCWD
tAWD tCWD tAWD
tCLZ
VI/OH VI/OL
DOUT
tCLZ
tCLZ
tOFF2
tOFF2
tOEH
DON'T CARE
UNDEFINED
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Publication Date Dec. 2000 Revision 10/15
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ONLY REFRESH CYCLE (ADDR A0~A8 DON' CARE)
tRAS
M10B416256A
tCRP
,CAS
tASR
ADDR
REFRESH CYCLE (A0~A8 DON' CARE)
tRPC
tCSR
tRPC
tCSR
OPEN
tRSR
UNDE
Note tRSR tRHR system design reference only. signal actually "don' care" time during REFRESH. However, should held HIGH time during REFRESH ensure compatibility with other DRAMs which require HIGH time during REFRESH.
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Publication Date Dec. 2000 Revision 11/15
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HIDDEN REFRESH CYCLE HIGH LOW)
(READ)
M10B416256A
tRAS
tRSH
tCHR
tRAD tASR
COLUMN
tCLZ
OPEN
tOFF1
tORD
tOFF2
DON'T CARE
UNDEFINE
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Publication Date Dec. 2000 Revision 12/15
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PACKING 40-LEAD SECTIONI
M10B416256A
DIMENSIONS SOJ(400mil)
0.050"
DETAIL
DETAIL 0.024"
SECTIONII
Symbol
Dimension Norm 3.250 3.510 3.760 2.080 2.790 0.380 0.460 0.560 0.635 0.180 0.250 0.360 1.270 25.91 26.040 26.290
Dimension inch Symbol Dimension Norm Norm 0.128 0.138 0.148 10.920 11.176 11.430 0.082 10.030 10.160 10.290 0.110 9.40 0.015 0.018 0.022 0.760 0.890 1.020 0.025 0.635 0.007 0.010 0.014 0.050 1.02 1.025 1.035 1.270 0.381
Dimension inch Norm 0.430 0.440 0.450 0.395 0.400 0.405 0.370 0.030 0.035 0.040 0.025
0.050 0.015
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Publication Date Dec. 2000 Revision 13/15
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PACKING 44-LEAD DIMENSIONS TSOP(II) DRAM(400mil)
M10B416256A
Symbol
Dimension 0.05 0.95 0.30 0.30 0.12 0.10 18.28 11.56 10.03 0.40 18.41 0.805 11.76 10.16 0.59 0.80 0.80 11.96 10.29 0.69 0.35 1.00 Norm 1.20 0.15 1.05 0.45 0.40 0.21 0.16 18.54
Dimension inch 0.002 0.037 0.012 0.012 0.005 0.004 0.720 0.455 0.395 0.016 0.725 0.0317 0.463 0.400 0.023 0.031 0.0315 0.471 0.027 0.014 0.039 Norm 0.047 0.006 0.042 0.018 0.016 0.008 0.006 0.730
Elite Memory Technology
Publication Date Dec. 2000 Revision 14/15
EliteMT
Important Notice rights reserved.
M10B416256A
part this document reproduced duplicated form means without prior permission EliteMT. contents contained this document believed accurate time publication. EliteMT assumes responsibility error this document, reserves right change products specification this document without notice. information contained herein presented only guide examples application products. responsibility assumed EliteMT infringement patents, copyrights, other intellectual property rights third parties which result from use. license, either express implied otherwise, granted under patents, copyrights other intellectual property rights EliteMT others. semiconductor devices have inherently certain rate failure. minimize risks associated with customer's application, adequate design operating safeguards against injury, damage, loss from such failure, should provided customer when making application designs. EliteMT's products authorized critical applications such limited life support devices system, where failure abnormal operation directly affect human lives cause physical injury property damage. products described here used such kinds application, purchaser must quality assurance testing appropriate such applications.
Elite Memory Technology
Publication Date Dec. 2000 Revision 15/15

M10B416256A FAST PAGE MODE FEATURES organization FAST PAGE a

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