QUALITY SEMICONDUCTOR, INC. 3.3V SYNC DRAM Clock Driver QS59
|
|
|
Top Searches for this datasheet
QS5920A
QUALITY SEMICONDUCTOR, INC.
3.3V SYNC DRAM Clock Driver
QS5920A
DESCRIPTION
QS5920A high-performance, skew, jitter, multiple output phase-locked loop clock driver which suitable PC-100 spread spectrum clock systems. provides precise phase frequency alignment clock outputs externally applied clock input signal. QS5920A been specially designed interface with high speed SDRAM applications range 33MHz 100MHz includes internal filter which provides excellent jitter characteristics eliminates need external components. synchronous output enable (sOE) control sets outputs except (which used maintain phase lock) subsequent negative clock transition: partial output clock pulses produced.
Intel PC100/Spread Spectrum compliant outputs Balanced Drive Outputs ±12mA Synchronous output enable (sOE) control SDRAM power down mode External feedback, internal loop filter skew guaranteed between outputs Supports 33MHz 100MHz SDRAMs JEDEC compatible LVTTL 3.0V 3.6V supply voltage Industrial temperature range Inputs tolerant Available 24-pin QSOP packages
Figure Logic Block Diagram
CLKIN
FREQ_SEL
TEST
OUTPUT LOGIC
MDSC-00036-03 SEPTEMBER 1998
QUALITY SEMICONDUCTOR, INC.
QS5920A Figure Configuration (All Pins View)
16-Pin QSOP
CLKIN VCCQ FREQ_SEL GNDQ TEST
24Pin QSOP
CLKIN VCCQ FREQ_SEL GNDQ TEST
QS5920A-04
Table Description
Name CLKIN Q0.Q9 TEST Functional Description Clock input Clock outputs
feedback input normally connected user. connected output strapped low. Dedicated clock output (non-disable) Synchronous output enable. Asserted normal operation. When asserted HIGH, clock outputs (except QFB) forced LOW. When LOW, normal operation. When HIGH, disables opens bypass. CLKIN goes outputs.
FREQ_SEL(1)
frequency select. optimizing operating frequency. input frequencies within 33MHz 75MHz, HIGH 66MHz 100MHz. Power supply output buffers Power supply (quiet) Ground supply output buffers Ground supply (quiet)
VCCQ
Note: this input switched, function timing outputs glitch, require additional tLOCK time before datasheet limits achieved.
Table Absolute Maximum Ratings
Supply Voltage Ground -0.5V 7.0V Output Voltage VOUT -0.5V 0.5V Input Voltage -0.5V 7.0V Input Diode Current with -20mA Maximum Power Dissipation 85°C, 0.55W TSTG Storage Temperature -65° 150°C
Note: Stresses greater than those listed under absolute maximum ratings cause permanent damage devices that result functional reliability type failures.
QUALITY SEMICONDUCTOR, INC.
MDSC-00036-03 SEPTEMBER 1998
QS5920A Table Capacitance
25°C, 1MHz,
Pins
QSOP
Units
Note: Capacitance characterized tested.
Table Recommended Operating Conditions
Symbol Parameter Power Supply Voltage Input Voltage Ambient Operating Temperature Unit
Table Electrical Characteristics Over Operating Range
Symbol Parameter Input HIGH Voltage Input Voltage Clamp Diode Voltage Output HIGH Voltage (Q0:9, QFB) Output Voltage (Q0:9, QFB) Test Condition Guaranteed Logic HIGH inputs Guaranteed Logic inputs Min., -18mA Min., -12mA Min., -8mA Min., -100µA Min., 12mA Min., Min., 100µA Max.,
Typ(1) -0.7 -1.2
Unit
Note: Typical values indicate 3.3V 25°C.
Input Leakage Current
Table Power Supply Characteristics
Symbol Parameter ICCQ ICCD Quiescent Power Supply Current Power Supply Current Input HIGH(1) Dynamic Power Supply Current Output(1) Test Conditions Max., TEST High, CLKIN Low, outputs unloaded Max., 3.0V Max., Unit
Total Power Supply Current(1) 3.3V, fCLKIN 50MHz(2) 3.3V, fCLKIN 100MHz(2)
Notes: Guaranteed characterization production tested. outputs each loaded with 15pF.
MDSC-00036-03 SEPTEMBER 1998
QUALITY SEMICONDUCTOR, INC.
QS5920A Table Switching Characteristics Over Operating Range
Symbol Description tPWC fCLKIN tSK1 (SSC) tOPW tLOCK tR,tF tDEV Input clock pulse, high Input frequency CLKIN input delay, 100MHz Cycle cycle jitter, 100MHz Output duty cycle distortion CLKIN phase lock Output rise fall times (0.8V 2.0V)
(1,4) (1,3) (1,5)
-250 -100 -200
1.00
Unit
Output Output skew, outputs, same transition,100MHz Spread Spectrum Clock induced skew, 100MHz
(1,2) (1,2)
Output pulse width distortion
TCYCLE/2 0.65 TCYCLE/2 0.65
Skew between outputs different devices
Notes: This parameter guaranteed design verified during production statistical correlation. Output signal nominally duty cycle: maximum error period 0.65ns, whichever greater. Spread spectrum clock induced skew measured under PC-100 conditions 30kHz 50kHz modulation with peak deviation -0.5%. tDEV applies device operating under same conditions (VCC, ambient temperature, package, flow, etc.) outputs with 15pF Load.
TCYCLE
Figure Waveforms
3.0V 2.0V 1.5V 0.8V
CLKIN
tPWC LVTTL Input Test Waveform
2.0V 1.5V 0.8V
LVTTL Output Waveform
Figure Timing Diagram
tSK1 tSK1
Q0-Q9
QUALITY SEMICONDUCTOR, INC.
MDSC-00036-03 SEPTEMBER 1998
QS5920A Ordering Information
Clock Management Product Prefix (QS5) Part Number 920A Package
QSOP
920A-04 Clock Management Product Prefix (QS5) Part Number Package
QSOP
MDSC-00036-03 SEPTEMBER 1998
QUALITY SEMICONDUCTOR, INC.
Other recent searches
SN74ACT04 - SN74ACT04 SN74ACT04 Datasheet
SN54ACT04 - SN54ACT04 SN54ACT04 Datasheet
LQ801 - LQ801 LQ801 Datasheet
K4S64163LF-R - K4S64163LF-R K4S64163LF-R Datasheet
AUMP-16H - AUMP-16H AUMP-16H Datasheet
APTDC902U601G - APTDC902U601G APTDC902U601G Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
