Interfacing MCP2122 Host Controller Author: Mark Palmer Microchip
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Interfacing MCP2122 Host Controller
Author: Mark Palmer Microchip Technology Inc. clock used baud clock timing (transmit receive). There clocks (16XCLK) each time. systems that have already been designed with HSDL-7000, 16XCLK signal already present. systems that designed, generation clock signal will need done. embedded systems using PICmicro® microcontroller unit (MCU) Host Controller, Capture/Compare/PWM (CCP) Timer2 modules used generate 16XCLK signal. This accomplished using module mode. This application note will discuss methods with which interface MCP2122 Host Controller PICmicro MCU's Timer2 modules generate 16XCLK signal.
MCP2122 four signals that interfaced embedded systems Host Controller. These signals transmitted received data RX), 16XCLK signal RESET signal. MCP2122 pinout compatible with Agilent® HSDL-7000 Encoder/Decoder.
FIGURE
TYPICAL MCP2122 SYSTEM BLOCK DIAGRAM Host UART Interface
Host Controller PICmicro®
Protocol Handler MCP2122
Interface
Optical Transceiver
TFDU 4100
Encode
TXIR
UART
RESET Clock (I/O CCPx) 16XCLK
Decode Reset Logic Clock Logic
RXIR
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HOST UART INTERFACE
Host UART interface signals, Transmit signal (TX) Receive signal (RX). These signals connected Host Controller's UART, which either hardware module implemented firmware.
Board System Clock
Board System Clock easiest since already available. that needs done connect clock 16XCLK pin. This means that baud rate will 1/16th frequency this clock.
TABLE
INTERFACE
interface signals, Transmit signal (TXIR) Receive signal (RXIR). These signals connected optical transceiver circuitry, which either integrated device implemented with discrete components. UART/IR Baud Rate 9,600 19,200 38,400 57,600
UART/IR BAUD RATE 16XCLK
16XCLK 153,600 307,200 614,400 921,600 Comment
16XCLK
MCP2122 state machine operate, device must clocked. frequency clock 16XCLK must times desired baud rate (see Table Figure shows relationship 16XCLK signal either UART signals signals). source this clock could from number sources, including: Board System Clock Host controller-generated clock Firmware-generated clock Hardware-generated clock using time-based module (such PICmicro module) clock source differences between MCP2122 MCP2120. MCP2120 requires crystal create device clock. MCP2120's internal 16XCLK signal (device baud rate) then specified state BAUD2:BAUD0 pins. MCP2120's BAUD2:BAU0 pins configured that baud rate determined state these pins (Hardware mode) controlled Host Controller (Software mode).
115,200 1,843,200 Maximum device baud rate
FIGURE
16XCLK SIGNAL
Data Data
16XCLK
Value
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Host Controller Firmware-Generated Clock
Host Controller's firmware implement 16XCLK signal. However, this complexity timing-related issues other parts application firmware. desired baud rate increases (relative system clock), number "free" instruction cycles performing other firmware operations decreases. Every 16XCLK clock (pulse) rising edge falling edge that must generated. With PICmicro MCU, rising edge generated with instruction falling edge with instruction. instructions required each 16XCLK clock (pulse). Table shows available PICmicro instruction cycles given device frequency) desired Host UART/IR interface baud rate. This probably means that application that planning generate 16XCLK firmware would want exceed baud rate 19200. most cases, 9600 would probably desired ensure sufficient bandwidth accomplish other tasks. section entitled "Using PICmicro® MCU's Module Generate 16XCLK" discusses details using PICmicro module. Note: There other techniques that could used with PICmicro devices generate 16XCLK signal. These techniques include: hardware USART generate 16XCLK clock output implement functions firmware. This done using USART Synchronous Master mode with Continuous Receive enabled (CREN set). selected clock Baud rate will output TX/CLK PICmicro MCU. With devices that have accurate internal clock, select option output that clock external circuit create desired 16XCLK frequency.
Host Controller Hardware-Generated Clock
Using hardware features Host Controller eliminate processing overhead firmware implementation, well allow much faster baud rates used. typical PICmicro device system implementation would consist using module generate clock, with module being configured mode. frequency would required 16XCLK frequency (for desired baud rate).The duty cycle should configured about 50%. After initial configuration module (after reset PICmicro device), additional software overhead required. This clock will synchronized operation PICmicro device UART.
RESET
RESET used MCP2122 into known state. Forcing RESET will immediately force output pins their default output state, shown Table
TABLE
Input Name RESET State
MCP2122 DEFAULT OUTPUT STATES DEVICE RESET
Output State TXIR Device reset mode Comments
TABLE
PICMICRO® FREQUENCY/INSTRUCTION CYCLES HOST UART/IR BAUD RATE
16XCLK 153,600 307,200 614,400 921,600 1,843,200 Instruction Frequency 614,400 1,228,800 2,457,600 3,686,400 7,372,800 Instruction Cycles Device Frequency (MHz) 14.7456 18.432 19.6608 5.33 2.67 Maximum baud rate Comment
UART/IR Baud Rate 9,600 19,200 38,400 57,600 115,200
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USING PICmicro MCU'S MODULE GENERATE 16XCLK
module hardware module that configured Capture, Compare operation. This module works conjunction with either Timer1 Timer2, depending mode selected. mode required generation 16XCLK. generation, Timer2 module used create time-base. simplified block diagram PIC16F877A's module mode shown Figure PIC16F877A modules; this figure generic either. output waveform shown Figure period determines often waveform repeats, while duty cycle determines relationship between time signal high time signal low. 16XCLK signal, time desired. module takes advantage PICmicro MCU's internal clocks clocks instruction cycle) generation duty cycle PWM. This allows slower device frequencies (lower power) used given baud rate. minimum period instruction cycle (TCY). Note: There some small, low-cost PICmicro devices that have module. These include 8-pin PIC12F683 14-pin PIC16F684.
FIGURE
MODULE MODE BLOCK DIAGRAM
CCPxCON<5:4> (DCxB<1:0>) Module
Duty cycle registers CCPRxL (DCxB<9:2>) CCPRxH (Slave) Comparator TMR2 Comparator Note: Note
TRISC<y>
RCy/CCPx
Timer2 Module
Clear Timer, Force CCPx High, Latch Duty Cycle
8-bit timer concatenated with 2-bit internal clock bits prescaler create 10-bit time base.
FIGURE
OUTPUT WAVEFORM
Duty Cycle DCxB9:DCxB0 (approximately 50%) Period
Before Initialized
Cycle
Subsequent Cycles
Timer2 cleared duty cycle value loaded from duty cycle latch into duty cycle slave register Timer2 value equals value duty cycle latch register, with driven Timer2 matches register, value from duty cycle latch loaded into slave register, driven high, with Timer2 being forced clear
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period
period specified writing register. period calculated using Equation
Duty Cycle
duty cycle specified writing DCxB9:DCxB0 bits. DCxB9:DCxB2 contained CCPRxL register, while DCxB1:DCxB0 located CCPxCON<5:4>). CCPRxL contains eight MSbs, while CCPxCON<5:4> contains LSbs. This 10-bit value represented DCxB9:DCxB0. Equation used calculate duty cycle.
EQUATION
CALCULATION PERIOD
TPWM period [(PR2) TOSC (TMR2 prescale value) Where: Value Register ToSC Oscillator Clock
EQUATION
CALCULATING DUTY CYCLE
Duty Cycle (DCxB<9:0> bits value) TOSC (TMR2 prescale value) Where: Duty Cycle Duty Cycle Time TOSC Oscillator Clock Though DCxB<9:0> bits written time, duty cycle value latched into CCPRxH until after match between TMR2 occurs (which marks current period). mode, CCPRxH read-only register. CCPRxH register 2-bit internal latch used double buffer duty cycle. This double buffering essential glitchless operation. When CCPRxH 2-bit latch match value TMR2 concatenated with internal 2-bit clock bits TMR2 prescaler), CCPx cleared. This marks duty cycle. Note: duty cycle value longer than period, CCPx will cleared. This allows duty cycle 100%.
frequency defined [PWM period]. When TMR2 equal PR2, following three events occur next increment cycle: TMR2 cleared CCPx (exception: duty cycle CCPx will set) duty cycle latched from CCPRxL into CCPRxH
period determines frequency 16XCLK signal. This corresponds UART/IR baud rate. Table shows, common UART/IR baud rates PICmicro frequencies, what (PWM period) CCPRxL (PWM duty cycle) values are.
Table shows (PWM period) CCPRxL (PWM duty cycle) values configure given UART/IR baud rate selected device frequencies.
TABLE
UART/IR Baud Rate 9,600 19,200 38,400 57,600 115,200 Note
PICmicro® FREQUENCY HOST UART/IR BAUD RATE
Device Frequency (MHz) 16XCLK Frequency 153,600 307,200 614,400 921,600 1,843,200 Instruction Frequency 614,400 1,228,800 2,457,600 3,686,400 7,372,800 TMR2 Prescaler 14.7456 CCPRxL 3728 CCPRxL 3.6864 CCPRxL
CCPxX:CCPxY bits always `11'b CCPxX:CCPxY `00'b will supply approximately duty cycle when CCPRxL CCPxX:CCPxY `10'b will supply duty cycle when CCPRxL value selected this baud rate (too much clock error). configured this baud rate this device frequency.
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CCPx multiplexed with PORT data latch corresponding TRIS must cleared make CCPx output.
SUMMARY
This application note shown Host Controller interfaced MCP2122. Several methods have been discussed, with detailed discussion PICmicro MCU's module. source code example PIC16F877A code provided Appendix Appendix shows screen captures (16XCLK) data timings from PIC16F877A code. This should help bootstrap development applications that plan using MCP2122.
Set-up Operation
following steps configure module operation: Establish period writing register. Establish duty cycle writing DCxB9:DCxB0 bits (CCPR1L register CCP1CON<5:4> bits). Make CCPx output clearing appropriate TRISC bit. Establish TMR2 prescale value enable Timer2 writing T2CON. Configure module operation.
Sleep Operation
When PIC16F877A placed sleep, Timer2 will increment state module will change. driving value, will continue drive that value. When device wakes will continue from this state. Note: desired place PICmicro device Sleep mode, good practice force known state before going "sleep". This done disabling (CCP Timer2 modules) forcing desired state.
Effects Reset
When PIC16F877A reset, Timer2 modules forced off. Timer2 module will need reconfigured operation.
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APPENDIX
FIGURE A-1:
PIC16F877A SOURCE CODE MCP2122TX.ASM
MCP2122TX.ASM PAGE
LIST C=132 include P16F877A.inc ERRORLEVEL -302, -306 Software License Agreement software supplied herewith Microchip Technology Incorporated (the "Company") intended supplied you, customer, solely exclusively with products manufactured Company. software owned Company and/or supplier, protected under applicable copyright laws. rights reserved. violation foregoing restrictions subject user criminal sanctions under applicable laws, well civil liability breach terms conditions this license. THIS SOFTWARE PROVIDED CONDITION. WARRANTIES, WHETHER EXPRESS, IMPLIED STATUTORY, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE APPLY THIS SOFTWARE. COMPANY SHALL NOT, CIRCUMSTANCES, LIABLE SPECIAL, INCIDENTAL CONSEQUENTIAL DAMAGES, REASON WHATSOEVER. MCP2122 Transmit Data Code This code will generate clock continuously transmit known byte value (bit stream). variables "BaudRate" "TXValue" must first selected program then assembled downloaded these configurations become effective. After Reset PICmicro(r) MCU, device baud rate will determine values load into UART CCP1 (PWM mode)/Timer2 registers. TXValue will value that continuously transmitted. Device: PIC16F877A Platform: PICDEM2 Plus Device Frequency: Fosc 14.7456MHz PORTC used interface MCP2122 device. signals this port are: 16XCLK, RESET Revision History 06/10/04 Initial Release
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FIGURE A-2: MCP2122TX.ASM PAGE
PICDEM Plus Requirements Clock Frequency: 14.7456 UART Baud: 9600, 19200, 38400, 57600, 115200 16XCLK: 153600, 307200, 614400, 921600, 1843200 Instructions/bit 115200 Baud) 14.7456/1.8432 instrctions/byte) PIC16F877 PORT Functions PORTA Function TRIS Direction Initial value PORTB Function LCD3 LCD2 LCD1 LCD0 TRIS Direction Initial value PORTC Function RST213X CCP1 TRIS Direction Initial value PORTD Function TRIS Direction Initial value PORTE Function TRIS Direction Initial value #define reset H'00' ;Reset vector Configuration Bits _CONFIG _CP_OFF _PWRTE_ON _HS_OSC _WDT_OFF _BODEN_OFF _LVP_OFF _WRT_HALF _CPD_OFF _DEBUG_ON _IDLOCS H'0010' PIC16F877 _CONFIG _CP_OFF _PWRTE_ON _HS_OSC _WDT_OFF _BODEN_OFF _LVP_OFF _WRT_ENABLE_ON _CPD_OFF _DEBUG_ON
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FIGURE A-3: MCP2122TX.ASM PAGE
PortA Bits #define PORTC, input, serial data from MCP2122 #define PORTC, output, serial data MCP2122 #define RESET213x PORTC, output, used reset MCP2122 high normal operation, RESET device
Program Definitions ddra B'00000000' Data Direction PORTA (output port) ddrb B'00000000' Data Direction PORTB (output port) ddrc B'11000000' Data Direction PORTC (input/output port) ddrd B'00000000' Data Direction PORTD (output port) ddre B'00000000' Data Direction PORTE (output port) cfgopt B'11001000' option setup Constants ;BaudRate D'9600' ;BaudRate D'19200' ;BaudRate D'38400' ;BaudRate D'57600' BaudRate D'115200'
;TXValue ;TXValue ;TXValue ;TXValue ;TXValue TXValue ;TXValue ;TXValue ;TXValue ;TXValue
0xFF 0x00 0x7E 0x81 0xFE 0x01 0xAA 0x55 0xC3 0x3C
Value transmit
Host UART Data Rate/BRG Value (BRGH SPBRG Value Baud Rate 20MHz 16MHz 14MHz 9600 19200 57600 115200 SPBRG Value B9600at14xMHz D'95' B19200at14xMHz D'47' B38400at14xMHz D'23' B57600at14xMHz D'15' B115200at14xMHz D'07'
4MHz N.A. N.A.
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FIGURE A-4: MCP2122TX.ASM PAGE
Values generate 16XCLK (For duty cycle register, CCP1X CCP1Y bits "1") Value CCPR1L Value PR2B9600at14xMHz D'23' D'11' PR2B19200at14xMHz D'11' D'05' PR2B38400at14xMHz D'05' D'02' PR2B57600at14xMHz D'03' D'01' PR2B115200at14xMHz D'01' D'00' (BaudRate D'9600') UARTBaud B9600at14xMHz PWMPR2Value PR2B9600at14xMHz endif (BaudRate D'19200') UARTBaud B19200at14xMHz PWMPR2Value PR2B19200at14xMHz endif (BaudRate D'38400') UARTBaud B38400at14xMHz PWMPR2Value PR2B38400at14xMHz endif (BaudRate D'57600') UARTBaud B57600at14xMHz PWMPR2Value PR2B57600at14xMHz endif (BaudRate D'115200') UARTBaud B115200at14xMHz PWMPR2Value PR2B115200at14xMHz endif Registers cblock H'20' temp endc H'00' reset vector goto START Start Routine post-reset setup done here START clrf STATUS Bank movlw 0xFF Force PORTB display High when configured Output movwf PORTB STATUS, Bank movlw ddra movwf TRISA Configure PORTA movlw ddrb movwf TRISB Configure PORTB movlw ddrc movwf TRISC Configure PORTC movlw ddrd movwf TRISD Configure PORTD movlw ddre movwf TRISE Configure PORTE movlw cfgopt setup option movwf OPTION_REG
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FIGURE A-5: MCP2122TX.ASM PAGE
Operational Baud Rate Initialize UART 16XCLK (TMR2 CCP1 modules) INITBAUD CLRF STATUS Bank CLRF CCP1CON CCP1 Module CLRF T2CON Timer Off, Prescaler Postscaler STATUS, Bank MOVLW UARTBaud Initialize UART MOVWF SPBRG movlw 0x24 BRGH 8-bit, Enabled, Async. movwf TXSTA CLRF STATUS Bank MOVLW 0x90 Enable serial port, continuous receive MOVWF RCSTA Initialize Frequency Duty Cycle CLRF TMR2 TMR2 MOVLW 0xFF MOVWF CCP1CON mode, CCP1X:CCP1Y MOVLW (PWMPR2Value-1)/2 MOVWF CCPR1L Load Duty Cycle value STATUS, Bank MOVLW PWMPR2Value MOVWF Load Period value CLRF STATUS Bank T2CON, TMR2ON Turn Timer 16XCLK generated CLRF PORTB clear outputs (Display LEDs) Transmit Value Routine TXData CLRF STATUS Bank RESET213x Force MCP2122 RESET (MCP2122 RESET) Hold MCP2122 reset some time RESET213x Force MCP2122 RESET High (Normal Operation) TXValueLP1 STATUS, Bank UARTWaitLP btfss TXSTA, TRMT check UART ready transmit goto UARTWaitLP ready, wait STATUS, Bank MOVLW TXValue This value byte send movwf TXREG send byte GOTO TXValueLP1 LAST
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APPENDIX SCREEN CAPTURE TIMING
following screen captures (from Figure Figure B-5) show time single data indicated baud rate. circled time shows measured baud rate.
FIGURE B-1:
TIMING CAPTURE 9600 BAUD
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FIGURE B-2: TIMING CAPTURE 19200 BAUD
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FIGURE B-3: TIMING CAPTURE 38400 BAUD
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FIGURE B-4: TIMING CAPTURE 57600 BAUD
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FIGURE B-5: TIMING CAPTURE 115200 BAUD
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