Using External with PIC17CXX Devices Author: Rodger Richey Advanc
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TB005
Using External with PIC17CXX Devices
Author: Rodger Richey Advanced Microcontroller Technology Division
TABLE INTERNAL/EXTERNAL MEMORY
Device Internal PIC17C42 External Internal PIC17C43 External Internal PIC17C44 External Size (Words) Address Range
2048 63488 4096 61440 8192 57344
Introduction
This Technical Brief shows connect PIC17CXX device external memory. also provides instructions calculations help determine which speeds SRAM work with which frequency crystal.
0x0000 0x07FF 0x0800 0xFFFF 0x0000 0x0FFF 0x1000 0xFFFF 0x0000 0x1FFF 0x2000 0xFFFF
System Configuration
doing FFT's? Storing arrays data? Typically, speed designs would EEPROM hold data that being generated. other hand, high speed designs need static because faster access times. External SRAM easily integrated with PIC17CXX device create SRAM bank your design requires. Data storage retrieval accomplished through table read table write instructions. equations lead timing also applied EPROMs. first thing need know much system requires. Table shows much external memory used with PIC17CXX family members. microcontroller into extended microcontroller mode which access both internal external memory. Both internal external memory 16-bits wide.
next step connect external SRAM PIC17CXX. Appendix shows schematic connecting MT5C2568 (32Kx8) SRAM devices PIC17C43. MT5C2568 obtained from Micron Semiconductor. only additional hardware required latches (74ACT373s 74ACT573s). Both chips octal latches 74ACT573 inputs outputs opposite sides chip which makes interfacing microcontroller easier.
1996 Microchip Technology Inc.
DS91004A-page
This document created with FrameMaker
TB005
READ TIMINGS
that know connect hardware, next step determine speed grade SRAM. Let's first take look read timings. Figure shows combined timing diagram read cycle PIC17C4X device MT5C2568 SRAM.
FIGURE PIC17C4X/MT5C2568 READ CYCLE TIMING DIAGRAM
OSC1
TADZ2OEL TOEL AD<15:0> Addr TADV2ALL TADV2OEH TPD573 A<15:0> Addr Valid TPDGAL TALL2ADI TACC TOEH2ADI Data Addr
TLZOE TLZCE
Data Valid
THZOE TAOE
TACE
value TACE shows which speed grade SRAM required read cycle. Figure three locations marked that help define TACE. Table summarizes these locations.
TABLE LOCATION MARKER DESCRIPTIONS FIGURE
Location Description Address Setup Time. This location marks spot where address becomes valid PIC17CXX before goes LOW. cycle) Propagation delay 74ACT573. This spot where address SRAM becomes valid. cycle) Propagation delay address decoder. This spot where signal from address decoder SRAM goes LOW. cycle) 0.25 Value time nanoseconds before cycle (TADV2ALL) time nanoseconds before cycle (TPD573)
TPDGAL
time nanoseconds before cycle
DS91004A-page
1996 Microchip Technology Inc.
TB005
TABLE MEMORY INTERFACE READ REQUIREMENTS
TADV2ALL TALL2ADI TADZ2OEL TADV2OEH TOEH2ADI TOEL TPD573 TACC TPDGAL TLZOE TAOE TLZCE TACE THZOE Characteristic AD15:AD0 (address) valid (address setup time) address invalid (address hold time) AD15:AD0 hi-impedance Data valid before (data setup time) OEto data invalid (data hold time) pulse width Output enable access time Data Valid) Propagation delay input output Address access time Propagation delay input combinatorial output output access time output access time Output disable output High 0.25Tcy 0.5Tcy 0.75Tcy 0.5TCY Units
determine TACE from Figure following equation used. Each part equation related timing parameter marked locations Figure
TACE 0.75 TPDGAL Address access time TACC Propagation delay 74ACT573 TPD573 Propagation delay address decoder
Finally, lets find some example speed grades various crystal frequencies. thing remember that this only read timing speed grade. must also calculate write timing speed grade. speed grade SRAM dependent address decoder. Typically, programmable array logic devices such 16V8 22V10 used. propagation delays these devices anywhere from
(TCY TACE 0.75 TPDGAL TACE TACE (TCY TACE 0.75 TPDGAL 157.5 TACE (TCY TACE 0.75 TPDGAL TACE (TCY TACE 0.75 TPDGAL
TPDGAL TACE TPDGAL
TPDGAL TACE 151.5 TPDGAL
TPDGAL TACE TPDGAL
TPDGAL TACE TPDGAL
reduce total propagation delay 74ACT573 address decoder, address/data lines from PIC17C4X routed address decoder. address latches address decoding performed parallel.
DS91004A-page
1996 Microchip Technology Inc.
TB005
WRITE TIMINGS
that have determined read timing speed grade, time calculate write timing speed grade SRAM your design. Figure shows combined timings write cycle PIC17C4X devices MT5C2568. Again, there markings some locations which described Table
FIGURE PIC17C4X/MT5C2568 WRITE CYCLE TIMING DIAGRAM
OSC1
TADV2ALL AD<15:0> TPD573 addr
TALL2ADI
TWRL data TADV2WRL addr valid TWRH2ADI addr
A<15:0>
TPDGAL
D<15:0>
data valid TWRL
TABLE LOCATION MARKER DESCRIPTIONS FIGURE
Location Description Address Setup Time. This location marks spot where address becomes valid PIC17CXX before goes LOW. cycle) Propagation delay 74ACT573. This spot where address SRAM becomes valid. cycle) Propagation delay address decoder. This spot where signal from address decoder SRAM goes LOW. cycle) Write pulse goes LOW. SRAM specifies that address it's inputs must valid before this point. cycle) 0.25 Value time nanoseconds before cycle (TADV2ALL)
time nanoseconds before cycle
TPDGAL
time nanoseconds before cycle
DS91004A-page
1996 Microchip Technology Inc.
TB005
TABLE MEMORY INTERFACE WRITE REQUIREMENTS
TADV2ALL TALL2ADI TADV2WRL TWRH2ADI TWRL TPD573 TPDGAL Characteristic AD<15:0> (address) valid (address setup time) address invalid (address hold time) Data valid (data setup time) data invalid (data hold time) pulse width Propagation delay input output Propagation delay input combinatorial output Data setup time write Address valid write Data hold time pulse width 0.25Tcy 0.25Tcy 0.25TCY 0.25TCY Units
critical timing specification write cycle when signal from address decoder SRAM goes LOW. Typically SRAM specifies this parameter (TAS MT5C2568). other important SRAM specifications check against PIC17C4X are: Write enable pulse width Data setup time, data valid before goes HIGH Data hold time, data valid after goes HIGH following some calculations write cycle various speed grades. These calculations used determine above specifications invalid. Micron MT5C2568 specifies following values above parameters: min. speed grades min. speed grade min. speed grade min. speed grades PIC17C4X specifies following values: 0.25 0.25 min. 0.25 TWRL TADV2WRL TWRH2ADI
DS91004A-page
1996 Microchip Technology Inc.
TB005
(TCY TADV2ALL 0.25 TADV2ALL (TCY TADV2ALL 0.25 TADV2ALL (TCY TADV2ALL 0.25 TADV2ALL (TCY TADV2ALL 0.25 TADV2ALL
TPDGAL TWRL 0.25
TPDGAL TWRL 0.25
TPDGAL TWRL 0.25
TPDGAL TWRL 0.25
TADV2WRL 0.25 TADV2WRL 0.25 TADV2WRL 0.25 TADV2WRL 0.25 0.25 0.25 0.25 0.25 TWRH2ADI 0.25 TADV2ALL TWRH2ADI 0.25 TADV2ALL 52.5 32.5 TWRH2ADI 0.25 TADV2ALL TWRH2ADI 0.25 TADV2ALL
TPDGAL TWRL TADV2WRL TWRH2ADI TADV2ALL TPDGAL TWRL TADV2WRL TWRH2ADI
TPDGAL 62.5 TWRL 62.5 TADV2WRL 227.5 TWRH2ADI 62.5 TADV2ALL 52.5 TPDGAL TWRL TADV2WRL TWRH2ADI
TPDGAL TWRL TADV2WRL TWRH2ADI TADV2ALL TPDGAL TWRL TADV2WRL TWRH2ADI
TPDGAL TWRL TADV2WRL TWRH2ADI TADV2ALL TPDGAL TWRL TADV2WRL TWRH2ADI
Assuming that 16V8 with propagation delay used address decoder, that crystal frequencies have greater than other parameters TADV2WRL, TWRH2ADI, TWRL have least spare room. parameters TADV2WRL, TWRH2ADI, TWRL were taken from speed grade SRAM. Therefore, speed grades MT5C2568 used write cycle PIC17C4X with external oscillator frequency MHz.
CONCLUSION
that have done calculations, let's determine proper SRAM speed grade various frequencies. only assumption that 16V8 used address decoding. SRAM SRAM SRAM SRAM
DS91004A-page
1996 Microchip Technology Inc.
4.7k AD10 AD11 AD12 AD13 AD14 AD15 74ACT573
TB005
DS91004A-page
RD0/AD8 RD1/AD9 RD2/AD10 RD3/AD11 RD4/AD12 RD5/AD13 RD6/AD14 RD7/AD15 MCLR/VPP RE0/ALE RE1/OE RE2/WR TEST RA0/INT RA1/T0CKI RA4/RX/DT RA5/TX/CK MT5C2568 Note Note AD10 AD11 AD12 AD13 AD14 AD15 74ACT573 Address Decoder MT5C2568
RC0/AD0 RC1/AD1 RC2/AD2 RC3/AD3 RC4/AD4 RC5/AD5 RC6/AD6 RC7/AD7 RB0/CAP1 RB1/CAP2 RB2/PWM1 RB3/PWM2 RB4/TCLK12 RB5/TCLK3 OSC1/CLKIN OSC2/CLKOUT
APPENDIX PIC17C4X EXTERNAL SCHEMATIC
Note
Note value crystal dependent your system requirements. value capacitors dependent crystal.
1996 Microchip Technology Inc.
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rights reserved. 1999 Microchip Technology Incorporated. Printed USA. 11/99
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Information contained this publication regarding device applications like intended suggestion only superseded updates. representation warranty given liability assumed Microchip Technology Incorporated with respect accuracy such information, infringement patents other intellectual property rights arising from such otherwise. Microchip's products critical components life support systems authorized except with express written approval Microchip. licenses conveyed, implicitly otherwise, under intellectual property rights. Microchip logo name registered trademarks Microchip Technology Inc. U.S.A. other countries. rights reserved. other trademarks mentioned herein property their respective companies.
1999 Microchip Technology Inc.
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