8-BIT WITH FLASH MEMORY, 10-BIT ADC, 16-BIT TIMERS, I2C, SPI, Mem
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ST72340, ST72344, ST72345
8-BIT WITH FLASH MEMORY, 10-BIT ADC, 16-BIT TIMERS, I2C, SPI,
Memories Kbytes Program memory: Single voltage extended Flash (XFlash) with read-out write protection, In-Circuit In-Application Programming (ICP IAP). write/ erase cycles guaranteed, data retention: years 55°C. Kbyte bytes data EEPROM with read-out protection. 300K write/erase cycles guaranteed, data retention: years 55°C. Clock, Reset Supply Management Power Power safe reset with programmable threshold levels (LVD) Power Down Voltage Detector (PDVD) Clock sources: crystal/ceramic resonator oscillators, high-accuracy internal oscillator external clock frequency multiplication Power Saving Modes: Slow, Wait, Halt, Auto-Wakeup from Halt Active Halt Clock output capability (fCPU) Interrupt Management Nested interrupt controller interrupt vectors plus TRAP RESET external interrupt lines vectors Ports multifunctional bidirectional lines 32-pin devices) high sink outputs 32-pin devices) Timers Configurable window watchdog timer Realtime base 16-bit timer with: input capture, output compares, external clock input, Pulse generator modes Device Summary
LQFP32
QFN40
LQFP44
LQFP48
TFBGA56
16-bit timer with: input captures, output compares, Pulse generator modes Communication Interfaces Multi Master Slave Slave Addresses Stretch with access Byte Pair Coherency Read asynchronous serial interface (LIN compatible) synchronous serial interface Analog peripheral 10-bit with input channels 32pin devices) Instruction 8-bit data manipulation basic instructions with illegal opcode detection main addressing modes unsigned multiply instruction Development tools Full hardware/software development package On-Chip Debug Module
Features
Program memory bytes (stack) bytes EEPROM data bytes Common peripherals Other peripherals high-accuracy 1MHz Frequency Temperature Range Package
ST72F340
(256)
ST72F344
ST72F345
(256) (256) (256) (256) Window Watchdog, 16-bit Timers, SCI, SPI, I2CMMS 10-bit I2C3SNS, 10-bit present Present Present 8MHz 3.3V 5.5V, 4MHz 2.7V 5.5V -40°C LQFP32 7x7, LQFP44 10x10, QFN40 TFBGA56 6x6, LQFP48
Rev.
April 2006 1/190
This preliminary information product development undergoing evaluation. Details subject change without notice.
Table Contents
INTRODUCTION DESCRIPTION REGISTER MEMORY FLASH PROGRAM MEMORY INTRODUCTION MAIN FEATURES PROGRAMMING MODES INTERFACE MEMORY PROTECTION REGISTER DESCRIPTION
DATA EEPROM INTRODUCTION MAIN FEATURES MEMORY ACCESS POWER SAVING MODES ACCESS ERROR HANDLING DATA EEPROM READ-OUT PROTECTION REGISTER DESCRIPTION
CENTRAL PROCESSING UNIT INTRODUCTION MAIN FEATURES REGISTERS
SUPPLY, RESET CLOCK MANAGEMENT PHASE LOCKED LOOP MULTI-OSCILLATOR (MO) REGISTER DESCRIPTION RESET SEQUENCE MANAGER (RSM) SYSTEM INTEGRITY MANAGEMENT (SI)
INTERRUPTS INTRODUCTION MASKING PROCESSING FLOW INTERRUPTS POWER MODES CONCURRENT NESTED MANAGEMENT INTERRUPT REGISTER DESCRIPTION EXTERNAL INTERRUPTS EXTERNAL INTERRUPT CONTROL REGISTER (EICR)
POWER SAVING MODES INTRODUCTION SLOW MODE WAIT MODE HALT MODE ACTIVE-HALT MODE
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Table Contents
AUTO WAKE FROM HALT MODE PORTS 10.1 INTRODUCTION 10.2 FUNCTIONAL DESCRIPTION 10.3 PORT IMPLEMENTATION 10.4 POWER MODES 10.5 INTERRUPTS ON-CHIP PERIPHERALS 11.1 WINDOW WATCHDOG (WWDG) 11.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK BEEPER (MCC/RTC) 11.3 16-BIT TIMER 11.4 SERIAL PERIPHERAL INTERFACE (SPI) 11.5 SERIAL COMMUNICATION INTERFACE 11.6 INTERFACE (I2C) 11.7 TRIPLE SLAVE INTERFACE WITH (I2C3S) 11.8 10-BIT CONVERTER (ADC) INSTRUCTION 12.1 ADDRESSING MODES 12.2 INSTRUCTION GROUPS ELECTRICAL CHARACTERISTICS 13.1 PARAMETER CONDITIONS 13.2 ABSOLUTE MAXIMUM RATINGS 13.3 OPERATING CONDITIONS 13.4 CHARACTERISTICS 13.5 INTERNAL OSCILLATOR CHARACTERISTICS 13.6 SUPPLY CURRENT CHARACTERISTICS 13.7 CLOCK TIMING CHARACTERISTICS 13.8 MEMORY CHARACTERISTICS 13.9 CHARACTERISTICS 13.10 PORT CHARACTERISTICS 13.11 CONTROL CHARACTERISTICS 13.12 COMMUNICATION INTERFACE CHARACTERISTICS 13.13 10-BIT CHARACTERISTICS 13.14 10-BIT CHARACTERISTICS PACKAGE CHARACTERISTICS 14.1 PACKAGE MECHANICAL DATA DEVICE CONFIGURATION ORDERING INFORMATION 15.1 OPTION BYTES 15.2 DEVICE ORDERING INFORMATION KNOWN LIMITATIONS 16.1 EXTERNAL INTERRUPT MISSED 16.2 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE
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Table Contents
16.3 16-BIT TIMER MODE 16.4 WRONG BREAK DURATION REVISION HISTORY
Please special attention Section "KNOWN LIMITATIONS" page
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INTRODUCTION
ST7234x devices members microcontroller family. devices based common industry-standard 8-bit core, featuring enhanced instruction set. They feature single-voltage FLASH memory with byte-by-byte In-Circuit Programming (ICP) InApplication Programming (IAP) capabilities. Under software control, devices placed WAIT, SLOW, Auto-Wakeup from Halt, ActiveHALT HALT mode, reducing power consumption when application idle stand-by state. Figure General Block Diagram
8-BIT CORE RESET CONTROL (512- 1024 Bytes) OSC1 OSC2 CLOCK CONTROL ADDRESS DATA INTERNAL MCC/RTC/BEEP WATCHDOG I2CMMS PORT PROGRAM MEMORY (16K Bytes)
enhanced instruction addressing modes offer both power flexibility software developers, enabling design highly efficient compact application code. addition standard 8-bit data management, microcontrollers feature true manipulation, unsigned multiplication indirect addressing modes. devices feature on-chip Debug Module (DM) support in-circuit debugging (ICD). description registers, refer Protocol Reference Manual.
(5-bits)
PORT (5-bits)
PORT (6-bits) TIMER BEEP
PORT TIMER I2C3SNS (6-bits) PORT 10-BIT VAREF VSSA PORT (8-bits)
(2-bits)
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DESCRIPTION
Figure LQFP32 Package Pinout
AIN1 AIN0 (HS) VDD_2 VDDA VSSA AIN8 (HS) OCMP1_A AIN10 ICAP1_A (HS) EXTCLK_A (HS) AIN12 OCMP2_B
OSC1 OSC2 VSS_2 RESET ICCSEL (HS) (HS) (HS)
AIN13 OCMP1_B ICAP2_B (HS) ICAP1_B (HS) ICCDATA MISO AIN14 MOSI ICCCLK AIN15 (HS)
(HS) 20mA high sink capability associated external interrupt vector
Figure QFN40 Package Pinout
(HS) (HS) (HS) VSS_1
(HS) AIN0 AIN1 AIN2 AIN3
(HS)
OSC1
OSC2 RESET ICCSEL
VDD_1 (HS) AIN15 ICCCLK MOSI AIN14 MISO ICCDATA (HS) ICAP1_B (HS) ICAP2_B OCMP1_B AIN13 OCMP2_B AIN12
AIN4 AIN5 VDDA VSSA
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AIN8 BEEP (HS) (HS) OCMP1_A AIN10 ICAP1_A (HS) EXTCLK_A (HS)
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DESCRIPTION (Cont'd) Figure LQFP44 Package Pinout
VDD_2 OSC1 OSC2 VSS_2 RESET ICCSEL (HS) (HS) (HS) (HS) (HS) AIN0 AIN1 AIN2 AIN3 AIN4
VSS_1 VDD_1 (HS) AIN15 ICCCLK MOSI AIN14 MISO ICCDATA (HS) ICAP1_B (HS) ICAP2_B OCMP1_B AIN13 OCMP2_B AIN12
Figure 48-Pin LQFP Package Pinout
VDD_2 OSC1 OSC2 VSS_2 RESET ICCSEL (HS)/SCL (HS)/SDA (HS) (HS) PD6/SDA3SNS PD7/SCL3SNS
AIN5 VDDA VSSA AIN8 BEEP (HS) (HS) OCMP1_A AIN10 ICAP1_A (HS) EXTCLK_A (HS) VDD_0 VSS_0
PE0/TD0 (HS) AIN0 AIN1 AIN2 AIN3 AIN4
VSS_1 VDD_1 (HS) AIN15 ICCCLK MOSI AIN14 MISO ICCDATA (HS) ICAP1_B (HS) ICAP2_B OCMP1_B AIN13
AIN5 VDDA VSSA AIN8 BEEP (HS) (HS) OCMP1_A AIN10 ICAP1_A (HS) EXTCLK_A (HS) VDD_0 VSS_0 OCMP2_B AIN12
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DESCRIPTION (Cont'd) Figure TFBGA56 Package Pinout
Notes: Reserved, must tied ground Reserved, must left floating
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DESCRIPTION (Cont'd) external connection guidelines, refer "ELECTRICAL CHARACTERISTICS" page 153. Legend Abbreviations Table Type: input, output, supply Input level: Dedicated analog input In/Output level: CMOS 0.3VDD/0.7VDD with input trigger Output level: 20mA high sink N-buffer only) Port control configuration: Input: float floating, weak pull-up, interrupt analog Output: open drain push-pull RESET configuration each shown bold. This configuration valid long device reset state. chip, each port have pads. Pads that bonded external pins input pull-up configuration after reset through option byte Package selection. configuration these pads must kept reset state avoid added current consumption. Table Device Description
TQFP32 TQFP44 TQFP48 Type QFN40 Name Level Output Input Port Input float Main function Output (after reset)
Alternate Function
VDDA VSSA PF0/MCO/ AIN8 (HS)/ BEEP (HS) PF4/ OCMP1_A/ AIN10 (HS)/ ICAP1_A (HS)/ EXTCLK_A VDD_0
Analog Supply Voltage Analog Ground Voltage Port Port Port Port Port Port Timer AnaOutput Compare Input Timer Input Capture Timer External Clock Source AnaMain clock (fOSC/2) Input Beep signal output
Digital Main Supply Voltage Digital Ground Voltage Port Timer AnaOutput Compare Input Timer AnaOutput Compare Input Timer Input Capture
VSS_0 PC0/ OCMP2_B/ AIN12 PC1/ OCMP1_B/ AIN13 (HS)/ ICAP2_B
Port Port
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TQFP32 TQFP44 TQFP48 Type QFN40 Name
Level Output Input
Port Input float
(HS)/ ICAP1_B PC4/MISO/ ICCDATA3) PC5/MOSI/ AIN14 PC6/SCK/ ICCCLK3)
Main function Output (after reset) Port Port
Alternate Function
Timer Input Capture Master Data Slave Input Data Master AnaOut Slave Data Input Serial Clock Slave Select (active low) Clock Output Analog Input
Port Port Port Port
PC7/SS/AIN15 (HS)
VDD_1 VSS_1 PD7/ SCL3SNS PD6/ SDA3SNS (HS) (HS)
Digital Main Supply Voltage Digital Ground Voltage Port Port Port Port Port Port Serial Data Serial Clock I2C3SNS Serial Clock I2C3SNS Serial Data
(HS)/SDA (HS)/SCL ICCSEL ICCDATA ICCCLK RESET VSS_2 OSC2 OSC1 VDD_2 PE0/TDO PE1/RDI (HS)
Mode selection Data Input Clock Output priority maskable interrupt. Digital Ground Voltage Resonator oscillator inverter output External clock input Resonator oscillator inverter input Digital Main Supply Voltage Port Port Port Port Port Port Port Port Port Port Analog Input Analog Input Analog Input Transmit Data Receive Data
PD0/AIN0 PD1/AIN1 PD2/AIN2
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TQFP32 TQFP44 TQFP48 Type QFN40 Name
Level Output Input
Port Input float
PD3/AIN3 PD4/AIN4 Reserved PD5/AIN5 Reserved Reserved Reserved Reserved
Main function Output (after reset) Port Port Port
Alternate Function
Analog Input Analog Input Analog Input
Reserved, must tied ground Must tied ground Must left floating Must left floating Must left floating Must left floating Must left floating Must left floating
Reserved
Reserved
Reserved
Notes: interrupt input column, "eiX" defines associated external interrupt vector. weak pull-up column (wpu) merged with interrupt column (int), then configuration pull-up interrupt input, else configuration floating interrupt input. open drain output column, defines true open drain (P-Buffer protection diode implemented). package, ICCDATA ICCCLK bonded pins respectively. They implemented alternate functions PC6.
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REGISTER MEMORY
shown Figure capable addressing Kbytes memories registers. available memory locations consist bytes register locations, Kbytes RAM, bytes Data EEPROM Kbytes Figure Memory user program memory. space includes bytes stack from 0100h 01FFh. highest address bytes contain user reset interrupt vectors.
0000h 007Fh 0080h 047Fh 0480h 0BFFh 0C00h 0CFFh 0D00h BFFFh C000h
Registers Table (512 Bytes) Reserved Data EEPROM (256 Bytes) Reserved Program Memory KBytes)
0080h
Short Addressing (zero page)
00FFh 0100h
Bytes Stack
01FFh 0200h
16-bit Addressing
047Fh C000h C000h
SECTOR KBytes
E000h E000h F000h (4k) FB00h (2k) FC00h (1k) FE00h (0.5k) FFFFh
FFDFh FFE0h FFFFh
SECTOR
Interrupt Reset Vectors Table
FFFFh
KBytes
SECTOR
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REGISTER MEMORY (Cont'd) Table Hardware Register
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0016h 0017h 0018h 0019h 001Ah 001Fh 00020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 00029h 002Ah 002Bh FLASH WWDG DM3) EEPROM EECSR SPIDR SPICR SPICSR ISPR0 ISPR1 ISPR2 ISPR3 EICR FCSR WDGCR SICSR RCCRH RCCRL Block Register Label PADR PADDR PAOR PBDR PBDDR PBOR PCDR PCDDR PCOR PDADR PDDDR PDOR PEDR PEDDR PEOR PFDR PFDDR PFOR Register Name Port Data Register Port Data Direction Register Port Option Register Port Data Register Port Data Direction Register Port Option Register Port Data Register Port Data Direction Register Port Option Register Port Data Register Port Data Direction Register Port Option Register Port Data Register Port Data Direction Register Port Option Register Port Data Register Port Data Direction Register Port Option Register Reserved area bytes) oscillator Control Register High oscillator Control Register Reserved area byte) Reserved area bytes) Data EEPROM Control/Status Register Data Register Control Register Control Status Register Interrupt Software Priority Register Interrupt Software Priority Register Interrupt Software Priority Register Interrupt Software Priority Register External Interrupt Control Register Flash Control/Status Register Watchdog Control Register System Integrity Control/Status Register 000x 000xb Reset Status 00h1) 00h1) 00h1) 00h1) 00h1) Remarks
Port
Port
Port
Port
Port
Port
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Address 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h
Block
Register Label MCCSR MCCBCR AWUCSR AWUPR WDGWR TACR2 TACR1 TACSR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR
Register Name Main Clock Control/Status Register Beep Control Register Control/Status Register Prescaler Register Window Watchdog Control Register Timer Control Register Timer Control Register Timer Control/Status Register Timer Input Capture High Register Timer Input Capture Register Timer Output Compare High Register Timer Output Compare Register Timer Counter High Register Timer Counter Register Timer Alternate Counter High Register Timer Alternate Counter Register Timer Input Capture High Register Timer Input Capture Register Timer Output Compare High Register Timer Output Compare Register Reserved Area Byte)
Reset Status
Remarks Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only
WWDG
TIMER
TIMER
TBCR2 TBCR1 TBCSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCIETPR
Timer Control Register Timer Control Register Timer Control/Status Register Timer Input Capture High Register Timer Input Capture Register Timer Output Compare High Register Timer Output Compare Register Timer Counter High Register Timer Counter Register Timer Alternate Counter High Register Timer Alternate Counter Register Timer Input Capture High Register Timer Input Capture Register Timer Output Compare High Register Timer Output Compare Register Status Register Data Register Baud Rate Register Control Register Control Register Reserved area Extended Receive Prescaler Register Extended Transmit Prescaler Register
x000 0000b -00h
Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only
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Address 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 0070h 0071h 0072h 0073h 007Fh
Block
Register Label I2CCR I2CSR1 I2CSR2 I2CCCR I2COAR1 I2COAR2 I2CDR
Register Name Control Register Status Register Status Register Clock Control Register Address Register Address Register2 Data Register Reserved area byte)
Reset Status
Remarks Read Only Read Only
I2C3SNS
I2C3SCR1 I2C3SCR2 I2C3SSR I2C3SBCR I2C3SSAR1 I2C3SCAR1 I2C3SSAR2 I2C3SCAR2 I2C3SSAR3 I2C3SCAR3 ADCCSR ADCDRH ADCDRL
I2C3SNS Control Register I2C3SNS Control Register I2C3SNS Status Register I2C3SNS Byte Count Register I2C3SNS Slave Address Register I2C3SNS Current Address Register I2C3SNS Slave Address Register I2C3SNS Current Address Register I2C3SNS Slave Address Register I2C3SNS Current Address Register Control Status Register Data Register High Data Register Reserved area bytes)
0000 00xxb
Read Only Read Only Read Only Read Only
Legend: x=undefined, R/W=read/write Notes: contents port registers readable only output configuration. input configuration, values pins returned instead register contents. bits associated with unavailable pins must always keep their reset value. description Debug Module registers, reference manual.
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FLASH PROGRAM MEMORY
Introduction single voltage extended Flash (XFlash) non-volatile memory that electrically erased programmed either byte-by-byte basis bytes parallel. XFlash devices programmed off-board (plugged programming tool) on-board using In-Circuit Programming In-Application Programming. array matrix organisation allows each sector erased reprogrammed without affecting other sectors. Main Features
(In-Circuit Programming) (In-Application Programming) (In-Circuit Testing) downloading executing user application test patterns Sector size configurable option byte Read-out write protection
PROGRAMMING MODES programmed three different ways: Insertion programming tool. this mode, FLASH sectors option byte data EEPROM present) programmed erased. In-Circuit Programming. this mode, FLASH sectors option byte data EEPROM present) programmed erased without removing device from application board. In-Application Programming. this mode, sector data EEPROM present) programmed erased without removing
device from application board while application running. 4.3.1 In-Circuit Programming (ICP) uses protocol called (In-Circuit Communication) which allows plugged printed circuit board (PCB) communicate with external programming device connected cable. performed three steps: Switch mode (In-Circuit Communications). This done driving specific signal sequence ICCCLK/DATA pins while RESET pulled low. When enters mode, fetches specific RESET vector which points System Memory containing protocol routine. This routine enables receive bytes from interface. Download Driver code from ICCDATA Execute Driver code program FLASH memory Depending Driver code downloaded RAM, FLASH memory programming fully customized (number bytes program, program locations, selection serial communication interface downloading). 4.3.2 Application Programming (IAP) This mode uses Driver program previously programmed Sector user mode). This mode fully controlled user software. This allows adapted user application, (user-defined strategy entering programming mode, choice communications protocol used fetch data stored etc.) mode used program memory areas except Sector which write/erase protected allow recovery case errors occur during programming operation.
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FLASH PROGRAM MEMORY (Cont'd) interface needs minimum pins connected programming tool. These pins are: RESET: device reset VSS: device power supply ground ICCCLK: output serial clock ICCDATA: input serial data ICCSEL: selection OSC1: main clock input external source (not required devices without OSC1/OSC2 pins) VDD: application board power supply (optional, Note Notes: ICCCLK ICCDATA pins only used outputs application, signal isolation necessary. soon Programming Tool plugged board, even session progress, ICCCLK ICCDATA pins available application. they used inputs application, isolation such serial resistor implemented case another device forces signal. Refer Programming Tool documentation recommended resistor values. Figure Typical Interface
PROGRAMMING TOOL CONNECTOR Cable CONNECTOR HE10 CONNECTOR TYPE OPTIONAL (See Note APPLICATION BOARD
During session, programming tool must control RESET pin. This lead conflicts between programming tool application reset circuit drives more than high level (push pull output pull-up resistor<1K). schottky diode used isolate application RESET circuit this case. When using classical network with R>1K reset management with open drain output pull-up resistor>1K, additional components needed. cases user must ensure that external reset generated application during session. connector depends Programming Tool architecture. This must connected when using most Programming Tools used monitor application power supply). Please refer Programming Tool manual. connected OSC1 when clock available application selected clock option programmed option byte. devices with multi-oscillator capability need have OSC2 grounded this case.
(See Note
APPLICATION RESET SOURCE Note APPLICATION POWER SUPPLY Note APPLICATION
RESET
ICCCLK
ICCSEL
ICCDATA
OSC2
OSC1
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FLASH PROGRAM MEMORY (Cont'd) Memory Protection There different types memory protection: Read Protection Write/Erase Protection which applied individually. 4.5.1 Read Protection Readout protection, when selected provides protection against program memory content extraction against write access Flash memory. Even protection considered totally unbreakable, feature provides very high level protection general purpose microcontroller.Both program data memory protected. flash devices, this protection removed reprogramming option. this case, both program data memory automatically erased, device reprogrammed. Read-out protection selection depends device type: Flash devices enabled removed through FMP_R option byte. devices enabled mask option specified Option List. 4.5.2 Flash Write/Erase Protection Write/erase protection, when set, makes impossible both overwrite erase program memory. does apply data. purpose provide advanced security applications prevent change being made memory content. Warning: Once set, Write/erase protection never removed. write-protected flash device longer reprogrammable. Write/erase protection enabled through FMP_W option byte. Register Description FLASH CONTROL/STATUS REGISTER (FCSR) Read/Write Reset Value: 0000 (00h) RASS Key: 0101 0110 (56h) RASS Key: 1010 1110 (AEh)
Note: This register reserved programming using ICP, other programming methods. controls XFlash programming erasing operations. details XFlash programming, refer Flash Programming Reference Manual. When another programming tool used socket mode), RASS keys sent automatically.
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DATA EEPROM
INTRODUCTION Electrically Erasable Programmable Read Only Memory used volatile backup storing data. Using EEPROM requires basic access protocol described this chapter. MAIN FEATURES
Bytes programmed same cycle EEPROM mono-voltage (charge pump) Chained erase programming cycles Internal control global programming cycle duration WAIT mode management Readout protection
Figure EEPROM Block Diagram
HIGH VOLTAGE PUMP
EECSR
E2LAT E2PGM
ADDRESS DECODER
DECODER
EEPROM MEMORY MATRIX BITS)
DATA MULTIPLEXER
BITS DATA LATCHES
ADDRESS
DATA
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DATA EEPROM (Cont'd) MEMORY ACCESS Data EEPROM memory read/write access modes controlled E2LAT EEPROM Control/Status register (EECSR). flowchart Figure describes these different memory access modes. Read Operation (E2LAT=0) EEPROM read normal location when E2LAT EECSR register cleared. this device, Data EEPROM also used execute machine code. Take care write Data EEPROM while executing from This would result unexpected code being executed. Write Operation (E2LAT=1) access write mode, E2LAT software (the E2PGM remains cleared). When write access EEPROM area occurs, Figure Data EEPROM Programming Flowchart value latched inside data latches according address. When software, previous bytes written data latches programmed EEPROM cells. effective high address (row) determined last EEPROM write sequence. avoid wrong programming, user must take care that bytes written between programming sequences have same high address: only five Least Significant Bits address change. programming cycle, bits cleared simultaneously. Note: Care should taken during programming cycle. Writing same memory location will over-program memory (logical between write access data result) because data latches only cleared programming cycle falling edge E2LAT bit. possible read latched data. This note ilustrated Figure
READ MODE E2LAT=0 E2PGM=0
WRITE MODE E2LAT=1 E2PGM=0
READ BYTES EEPROM AREA
WRITE BYTES EEPROM AREA (with same address)
START PROGRAMMING CYCLE E2LAT=1 E2PGM=1 (set software)
CLEARED HARDWARE
E2LAT
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DATA EEPROM (Cont'd) Figure Data E2PROM Write Operation
Byte DEFINITION Read operation impossible Physical Address
00h.1Fh 20h.3Fh Nx20h.Nx20h+1Fh
Read operation possible
Byte
Byte PHASE
Byte
Programming cycle PHASE
Writing data latches E2LAT
USER application
Waiting E2PGM E2LAT fall
Cleared hardware
E2PGM
Note: programming cycle interrupted reset action), integrity data memory guaranteed.
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DATA EEPROM (Cont'd) POWER SAVING MODES Wait mode DATA EEPROM enter WAIT mode execution instruction microcontroller when microcontroller enters Active-HALT mode.The DATA EEPROM will immediately enter this mode there programming progress, otherwise DATA EEPROM will finish cycle then enter WAIT mode. Active-Halt mode Refer Wait mode. Halt mode DATA EEPROM immediately enters HALT mode microcontroller executes HALT instruction. Therefore EEPROM will stop function progress, data corrupted. ACCESS ERROR HANDLING read access occurs while E2LAT=1, then data will driven. write access occurs while E2LAT=0, then data will latched. programming cycle interrupted RESET action), memory data will guaranteed. DATA EEPROM READ-OUT PROTECTION read-out protection enabled through option (see option byte section). When this option selected, programs data stored EEPROM memory protected against read-out (including re-write protection). Flash devices, when this protection removed reprogramming Option Byte, entire Program memory EEPROM first automatically erased. Note: Both Program Memory data EEPROM protected using same option bit.
Figure Data EEPROM Programming Cycle
READ OPERATION POSSIBLE INTERNAL PROGRAMMING VOLTAGE ERASE CYCLE WRITE DATA LATCHES WRITE CYCLE READ OPERATION POSSIBLE
tPROG
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DATA EEPROM (Cont'd) REGISTER DESCRIPTION EEPROM CONTROL/STATUS REGISTER (EECSR) Read/Write Reset Value: 0000 0000 (00h)
E2LAT E2PGM
Bits Reserved, forced hardware E2LAT Latch Access Transfer This software. cleared hardware programming cycle. only cleared software E2PGM cleared. Read mode Write mode E2PGM Programming control status This software begin programming cycle. programming cycle, this cleared hardware. Programming finished started Programming cycle progress Note: E2PGM cleared during programming cycle, memory data guaranteed
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DATA EEPROM (Cont'd) Table DATA EEPROM Register Reset Values
Address (Hex.) 0020h Register Label EECSR Reset Value E2LAT E2PGM
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CENTRAL PROCESSING UNIT
INTRODUCTION This full 8-bit architecture contains internal registers allowing efficient 8-bit data manipulation. MAIN FEATURES
REGISTERS registers shown Figure present memory mapping accessed specific instructions. Accumulator Accumulator 8-bit general purpose register used hold operands results arithmetic logic calculations manipulate data. Index Registers These 8-bit registers used create effective addresses temporary storage areas data manipulation. (The Cross-Assembler generates precede instruction (PRE) indicate that following instruction refers register.) register affected interrupt automatic procedures. Program Counter (PC) program counter 16-bit register containing address next instruction executed CPU. made 8-bit registers (Program Counter which LSB) (Program Counter High which MSB).
Enable executing basic instructions Fast 8-bit 8-bit multiply main addressing modes (with indirect addressing mode) 8-bit index registers 16-bit stack pointer power HALT WAIT modes Priority maskable hardware interrupts Non-maskable software/hardware interrupts
Figure Registers
RESET VALUE RESET VALUE RESET VALUE PROGRAM COUNTER RESET VALUE RESET VECTOR FFFEh-FFFFh CONDITION CODE REGISTER RESET VALUE STACK POINTER RESET VALUE STACK HIGHER ADDRESS Undefined Value INDEX REGISTER INDEX REGISTER ACCUMULATOR
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CENTRAL PROCESSING UNIT (Cont'd) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx
This cleared hardware. This indicates that result last arithmetic, logical data manipulation zero. result last operation different from zero. result last operation zero. This accessed JREQ JRNE test instructions. Carry/borrow. This cleared hardware software. indicates overflow underflow occurred during last arithmetic operation. overflow underflow occurred. overflow underflow occurred. This driven instructions tested JRNC instructions. also affected "bit test branch", shift rotate instructions. Interrupt Management Bits Interrupt combination bits gives current interrupt software priority.
Interrupt Software Priority Level (main) Level Level Level interrupt disable)
8-bit Condition Code register contains interrupt masks four flags representative result instruction just executed. This register also handled PUSH instructions. These bits individually tested and/or controlled specific instructions. Arithmetic Management Bits Half carry. This hardware when carry occurs between bits during instructions. reset hardware during same instructions. half carry occurred. half carry occurred. This tested using JRNH instruction. useful arithmetic subroutines. Negative. This cleared hardware. representative result sign last arithmetic, logical data manipulation. It's copy result bit. result last operation positive null. result last operation negative (i.e. most significant logic This accessed JRMI JRPL instructions. Zero.
These bits set/cleared hardware when entering interrupt. loaded value given corresponding bits interrupt software priority registers (IxSPR). They also set/ cleared software with RIM, SIM, IRET, HALT, PUSH/POP instructions. interrupt management chapter more details.
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CENTRAL PROCESSING UNIT (Cont'd) Stack Pointer (SP) Read/Write Reset Value:
Stack Pointer 16-bit register which always pointing next free location stack. then decremented after data been pushed onto stack incremented before data popped from stack (see Figure 14). Since stack bytes deep, most significant bits forced hardware. Following Reset, after Reset Stack Pointer instruction (RSP), Stack Pointer contains reset value (the bits set) which stack higher address. Figure Stack Manipulation Example
CALL Subroutine 0100h Interrupt Event PUSH
least significant byte Stack Pointer (called directly accessed instruction. Note: When lower limit exceeded, Stack Pointer wraps around stack upper limit, without indicating stack overflow. previously stored information then overwritten therefore lost. stack also wraps case underflow. stack used save return address during subroutine call context during interrupt. user also directly manipulate stack means PUSH instructions. case interrupt, stored first location pointed Then other registers stored next locations shown Figure When interrupt received, decremented context pushed stack. return from interrupt, incremented context popped from stack. subroutine call occupies locations interrupt five locations stack area.
IRET
01FFh
Stack Higher Address 01FFh Stack Lower Address 0100h
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SUPPLY, RESET CLOCK MANAGEMENT
device includes range utility features securing application critical situations (for example case power brown-out), reducing number external components.
External Clock Input (enabled option byte) multiplying frequency (enabled option byte) Reset Sequence Manager (RSM) System Integrity Management (SI) Main supply voltage detection (LVD) with reset generation (enabled option byte) Power Down Voltage Detector (PDVD) with interrupt capability monitoring main supply (enabled option byte)
Main features
Clock Management high-accuracy internal oscillator (enabled option byte) External crystal/ceramic resonator (enabled option byte)
Figure Clock, Reset Supply Block Diagram
RCCRH/RCCRL Register MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK(MCC/RTC) fCPU
Tunable Oscillator 1MHz DIVIDER 1MHz 8MHz 1MHz 4MHz 4MHz Option
8MHz
External Clock (0.5-8MHz) Clock (1MHz.) fOSC2 DIVIDER* Clock 8/4MHz
PLLx4x8 Option
DIV2EN Option bit* Crystal (0.5-8MHz)
OSC1 OSC2
1-16
OSC, PLLOFF OSCRANGE[2:0] Option bits
DIVIDER
*not available PLLx4 enabled
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PHASE LOCKED LOOP used multiply 1MHz frequency from oscillator external clock obtain fOSC MHz. enabled multiplication factor selected option bits. Refer Table configuration depending required frequency application voltage. Refer Section 15.1 option byte description. Table Configurations
Target Ratio x41)
When started, after reset wakeup from Halt mode AWUFH mode, outputs clock after delay tSTARTUP. When output signal reaches operating frequency, LOCKED SICSCR register set. Full accuracy (ACCPLL) reached after stabilization time tSTAB (see Figure Refer Section 7.5.4 page description LOCKED SICSR register. Caution: recommended applications where timing accuracy required.
2.7V 3.65V 3.3V 5.5V
Ratio
DIV2
target ratio between 3.3V 3.65V, this recommended configuration. Figure Output Frequency Timing Diagram LOCKED input freq. tSTAB Output freq. tLOCK tSTARTUP
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MULTI-OSCILLATOR (MO) main clock generated three different source types coming from multioscillator block: external source crystal ceramic resonator oscillators internal high-accuracy oscillator Each oscillator optimized given frequency range terms consumption selectable through option byte. associated hardware configurations shown Table Refer electrical characteristics section more details. Caution: OSC1 and/or OSC2 pins must left unconnected. purposes Failure Mode Effect Analysis, should noted that OSC1 and/or OSC2 pins left unconnected, main oscillator start and, this configuration, could generate fOSC clock frequency excess allowed maximum (>16MHz.), putting unsafe/undefined state. product behaviour must therefore considered undefined when pins left unconnected. External Clock Source this external clock mode, clock signal (square, sinus triangle) with ~50% duty cycle drive OSC1 while OSC2 tied ground. Crystal/Ceramic Oscillators This family oscillators advantage producing very accurate rate main clock ST7. selection within list oscillators with different frequency ranges done option byte order reduce consumption (refer Section 15.1 page more details frequency ranges). this mode multioscillator, resonator load capacitors have placed close possible oscillator pins order minimize output distortion start-up stabilization time. loading capacitance values must adjusted according selected oscillator. These oscillators stopped during RESET phase avoid losing time oscillator start-up phase. Table Clock Sources
Hardware Configuration
External Clock
OSC1 OSC2
EXTERNAL SOURCE
Crystal/Ceramic Resonators
OSC1 OSC2
LOAD CAPACITORS
Internal Oscillator
OSC1 OSC2
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MULTI-OSCILLATOR (Cont'd) Internal Oscillator device contains high-precision internal oscillator. must calibrated obtain frequency required application. This done software writing calibration value RCCRH RCCRL Registers. Whenever microcontroller reset, RCCR returns default value 03h), i.e. each time device reset, calibration value must loaded RCCRH RCCRL registers. Predefined calibration values stored XFLASH supply voltages 25°C, shown following table.
RCCR RCCR0 Conditions VDD=5V TA=25°C fRC=1MHz VDD=3V TA=25°C fRC=700KHz Address BEE0, BEE1
REGISTER DESCRIPTION CONTROL REGISTER (RCCRH) Read Write Reset Value: 1111 1111 (FFh)
Bits CR[9:2] Oscillator Frequency Adjustment Bits CONTROL REGISTER (RCCRL) Read Write Reset Value: 0000 0011 (03h)
RCCR1
BEE4, BEE5
Note: improve clock stability, recommended place decoupling capacitor between pins. These 10-bit values systematically programmed including FASTROM devices. Consequently, customers intending FASTROM service must these addresses. RCCR0 RCCR1 calibration values will erased read-out protection reset after been set. "Memory Protection" page Caution: voltage temperature conditions change application, frequency need recalibrated. Refer application note AN1324 information calibrate frequency using external reference signal.
Bits Reserved, must kept cleared. Bits CR[1:0] Oscillator Frequency Adjustment Bits This 10-bit value must written immediately after reset adjust oscillator frequency order obtain specified accuracy. application store correct value each voltage range EEPROM write this register start-up. 0000h maximum available frequency 03FFh lowest available frequency Note: tune oscillator, write series different values register until correct frequency reached. fastest method dichotomy starting with 200h.
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RESET SEQUENCE MANAGER (RSM) 7.4.1 Introduction reset sequence manager includes three RESET sources shown Figure External RESET source pulse Internal RESET (Low Voltage Detection) Internal WATCHDOG RESET Note: reset also triggered following detection illegal opcode prebyte code. Refer Section 12.2.1 page further details. These sources RESET always kept during delay phase. RESET service routine vector fixed addresses FFFEh-FFFFh memory map. basic RESET sequence consists phases shown Figure Active Phase depending RESET source 4096 clock cycle delay (selected option byte) RESET vector fetch 4096 clock cycle delay allows oscillator stabilise ensures that recovery taken place from Reset state. shorter longer clock cycle delay should selected option byte correspond stabilization time Figure Reset Block Diagram external oscillator used application (see Section 15.1 page 182). RESET vector fetch phase duration clock cycles. Figure RESET Sequence Phases
RESET
Active Phase INTERNAL RESET 4096 CLOCK CYCLES FETCH VECTOR
7.4.2 Asynchronous External RESET RESET both input open-drain output with integrated weak pull-up resistor. This pull-up fixed value varies accordance with input voltage. pulled external circuitry reset device. "ELECTRICAL CHARACTERISTICS" page more details. RESET signal originating from external source must have duration least th(RSTL)in order recognized (see Figure 19). This detection asynchronous therefore enter reset state even HALT mode.
RESET
Filter INTERNAL RESET
PULSE GENERATOR
WATCHDOG RESET ILLEGAL OPCODE RESET RESET
Note "Illegal Opcode Reset" page 150. more details illegal opcode reset conditions.
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RESET SEQUENCE MANAGER (Cont'd) RESET asynchronous signal which plays major role performance. noisy environment, recommended follow guidelines mentioned electrical characteristics section. external RESET pulse shorter than tw(RSTL)out (see short ext. Reset Figure 19), signal RESET stretched. Otherwise delay will applied (see long ext. Reset Figure 19). Starting from external RESET pulse recognition, device RESET acts output that pulled during least tw(RSTL)out. 7.4.3 External Power-On RESET disabled option byte, start microcontroller correctly, user must ensure means external reset circuit that reset signal held until over minimum level specified selected fOSC frequency. (see "OPERATING CONDITIONS" page 155) proper reset signal slow rising supply generally provided external network connected RESET pin. Figure RESET Sequences
VIT+(LVD) VIT-(LVD)
7.4.4 Internal Voltage Detector (LVD) RESET different RESET sequences caused internal circuitry distinguished: Power-On RESET Voltage Drop RESET device RESET acts output that pulled when VDD<VIT+ (rising edge) VDD<VIT- (falling edge) shown Figure filters spikes larger than tg(VDD) avoid parasitic resets. Note: recommended make sure that supply voltage rises monotonously when device exiting from Reset, ensure application functions properly. 7.4.5 Internal Watchdog RESET RESET sequence generated internal Watchdog counter overflow shown Figure Starting from Watchdog counter underflow, device RESET acts output that pulled during least tw(RSTL)out.
RESET
SHORT EXT. RESET
LONG EXT. RESET
WATCHDOG RESET
ACTIVE PHASE
ACTIVE PHASE
ACTIVE PHASE
ACTIVE PHASE
tw(RSTL)out th(RSTL)in
EXTERNAL RESET SOURCE
tw(RSTL)out th(RSTL)in
DELAY
tw(RSTL)out
RESET
WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (256 4096 TCPU) VECTOR FETCH
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SYSTEM INTEGRITY MANAGEMENT (SI) System Integrity Management block contains Voltage Detector (LVD) Power Down Voltage Detector (PDVD) functions. managed SICSR register. Note: reset also triggered following detection illegal opcode prebyte code. Refer Section 12.2.1 page further details. 7.5.1 Voltage Detector (LVD) Voltage Detector function (LVD) generates static reset when supply voltage below VIT- reference value. This means that secures power-up well power-down keeping reset. VIT- reference value voltage drop lower than VIT+ reference value power-on order avoid parasitic reset when starts running sinks current supply (hysteresis). Reset circuitry generates reset when below: VIT+ when rising VIT- when falling function illustrated Figure optional function which selected option byte. Note: Threshold Configuration voltage threshold configured option byte low, medium high. configuration should chosen depending fOSC parameters application. When correctly configured, ensures safe power-on power-off conditions microcontroller without using external components. determine which thresholds use: Define minimum operating voltage application VAPP(min) Refer Electrical Characteristics section minimum operating voltage application frequency VDD(min) Select threshold that ensures that internal RESET released VAPP(min) activated VDD(MCUmin) During Voltage Detector Reset, RESET held low, thus permitting reset other devices.
Figure Voltage Detector Reset
Vhys VIT+(LVD) VIT-((LVD)
RESET
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 7.5.2 Power Down Voltage Detector (PDVD) PDVD used provide application with early warning drop voltage. enabled, interrupt generated allowing software shut down safely before resets microcontroller. Figure PDVD function active only enabled through option byte (see Section 15.1 page 182). activation level PDVD fixed around above selected threshold. Figure Using PDVD Monitor Early Warning Interrupt (Power dropped, reset)
Vhys VIT+(PDVD) VIT-(PDVD)
case drop voltage below VIT-(PVD), PDVDF flag interrupt request issued. rises above VIT+(PDVD) threshold voltage PDVDF cleared automatically hardware. interrupt generated, therefore software should poll PDVDF detect when voltage risen, resume normal processing.
VIT-(LVD)
PDVDF PDVD INTERRUPT REQUEST PDVDIE
RESET VALUE
INTERRUPT PROCESS
RESET
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 7.5.3 Power Modes
Mode WAIT HALT Description effect PDVD interrupts cause device exit from Wait mode. SICSR register frozen.
7.5.3.1 Interrupts PDVD interrupt event generates interrupt corresponding PDVDIE interrupt mask register reset (RIM instruction).
Interrupt Event PDVD event Enable Event Control Flag PDVDF PDVDIE Exit from Wait Exit from Halt
LVDRF reset flag This indicates that last Reset generated block. hardware (LVD reset) cleared software (writing zero). WDGRF flag description more details. When disabled OPTION BYTE, LVDRF value undefined. LOCKED Locked Flag This cleared hardware. automatically when reaches operating frequency. locked locked Bits Reserved, must kept cleared. WDGRF Watchdog reset flag This indicates that last Reset generated Watchdog peripheral. hardware (watchdog reset) cleared software (writing zero) Reset ensure stable cleared state WDGRF flag when starts). Combined with LVDRF flag information, flag description given following table.
RESET Sources External RESET Watchdog LVDRF WDGRF
7.5.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write Reset Value: 000x 000x (xxh)
PDVD PDVDF
Reserved, must kept cleared. PDVDIE Voltage Detector interrupt enable This cleared software. enables interrupt generated when PDVDF flag goes from pending interrupt information automatically cleared when software enters PDVD interrupt routine. PDVD interrupt disabled PDVD interrupt enabled PDVDF Voltage Detector flag This read-only cleared hardware. PDVDIE set, interrupt request generated when PDVDF goes from Refer Figure Section 7.5.2 additional details. over VIT+(PDVD) threshold under VIT-(PDVD) threshold
Application notes LVDRF flag cleared when another RESET type occurs (external watchdog), LVDRF flag remains keep trace original failure. this case, watchdog reset detected software while external reset not. CAUTION: When activated with associated option byte, WDGRF flag used application.
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INTERRUPTS
INTRODUCTION enhanced interrupt management provides following features: Hardware interrupts Software interrupt (TRAP) Nested concurrent interrupt management with flexible interrupt priority level management: software programmable nesting levels interrupt vectors fixed hardware maskable events: RESET, TRAP This interrupt management based register (I1:0), Interrupt software priority registers (ISPRx), Fixed interrupt vector addresses located high addresses memory (FFE0h FFFFh) sorted hardware priority order. This enhanced interrupt controller guarantees full upward compatibility with standard (not nested) interrupt controller. MASKING PROCESSING FLOW interrupt masking managed bits register ISPRx registers which give interrupt software priority level each interrupt vector (see Table processing flow shown Figure Figure Interrupt Processing Flowchart
RESET PENDING INTERRUPT TRAP Interrupt same lower software priority than current I1:0 Interrupt higher software priority than current
When interrupt request serviced: Normal processing suspended current instruction execution. registers saved onto stack. bits register according corresponding values ISPRx registers serviced interrupt vector. then loaded with interrupt vector interrupt service first instruction interrupt service routine fetched (refer "Interrupt Mapping" table vector addresses). interrupt service routine should with IRET instruction which causes contents saved registers recovered from stack. Note: consequence IRET instruction, bits will restored from stack program previous level will resume. Table Interrupt Software Priority Levels
Interrupt software priority Level (main) Level Level Level interrupt disable) Level
High
FETCH NEXT INSTRUCTION
INTERRUPT STAYS PENDING
"IRET"
RESTORE FROM STACK
EXECUTE INSTRUCTION
STACK LOAD I1:0 FROM INTERRUPT REG. LOAD FROM INTERRUPT VECTOR
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INTERRUPTS (Cont'd) Servicing Pending Interrupts several interrupts pending same time, interrupt taken into account determined following two-step process: highest software priority interrupt serviced, several interrupts have same software priority then interrupt with highest hardware priority serviced first. Figure describes this decision process. Figure Priority Decision Process
PENDING INTERRUPTS
registers (except RESET), corresponding vector loaded register bits disable interrupts (level These sources allow processor exit HALT mode. TRAP (Non Maskable Software Interrupt) This software interrupt serviced when TRAP instruction executed. will serviced according flowchart Figure RESET RESET source highest priority ST7. This means that first current routine highest software priority (level highest hardware priority. RESET chapter more details. Maskable Sources Maskable interrupt vector sources serviced corresponding interrupt enabled interrupt software priority ISPRx registers) higher than currently being serviced register). these conditions false, interrupt latched thus remains pending. External Interrupts External interrupts allow processor exit from HALT power mode. External interrupt sensitivity software selectable through External Interrupt Control register (EICR). External interrupt triggered edge will latched interrupt request automatically cleared upon entering interrupt service routine. several input pins group connected same interrupt line selected simultaneously, these will logically ORed. Peripheral Interrupts Usually peripheral interrupts cause exit from HALT mode except those mentioned "Interrupt Mapping" table. peripheral interrupt occurs when specific flag peripheral status registers corresponding enable peripheral control register. general sequence clearing interrupt based access status register followed read write associated register. Note: clearing sequence resets internal latch. pending interrupt (i.e. waiting being serviced) will therefore lost clear sequence executed.
Same
SOFTWARE PRIORITY
Different
HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED
When interrupt request serviced immediately, latched then processed when software priority combined with hardware priority becomes highest one. Notes: hardware priority exclusive while software not. This allows previous process succeed with only interrupt. TLI, RESET TRAP considered having highest software priority decision process. Different Interrupt Vector Sources interrupt source types managed interrupt controller: non-maskable type (RESET, TRAP) maskable type (external from internal peripherals). Non-Maskable Sources These sources processed regardless state bits register (see Figure 22). After stacking
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INTERRUPTS (Cont'd) INTERRUPTS POWER MODES interrupts allow processor exit WAIT power mode. contrary, only external other specified interrupts allow processor exit from HALT modes (see column "Exit from HALT" "Interrupt Mapping" table). When several pending interrupts present while exiting HALT mode, first serviced only interrupt with exit from HALT mode capability selected through same decision process shown Figure Note: interrupt, that able Exit from HALT mode, pending with highest priority when exiting HALT mode, this interrupt serviced after first serviced. Figure Concurrent Interrupt Management
TRAP SOFTWARE PRIORITY LEVEL
CONCURRENT NESTED MANAGEMENT following Figure Figure show different interrupt management modes. first called concurrent mode does allow interrupt interrupted, unlike nested mode Figure interrupt hardware priority given this order from lowest highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. software priority given each interrupt. Warning: stack overflow occur without notifying software failure.
HARDWARE PRIORITY
TRAP MAIN MAIN
Figure Nested Interrupt Management
TRAP
SOFTWARE PRIORITY LEVEL
HARDWARE PRIORITY
TRAP MAIN MAIN
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USED STACK BYTES
USED STACK BYTES
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INTERRUPTS (Cont'd) INTERRUPT REGISTER DESCRIPTION REGISTER INTERRUPT BITS Read/Write Reset Value: 111x 1010 (xAh)
ISPR0
INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX) Read/Write (bit ISPR3 read only) Reset Value: 1111 1111 (FFh)
I1_3 I1_7 I0_3 I0_7 I1_2 I1_6 I0_2 I0_6 I1_1 I1_5 I0_1 I0_5 I0_9 I1_0 I1_4 I1_8 I0_0 I0_4 I0_8
Software Interrupt Priority These bits indicate current interrupt software priority.
Interrupt Software Priority Level (main) Level Level Level interrupt disable*) Level
ISPR1 ISPR2 ISPR3
I1_11 I0_11 I1_10 I0_10 I1_9
I1_13 I0_13 I1_12 I0_12
High
These bits set/cleared hardware when entering interrupt. loaded value given corresponding bits interrupt software priority registers (ISPRx). They also set/cleared software with RIM, SIM, HALT, WFI, IRET PUSH/POP instructions (see "Interrupt Dedicated Instruction Set" table). *Note: TRAP RESET events interrupt level program.
These four registers contain interrupt software priority each interrupt vector. Each interrupt vector (except RESET TRAP) corresponding bits these registers where software priority stored. This correspondence shown following table.
Vector address FFFBh-FFFAh FFF9h-FFF8h FFE1h-FFE0h ISPRx bits I1_0 I0_0 bits* I1_1 I0_1 bits I1_13 I0_13 bits
Each I1_x I0_x value ISPRx registers same meaning bits register. Level written (I1_x=1, I0_x=0). this case, previously stored value kept. (example: previous=CFh, write=64h, result=44h) RESET, TRAP vectors have software priorities. When serviced, bits register both set. Caution: I1_x I0_x bits modified while interrupt executed following behaviour considered: interrupt still pending (new interrupt flag cleared) software priority higher than previous one, interrupt re-entered. Otherwise, software priority stays unchanged next interrupt request (after IRET interrupt
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INTERRUPTS (Cont'd) Table Dedicated Interrupt Instruction
Instruction HALT IRET JRNM TRAP Description Entering Halt mode Interrupt routine return Jump I1:0=11 (level Jump I1:0<>11 from Stack Enable interrupt (level set) Disable interrupt (level set) Software trap Wait interrupt I1:0=11 I1:0<>11 Load I1:0 Load I1:0 Software Function/Example
Note: During execution interrupt routine, HALT, POPCC, RIM, instructions change current software priority next IRET instruction previously mentioned instructions.
Table Interrupt Mapping
Source Block RESET TRAP/ICD MCC/RTC I2C3SNS I2C3SNS TIMER TIMER PDVD Reset Software Interrupt Auto Wake Interrupt Time base interrupt External Interrupt Port PA3, External Interrupt Port PF2:0 External Interrupt Port PB3:0 External Interrupt Port I2C3SNS Address Interrupt I2C3SNS Address Interrupt Peripheral Interrupts TIMER Peripheral Interrupts TIMER Peripheral Interrupts Peripheral Interrupt Power Down Voltage Detector Interrupt Peripheral Interrupt Description Register Label AWUCSR MCCSR I2C3SSR SPISR TASR TBSR SCISR SICSR I2CSRx Lowest Priority Priority Order Highest Priority Exit from HALT1 yes2 Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h
Notes: Valid HALT ACTIVE-HALT modes except MCC/RTC interrupt source which exits from ACTIVE-HALT mode only interrupt which exits from AWUFH mode only. Exit from HALT possible when slave mode.
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INTERRUPTS (Cont'd) EXTERNAL INTERRUPTS 8.6.1 Port Interrupt Sensitivity external interrupt sensitivity controlled IPA, ISxx bits EICR register (Figure 26). This control allows have fully independent external interrupt source sensitivities. Each external interrupt source generated four five) different events pin: Falling edge Rising edge Falling rising edge Figure External Interrupt Control bits
PORT INTERRUPTS PAOR.3 PADDR.3 CONTROL PORT [2:0] INTERRUPTS PFOR.2 PFDDR.2 EICR IS20 IS21 EICR IS20 IS21 INTERRUPT SOURCE
Falling edge level Rising edge high level (only ei2) guarantee correct functionality, sensitivity bits EICR register modified only when bits register both (level This means that interrupts must disabled before changing sensitivity. pending interrupts cleared writing different value ISx[1:0], bits EICR.
SENSITIVITY
SENSITIVITY CONTROL
INTERRUPT SOURCE
PORT [3:0] INTERRUPTS PBOR.3 PBDDR.3
EICR IS10 IS11
SENSITIVITY CONTROL
INTERRUPT SOURCE
PORT INTERRUPT PBOR.4 PBDDR.4
EICR IS10 IS11 INTERRUPT SOURCE
SENSITIVITY CONTROL
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INTERRUPTS (Cont'd) EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read/Write Reset Value: 0000 0000 (00h)
IS11 IS10 IS21 IS20
IS2[1:0] sensitivity interrupt sensitivity, defined using IS2[1:0] bits, applied following external interrupts: (port port
External Interrupt Sensitivity IS21 IS20 Falling edge level Rising edge only Falling edge only Rising edge high level Falling edge only Rising edge only
IS1[1:0] sensitivity interrupt sensitivity, defined using IS1[1:0] bits, applied following external interrupts: (port B3.0)
External Interrupt Sensitivity IS11 IS10 Falling edge level Rising edge only Falling edge only Rising edge high level Falling edge only Rising edge only
Rising falling edge
(port F2.0)
IS21 IS20 External Interrupt Sensitivity Falling edge level Rising edge only Falling edge only Rising falling edge
Rising falling edge
(port
IS11 IS10 External Interrupt Sensitivity Falling edge level Rising edge only Falling edge only Rising falling edge
These bits written only when register both (level Interrupt polarity ports This used invert sensitivity port external interrupts. cleared software only when register both (level sensitivity inversion Sensitivity inversion Bits Reserved, must always kept cleared.
These bits written only when register both (level Interrupt polarity port This used invert sensitivity port [3:0] external interrupts. cleared software only when register both (level sensitivity inversion Sensitivity inversion
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INTERRUPTS (Cont'd) Table Nested Interrupts Register Reset Values
Address (Hex.) 0024h Register Label ISPR0 Reset Value ISPR1 Reset Value ISPR2 Reset Value ISPR3 Reset Value EICR Reset Value I1_0 I1_4 I1_8 I0_8 I0_4 I0_0
0025h
0026h
I1_3 I0_3 I2C3SNS I1_7 I0_7 I1_11 I0_11
I1_2 I0_2 I2C3SNS I1_6 I0_6 TIMER I1_10 I0_10
0027h 0028h
IS11
IS10
IS21
I1_1 I0_1 I1_5 I0_5 TIMER I1_9 I0_9 I1_13 I0_13 IS20
PDVD I1_12 I0_12
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POWER SAVING MODES
INTRODUCTION give large measure flexibility application terms power consumption, five main power saving modes implemented (see Figure 27): Slow Wait (and Slow-Wait) Active Halt Auto Wake From Halt (AWUFH) Halt After RESET normal operating mode selected default (RUN mode). This mode drives device (CPU embedded peripherals) means master clock which based main oscillator frequency divided multiplied (fOSC2). From mode, different power saving modes selected setting relevant register bits calling specific software instruction whose action depends oscillator status. Figure Power Saving Mode Transitions
fOSC2
SLOW MODE This mode targets: reduce power consumption decreasing internal clock device, adapt internal clock frequency (fCPU) available supply voltage. SLOW mode controlled three bits MCCSR register: which enables disables Slow mode bits which select internal slow frequency (fCPU). this mode, master clock frequency (fOSC2) divided peripherals clocked this lower frequency (fCPU). Note: SLOW-WAIT mode activated entering WAIT mode while device SLOW mode. Figure SLOW Mode Clock Transitions
fOSC2/2 fCPU fOSC2/4 fOSC2
MCCSR
High SLOW WAIT SLOW WAIT ACTIVE HALT AUTO WAKE FROM HALT HALT POWER CONSUMPTION
CP1:0
SLOW FREQUENCY REQUEST
NORMAL MODE REQUEST
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POWER SAVING MODES (Cont'd) WAIT MODE WAIT mode places power consumption mode stopping CPU. This power saving mode selected calling `WFI' instruction. peripherals remain active. During WAIT mode, I[1:0] bits register forced `10', enable interrupts. other registers memory remain unchanged. remains WAIT mode until interrupt RESET occurs, whereupon Program Counter branches starting address interrupt Reset service routine. will remain WAIT mode until Reset Interrupt occurs, causing wake Refer Figure Figure WAIT Mode Flow-chart
OSCILLATOR PERIPHERALS I[1:0] BITS
INSTRUCTION
RESET INTERRUPT OSCILLATOR PERIPHERALS I[1:0] BITS
4096 CLOCK CYCLE DELAY
OSCILLATOR PERIPHERALS I[1:0] BITS
FETCH RESET VECTOR SERVICE INTERRUPT
Note: Before servicing interrupt, register pushed stack. I[1:0] bits register current software priority level interrupt routine recovered when register popped.
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POWER SAVING MODES (Cont'd) HALT MODE HALT mode lowest power consumption mode MCU. entered executing `HALT' instruction when Main Clock Controller Status register (MCCSR) cleared (see Section 11.2 page more details MCCSR register) when AWUEN AWUCSR register cleared. exit HALT mode reception either specific interrupt (see Table "Interrupt Mapping," page RESET. When exiting HALT mode means RESET interrupt, oscillator immediately turned 4096 cycle delay used stabilize oscillator. After start delay, resumes operation servicing interrupt fetching reset vector which woke (see Figure 31). When entering HALT mode, I[1:0] bits register forced `10b'to enable interrupts. Therefore, interrupt pending, wakes immediately. HALT mode, main oscillator turned causing internal processing stopped, including operation on-chip peripherals. peripherals clocked except ones which their clock supply from another clock generator (such external auxiliary oscillator). compatibility Watchdog operation with HALT mode configured "WDGHALT" option option byte. HALT instruction when executed while Watchdog system enabled, generate Watchdog RESET (see Section 11.1 page more details). Figure HALT Timing Overview
HALT 4096 CYCLE DELAY RESET INTERRUPT FETCH VECTOR
Figure HALT Mode Flow-chart
HALT INSTRUCTION (MCCSR.OIE=0) (AWUCSR.AWUEN=0) ENABLE WDGHALT WATCHDOG RESET OSCILLATOR PERIPHERALS I[1:0] BITS WATCHDOG DISABLE
RESET INTERRUPT OSCILLATOR PERIPHERALS I[1:0] BITS 4096 CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS I[1:0] BITS FETCH RESET VECTOR SERVICE INTERRUPT
HALT INSTRUCTION [MCCSR.OIE=0]
Notes: WDGHALT option bit. option byte section more details. Peripheral clocked with external clock source still active. Only some specific interrupts exit from HALT mode (such external interrupt). Refer Table "Interrupt Mapping," page more details. Before servicing interrupt, register pushed stack. I[1:0] bits register current software priority level interrupt routine recovered when register popped.
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POWER SAVING MODES (Cont'd) Halt Mode Recommendations Make sure that external event available wake microcontroller from Halt mode. When using external interrupt wake microcontroller, reinitialize corresponding "Input Pull-up with Interrupt" before executing HALT instruction. main reason this that wrongly configured external interference unforeseen logical condition. same reason, reinitialize level sensitiveness each external interrupt precautionary measure. opcode HALT instruction 0x8E. avoid unexpected HALT instruction program counter failure, advised clear occurrences data value 0x8E from memory. example, avoid defining constant with value 0x8E. HALT instruction clears interrupt mask register allow interrupts, user choose clear pending interrupt bits before executing HALT instruction. This avoids entering other peripheral interrupt routines after executing external interrupt routine corresponding wake-up event (reset external interrupt). ACTIVE-HALT MODE ACTIVE-HALT mode lowest power consumption mode with real time clock available. entered executing `HALT' instruction when MCC/RTC interrupt enable flag (OIE MCCSR register) when AWUEN AWUCSR register cleared (See "Register Description" page 52.)
MCCSR Power Saving Mode entered when HALT instruction executed HALT mode ACTIVE-HALT mode
exit ACTIVE-HALT mode reception interrupt some specific interrupts (see Table "Interrupt Mapping," page RESET. When exiting ACTIVE-HALT mode means RESET 4096 cycle delay occurs (depending option byte). After start delay, resumes operation servicing interrupt fetching reset vector which woke (see Figure 33). When entering ACTIVE-HALT mode, I[1:0] bits register cleared enable interrupts. Therefore, interrupt pending, wakes immediately. ACTIVE-HALT mode, only main oscillator associated counter (MCC/RTC) running keep wake-up time base. other peripherals clocked except those which their clock supply from another clock generator (such external auxiliary oscillator). safeguard against staying locked ACTIVEHALT mode provided oscillator interrupt. Note: soon active halt enabled, executing HALT instruction while Watchdog active does generate RESET. This means that device cannot spend more than defined delay this power saving mode.
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POWER SAVING MODES (Cont'd) Figure ACTIVE-HALT Timing Overview
ACTIVE 4096 CYCLE HALT DELAY (AFTER RESET) RESET INTERRUPT
HALT INSTRUCTION (Active Halt enabled)
FETCH VECTOR
Figure ACTIVE-HALT Mode Flow-chart
HALT INSTRUCTION (MCCSR.OIE=1) (AWUCSR.AWUEN=0) OSCILLATOR PERIPHERALS I[1:0] BITS RESET INTERRUPT OSCILLATOR PERIPHERALS I[1:0] BITS 4096 CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS I[1:0] BITS FETCH RESET VECTOR SERVICE INTERRUPT
Notes: This delay occurs only exits ACTIVE-HALT mode means RESET. Peripheral clocked with external clock source still active. Only interrupt some specific interrupts exit from ACTIVE-HALT mode (such external interrupt). Refer Table "Interrupt Mapping," page more details. Before servicing interrupt, register pushed stack. I[1:0] bits register current software priority level interrupt routine restored when register popped.
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POWER SAVING MODES (Cont'd) AUTO WAKE FROM HALT MODE Auto Wake From Halt (AWUFH) mode similar Halt mode with addition internal oscillator wake-up. Compared ACTIVEHALT mode, AWUFH lower power consumption because main clock kept running, there accurate realtime clock available. entered executing HALT instruction when AWUEN AWUCSR register been MCCSR register cleared (see Section 11.2 page more details). Figure AWUFH Mode Block Diagram oscillator fAWU_RC Timer input capture After this start-up delay, resumes operation servicing AWUFH interrupt. flag associated interrupt cleared software reading AWUCSR register. compensate frequency dispersion oscillator, calibrated measuring clock frequency fAWU_RC then calculating right prescaler value. Measurement mode enabled setting AWUM AWUCSR register mode. This connects internally fAWU_RC ICAP2 input 16-bit timer allowing fAWU_RC measured using main oscillator clock reference timebase. Similarities with Halt mode following AWUFH mode behaviour same normal Halt mode: exit AWUFH mode means interrupt with exit from Halt capability reset (see Section "HALT MODE" page 47). When entering AWUFH mode, I[1:0] bits register forced enable interrupts. Therefore, interrupt pending, wakes immediately. AWUFH mode, main oscillator turned causing internal processing stopped, including operation on-chip peripherals. None peripherals clocked except those which their clock supply from another clock generator (such external auxiliary oscillator like oscillator). compatibility Watchdog operation with AWUFH mode configured WDGHALT option option byte. Depending this setting, HALT instruction when executed while Watchdog system enabled, generate Watchdog RESET.
divider
AWUFH prescaler
AWUFH interrupt
soon HALT mode entered, AWUEN been AWUCSR register, oscillator provides clock signal (fAWU_RC). frequency divided fixed divider programmable prescaler controlled AWUPR register. output this prescaler provides delay time. When delay elapsed AWUF flag hardware interrupt wakes-up from Halt mode. same time main oscillator immediately turned 4096 cycle delay used stabilize Figure AWUF Halt Timing Diagram tAWU MODE
fCPU fAWU_RC
HALT MODE
4096 tCPU
MODE
Clear software
AWUFH interrupt
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POWER SAVING MODES (Cont'd) Figure AWUFH Mode Flow-chart
HALT INSTRUCTION (MCCSR.OIE=0) (AWUCSR.AWUEN=1) ENABLE WDGHALT WATCHDOG RESET MAIN PERIPHERALS I[1:0] BITS WATCHDOG DISABLE
Notes: WDGHALT option bit. option byte section more details. Peripheral clocked with external clock source still active. Only AWUFH interrupt some specific interrupts exit from HALT mode (such external interrupt). Refer Table "Interrupt Mapping," page more details. Before servicing interrupt, register pushed stack. I[1:0] bits register current software priority level interrupt routine recovered when register popped.
RESET INTERRUPT MAIN PERIPHERALS I[1:0] BITS 4096 CLOCK CYCLE DELAY MAIN PERIPHERALS I[1:0] BITS FETCH RESET VECTOR SERVICE INTERRUPT
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POWER SAVING MODES (Cont'd) 9.6.0.1 Register Description AWUFH CONTROL/STATUS REGISTER (AWUCSR) Read/Write (except read only) Reset Value: 0000 0000 (00h)
AWUFH PRESCALER REGISTER (AWUPR) Read/Write Reset Value: 1111 1111 (FFh)
Bits Reserved. AWUF Auto Wake Flag This hardware when module generates interrupt cleared software reading AWUCSR. interrupt occurred interrupt occurred AWUM Auto Wake Measurement This enables oscillator connects internally output ICAP2 input 16bit timer This allows timer used measure oscillator dispersion then compensate this dispersion providing right value AWUPR register. Measurement disabled Measurement enabled AWUEN Auto Wake From Halt Enabled This enables Auto Wake From Halt feature: once HALT mode entered, AWUFH wakes microcontroller after time delay defined prescaler value. cleared software. AWUFH (Auto Wake From Halt) mode disabled AWUFH (Auto Wake From Halt) mode enabled Table Register Reset Values
Address (Hex.) 002Eh 002Fh Register Label
Bits 7:0= AWUPR[7:0] Auto Wake Prescaler These bits define AWUPR Dividing factor explained below:
AWUPR[7:0] Dividing factor Forbidden (See note)
mode, period that stays Halt Mode (tAWU Figure defined
AWUPR RCSTRT AWURC
This prescaler register programmed modify time that stays Halt mode before waking automatically. Note: written AWUPR, depending product, interrupt generated immediately after HALT instruction, AWUPR remains unchanged.
AWUCSR AWUF AWUM AWUEN Reset Value AWUPR AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0 Reset Value
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PORTS
10.1 INTRODUCTION ports offer different functional modes: transfer data through digital inputs outputs specific pins: external interrupt generation alternate signal input/output on-chip peripherals. port contains pins. Each programmed independently digital input (with without interrupt generation) digital output. 10.2 FUNCTIONAL DESCRIPTION Each port main registers: Data Register (DR) Data Direction Register (DDR) optional register: Option Register (OR) Each programmed using corresponding register bits registers: corresponding port. same correspondence used register. following description takes into account register, (for specific ports which provide this register refer Port Implementation section). generic block diagram shown Figure 10.2.1 Input Modes input configuration selected clearing corresponding register bit. this case, reading register returns digital value applied external pin. Different input modes selected software through register. Notes: Writing register modifies latch value does affect status. When switching from input output mode, register written first drive correct level soon port configured output. read/modify/write instructions (BSET BRES) modify register External interrupt function When configured Input with Interrupt, event this generate external interrupt request CPU. Each independently generate interrupt request. interrupt sensitivity independently programmable using sensitivity bits EICR register. Each external interrupt vector linked dedicated group port pins (see pinout description interrupt section). several input pins selected simultaneously interrupt sources, these first detected according sensitivity bits EICR register then logically ORed. external interrupts hardware interrupts, which means that request latch (not accessible directly application) automatically cleared when corresponding interrupt vector fetched. clear unwanted pending interrupt software, sensitivity bits EICR register must modified. 10.2.2 Output Modes output configuration selected setting corresponding register bit. this case, writing register applies this digital value through latch. Then reading register returns previously stored value. different output modes selected software through register: Output push-pull open-drain. register value output status:
Push-pull Open-drain Floating
10.2.3 Alternate Functions When on-chip peripheral configured pin, alternate function automatically selected. This alternate function takes priority over standard programming. When signal coming from on-chip peripheral, automatically configured output mode (push-pull open drain according peripheral). When signal going on-chip peripheral, must configured input mode. this case, state also digitally readable addressing register. Note: Input pull-up configuration cause unexpected value input alternate peripheral input. When on-chip peripheral input output, this configured input floating mode.
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PORTS (Cont'd) Figure Port General Block Diagram
REGISTER ACCESS ALTERNATE OUTPUT ALTERNATE ENABLE
P-BUFFER (see table below) PULL-UP (see table below)
PULL-UP CONDITION implemented N-BUFFER CMOS SCHMITT TRIGGER ANALOG INPUT DIODES (see table below)
EXTERNAL INTERRUPT SOURCE (eix)
Table Port Mode Options
Configuration Mode Input Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Pull-Up P-Buffer Diodes
Output
Legend: implemented implemented activated implemented activated
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DATA
ALTERNATE INPUT
(see note)
Note: diode implemented true open drain pads. local protection between implemented protect device against positive stress.
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PORTS (Cont'd) Table Port Configurations
Hardware Configuration
IMPLEMENTED TRUE OPEN DRAIN PORTS PULL-UP CONDITION REGISTER ACCESS
REGISTER
DATA
INPUT
ALTERNATE INPUT EXTERNAL INTERRUPT SOURCE (eix) INTERRUPT CONDITION ANALOG INPUT IMPLEMENTED TRUE OPEN DRAIN PORTS
OPEN-DRAIN OUTPUT
REGISTER ACCESS
REGISTER
DATA
ALTERNATE ENABLE
ALTERNATE OUTPUT
PUSH-PULL OUTPUT
IMPLEMENTED TRUE OPEN DRAIN PORTS
REGISTER ACCESS
REGISTER
DATA
ALTERNATE ENABLE
ALTERNATE OUTPUT
Notes: When port input configuration associated alternate function enabled output, reading register will read alternate function output status. When port output configuration associated alternate function enabled input, alternate function reads status given register content.
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PORTS (Cont'd) CAUTION: alternate function must activated long configured input with interrupt, order avoid generating spurious interrupts. Analog alternate function When used input, must configured floating input. analog multiplexer (controlled registers) switches analog voltage present selected common analog rail which connected input. recommended change voltage level loading port while conversion progress. Furthermore recommended have clocking pins located close selected analog pin. WARNING: analog input voltage level must within limits stated absolute maximum ratings. 10.3 PORT IMPLEMENTATION hardware implementation each port depends settings registers specific feature port such Input true open drain. Switching these ports from state another should done sequence that prevents unwanted side effects. Recommended safe transitions illustrated Figure Other transitions potentially risky should avoided, since they likely present unwanted side-effects such spurious interrupt generation.
Figure Interrupt Port State Transitions
INPUT floating/pull-up interrupt
INPUT floating (reset state)
OUTPUT open-drain
OUTPUT push-pull
DDR,
10.4 POWER MODES
Mode WAIT HALT Description effect ports. External interrupts cause device exit from WAIT mode. effect ports. External interrupts cause device exit from HALT mode.
10.5 INTERRUPTS external interrupt event generates interrupt corresponding configuration selected with registers interrupt mask register active (RIM instruction).
Interrupt Event External interrupt selected external event Enable Event Control Flag DDRx Exit from Wait Exit from Halt
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PORTS (Cont'd) 10.5.1 port implementation port register configurations summarised follows. Standard ports PA5:4, PC7:0, PD5:0, PE0, PF7:6,
MODE floating input pull-up input open drain output push-pull output
PA3, PE1, PB3, (without pull-up)
MODE floating input floating interrupt input open drain output push-pull output
True open drain ports PA7:6 PD7:6
MODE floating input open drain (high sink ports)
Interrupt ports PB4, PB2:0, PF1:0 (with pull-up)
MODE floating input pull-up interrupt input open drain output push-pull output
Table Port configuration
Port name
PA7:6 PA5:4 PB4, PB2:0 PC7:0 PD7:6 PD5:0 PF7:6, PF1:0
Input
floating floating floating floating floating floating floating floating floating floating floating floating pull-up floating interrupt floating interrupt pull-up interrupt pull-up floating pull-up floating interrupt pull-up pull-up floating interrupt pull-up interrupt
Output
true open-drain open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull true open-drain open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull
Port
Port Port Port Port
Port
CAUTION: small packages, internal pull-up applied permanently non-bonded pins. they have kept input floating configuration avoid unwanted consumption.
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PORTS (Cont'd) Table port register reset values
Address (Hex.) Register Label
Reset Value port registers 0000h PADR 0001h PADDR 0002h PAOR 0003h PBDR 0004h PBDDR 0005h PBOR 0006h PCDR 0007h PCDDR 0008h PCOR 0009h PDDR 000Ah PDDDR 000Bh PDOR 000Ch PEDR 000Dh PEDDR 000Eh PEOR 000Fh PFDR 0010h PFDDR 0011h PFOR
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ON-CHIP PERIPHERALS
11.1 WINDOW WATCHDOG (WWDG) 11.1.1 Introduction Window Watchdog used detect occurrence software fault, usually generated external interference unforeseen logical conditions, which causes application program abandon normal sequence. Watchdog circuit generates reset expiry programmed time period, unless program refreshes contents downcounter before becomes cleared. reset also generated 7-bit downcounter value control register) refreshed before downcounter reached window register value. This implies that counter must refreshed limited window. 11.1.2 Main Features Programmable free-running downcounter Conditional reset Reset watchdog activated) when downcounter value becomes less than Reset watchdog activated) downFigure Watchdog Block Diagram
RESET WATCHDOG WINDOW REGISTER (WDGWR)
counter reloaded outside window (see Figure Hardware/Software Watchdog activation (selectable option byte) Optional reset HALT instruction (configurable option byte) 11.1.3 Functional Description counter value stored WDGCR register (bits T[6:0]), decremented every 16384 fOSC2 cycles (approx.), length timeout period programmed user increments. watchdog activated (the WDGA set) when 7-bit downcounter (T[6:0] bits) rolls over from becomes cleared), initiates reset cycle pulling reset typically 30µs. software reloads counter while counter greater than value stored window register, then reset generated.
comparator when T6:0 W6:0 Write WDGCR WATCHDOG CONTROL REGISTER (WDGCR) WDGA
MCC/RTC fOSC2
6-BIT DOWNCOUNTER (CNT)
PRESCALER 12-BIT COUNTER
TB[1:0] bits (MCCSR Register)
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WINDOW WATCHDOG (Cont'd) application program must write WDGCR register regular intervals during normal operation prevent reset. This operation must occur only when counter value lower than window register value. value stored WDGCR register must between (see Figure 40): Enabling watchdog: When Software Watchdog selected option byte), watchdog disabled after reset. enabled setting WDGA WDGCR register, then cannot disabled again except reset. When Hardware Watchdog selected option byte), watchdog always active WDGA used. Controlling downcounter This downcounter free-running: counts down even watchdog disabled. When watchdog enabled, must prevent generating immediate reset. T[5:0] bits contain number increments which represents time delay before watchdog produces reset (see Figure Approximate Timeout Duration). timing varies
between minimum maximum value unknown status prescaler when writing WDGCR register (see Figure 41). window register (WDGWR) contains high limit window: prevent reset, downcounter must reloaded when value lower than window register value greater than 3Fh. Figure describes window watchdog process. Note: used generate software reset (the WDGA cleared). Watchdog Reset Halt option watchdog activated watchdog reset halt option selected, then HALT instruction will generate Reset. 11.1.4 Using Halt Mode with Halt mode with Watchdog enabled option byte watchdog reset HALT instruction), recommended before executing HALT instruction refresh counter, avoid unexpected reset immediately after waking microcontroller.
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WINDOW WATCHDOG (Cont'd) 11.1.5 Program Watchdog Timeout Figure shows linear relationship between 6-bit value loaded Watchdog Counter (CNT) resulting timeout duration milliseconds. This used quick calculation without taking timing variations into account. Figure Approximate Timeout Duration
more precision needed, formulae Figure Caution: When writing WDGCR register, always write avoid generating immediate reset.
Value (hex.)
Watchdog timeout (ms) MHz. fOSC2
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WINDOW WATCHDOG (Cont'd) Figure Exact Timeout Duration (tmin tmax) WHERE: tmin0 (LSB 128) tOSC2 tmax0 16384 tOSC2 tOSC2 125ns fOSC2=8 Value T[5:0] bits WDGCR register bits) values from table below depending timebase selected TB[1:0] bits MCCSR register
(MCCSR Reg.) (MCCSR Reg.) Selected MCCSR Timebase 10ms 25ms
calculate minimum Watchdog Timeout (tmin):
THEN min0 16384 tosc2 ELSE min0 16384 4CNT 4CNT
osc2
calculate maximum Watchdog Timeout (tmax):
THEN max0 16384 osc2 ELSE max0 16384 4CNT 4CNT
osc2
Note: above formulae, division results must rounded down next integer value. Example: With timeout selected MCCSR register
Value T[5:0] Bits WDGCR Register (Hex.) Min. Watchdog Timeout (ms) tmin 1.496 Max. Watchdog Timeout (ms) tmax 2.048 128.552
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WINDOW WATCHDOG (Cont'd) Figure Window Watchdog Timing Diagram
T[5:0] downcounter
WDGWR
Refresh allowed Refresh Window
time (step 16384/fOSC2)
Reset
11.1.6 Power Modes Mode SLOW WAIT Description effect Watchdog downcounter continues decrement normal speed. effect Watchdog downcounter continues decrement.
MCCSR register WDGHALT Option Byte Watchdog reset generated. enters Halt mode. Watchdog counter decremented once then stops counting longer able generate watchdog reset until receives external interrupt reset. interrupt received (refer interrupt table mapping interrupts which occur halt mode), Watchdog restarts counting after 4096 clocks. reset generated, Watchdog disabled (reset state) unless Hardware Watchdog selected option byte. application recommendations Section 11.1.8 below. reset generated instead entering halt mode. reset generated. enters Active Halt mode. Watchdog counter decremented. stop counting. When receives oscillator interrupt external interrupt, Watchdog restarts counting immediately. When receives reset Watchdog restarts counting after 4096 clocks.
HALT
ACTIVE HALT
11.1.7 Hardware Watchdog Option Hardware Watchdog selected option byte, watchdog always active WDGA WDGCR used. Refer Option Byte description.
11.1.8 Using Halt Mode with (WDGHALT option) following recommendation applies Halt mode used when watchdog enabled. Before executing HALT instruction, refresh counter, avoid unexpected reset immediately after waking microcontroller.
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WINDOW WATCHDOG (Cont'd) 11.1.9 Interrupts None. 11.1.10 Register Description CONTROL REGISTER (WDGCR) Read/Write Reset Value: 0111 1111 (7Fh)
WDGA
Note: This used hardware watchdog option enabled option byte. Bits T[6:0] 7-bit counter (MSB LSB). These bits contain value watchdog counter. decremented every 16384 fOSC2 cycles (approx.). reset produced when rolls over from becomes cleared). WINDOW REGISTER (WDGWR) Read/Write Reset Value: 0111 1111 (7Fh)
WDGA Activation bit. This software only cleared hardware after reset. When WDGA watchdog generate reset. Watchdog disabled Watchdog enabled
Reserved Bits W[6:0] 7-bit window value These bits contain window value compared downcounter.
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WINDOW WATCHDOG(Cont'd) Table Watchdog Timer Register Reset Values
Address (Hex.) Register Label WDGCR Reset Value WDGWR Reset Value WDGA
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11.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK BEEPER (MCC/RTC) Main Clock Controller consists three different functions: programmable clock prescaler clock-out signal supply external devices real time clock timer with interrupt capability Each function used independently simultaneously. 11.2.1 Programmable Clock Prescaler programmable clock prescaler supplies clock internal peripherals. manages SLOW power saving mode (See Section "SLOW MODE" page more details). prescaler selects fCPU main clock frequency controlled three bits MCCSR register: CP[1:0] SMS. 11.2.2 Clock-out Capability clock-out capability alternate function port that outputs fOSC2 clock drive external devices. controlled MCCSR register. CAUTION: When selected, clock suspends clock during ACTIVE-HALT mode. 11.2.3 Real Time Clock Timer (RTC) counter real time clock timer allows interrupt generated based accurate real time clock. Four different time bases depending directly fOSC2 available. whole functionality controlled four bits MCCSR register: TB[1:0], OIF. When interrupt enabled (OIE set), enters ACTIVE-HALT mode when HALT instruction executed. Section "ACTIVE-HALT MODE" page more details. 11.2.4 Beeper beep function controlled MCCBCR register. output three selectable frequencies BEEP (I/O port alternate function).
Figure Main Clock Controller (MCC/RTC) Block Diagram
MCCBCR BEEP BEEP SIGNAL SELECTION
12-BIT COUNTER
WATCHDOG TIMER
MCCSR fOSC2
MCC/RTC INTERRUPT
fCPU
CLOCK PERIPHERALS
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont'd) 11.2.5 Power Modes Bits CP[1:0] clock prescaler Mode Description These bits select clock prescaler which effect MCC/RTC peripheral. applied different slow modes. Their action WAIT MCC/RTC interrupt cause device exit conditioned setting bit. These from WAIT mode. bits cleared software
ACTIVEHALT effect MCC/RTC counter (OIE set), registers frozen. MCC/RTC interrupt cause device exit from ACTIVE-HALT mode. MCC/RTC counter registers frozen. MCC/RTC operation resumes when woken interrupt with "exit from HALT" capability. fCPU SLOW mode fOSC2 fOSC2 fOSC2 fOSC2
HALT
11.2.6 Interrupts MCC/RTC interrupt event generates interrupt MCCSR register interrupt mask register active (RIM instruction).
Interrupt Event Time base overflow event Enable Event Control Flag Exit from Wait Exit from Halt
Slow mode select This cleared software. Normal mode. fCPU fOSC2 Slow mode. fCPU given CP1, Section "SLOW MODE" page Section 11.1 "WINDOW WATCHDOG (WWDG)" page more details. Bits TB[1:0] Time base control These bits select programmable divider time base. They cleared software.
Time Base Counter Prescaler OSC2 =4MHz fOSC2=8MHz 16000 32000 20ms 50ms 10ms 25ms
Note: MCC/RTC interrupt wakes from ACTIVE-HALT mode, from HALT mode.
11.2.7 Register Description CONTROL/STATUS REGISTER (MCCSR) Read/Write Reset Value: 0000 0000 (00h)
80000 200000
modification time base taken into account current period (previously set) avoid unwanted time shift. This allows this time base real time clock. Oscillator interrupt enable This cleared software. Oscillator interrupt disabled Oscillator interrupt enabled This interrupt used exit from ACTIVEHALT mode. When this set, calling software HALT instruction enters ACTIVE-HALT power saving mode.
Main clock selection This enables alternate function port. cleared software. alternate function disabled (I/O free general-purpose I/O) alternate function enabled (fCPU port) Note: reduce power consumption, function active ACTIVE-HALT mode.
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont'd) BEEP CONTROL REGISTER (MCCBCR) Oscillator interrupt flag This hardware cleared software Read/Write reading MCCSR register. indicates when Reset Value: 0000 0000 (00h) that main oscillator reached selected elapsed time (TB1:0). Timeout reached Timeout reached CAUTION: BRES BSET instructions must used MCCSR register avoid Bits Reserved, must kept cleared. unintentionally clearing bit. Bits BC[1:0] Beep control These bits select beep capability.
~2-KHz ~1-KHz ~500-Hz Beep mode with fOSC2=8MHz Output Beep signal ~50% duty cycle
beep output signal available ACTIVEHALT mode disabled reduce consumption. Table Main Clock Controller Register Reset Values
Address (Hex.) 002Bh 002Ch 002Dh Register Label SICSR Reset Value MCCSR Reset Value MCCBCR Reset Value AVDIE AVDF LVDRF LOCKED WDGRF
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11.3 16-BIT TIMER 11.3.1 Introduction timer consists 16-bit free-running counter driven programmable prescaler. used variety purposes, including pulse length measurement input signals (input capture) generation output waveforms (output compare PWM). Pulse lengths waveform periods modulated from microseconds several milliseconds using timer prescaler clock prescaler. Some devices family have on-chip 16-bit timers. They completely independent, share resources. They synchronized after Device reset long timer clock frequencies modified. This description covers 16-bit timers. devices with timers, register names prefixed with (Timer (Timer 11.3.2 Main Features Programmable prescaler: fCPU divided Overflow status flag maskable interrupt External clock input (must least times slower than clock speed) with choice active edge Output compare functions with dedicated 16-bit registers dedicated programmable signals dedicated status flags dedicated maskable interrupt Input capture functions with dedicated 16-bit registers dedicated active edge selection signals dedicated status flags dedicated maskable interrupt Pulse width modulation mode (PWM) pulse mode Reduced Power Mode alternate functions ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* Block Diagram shown Figure *Note: Some timer pins available (not bonded) some devices. Refer device description. When reading input signal non-bonded pin, value will always `1'. 11.3.3 Functional Description 11.3.3.1 Counter main block Programmable Timer 16-bit free running upcounter associated 16-bit registers. 16-bit registers made 8-bit registers called high low. Counter Register (CR): Counter High Register (CHR) most significant byte Byte). Counter Register (CLR) least significant byte Byte). Alternate Counter Register (ACR) Alternate Counter High Register (ACHR) most significant byte Byte). Alternate Counter Register (ACLR) least significant byte Byte). These read-only 16-bit registers contain same value with difference that reading ACLR register does clear (Timer overflow flag), located Status register, (SR), (see note paragraph titled 16-bit read sequence). Writing register ACLR register resets free running counter FFFCh value. Both counters have reset value FFFCh (this only value which reloaded 16-bit timer). reset value both counters also FFFCh Pulse mode mode. timer clock depends clock control bits register, illustrated Table Clock Control Bits. value counter register repeats every 072, clock cycles depending CC[1:0] bits. timer frequency fCPU/2, fCPU/4, fCPU/8 external frequency.
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16-BIT TIMER (Cont'd) Figure Timer Block Diagram
INTERNAL fCPU 16-BIT TIMER PERIPHERAL INTERFACE 8-bit buffer EXEDG EXTCLK COUNTER REGISTER ALTERNATE COUNTER REGISTER CC[1:0] TIMER INTERNAL OVERFLOW DETECT CIRCUIT OUTPUT COMPARE REGISTER OUTPUT COMPARE REGISTER INPUT CAPTURE REGISTER INPUT CAPTURE REGISTER high high high high
high
OUTPUT COMPARE CIRCUIT
EDGE DETECT CIRCUIT1
ICAP1
EDGE DETECT CIRCUIT2
ICAP2
LATCH1
ICF1 OCF1 ICF2 OCF2 TIMD
OCMP1 OCMP2
LATCH2
(Control/Status Register)
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
OC1E OC2E
IEDG2 EXEDG
(Control Register
(Control Register
(See note) TIMER INTERRUPT
Note: interrupt requests have separate vectors then last present (See Device Interrupt Vector Table)
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16-BIT TIMER (Cont'd) 16-bit read sequence: (from either Counter Register Alternate Counter Register). Beginning sequence Read Byte Other instructions Read Byte Sequence completed user must read Byte first, then Byte value buffered automatically. This buffered value remains unchanged until 16-bit read sequence completed, even user reads Byte several times. After complete reading sequence, only register ACLR register read, they return Byte count value time read. Whatever timer mode used (input capture, output compare, pulse mode mode) overflow occurs when counter rolls over from FFFFh 0000h then: register set. timer interrupt generated TOIE register register cleared. these conditions false, interrupt remains pending issued soon they both true.
Returns buffered
Byte buffered
Byte value
Clearing overflow interrupt request done steps: Reading register while set. access (read write) register. Notes: cleared accesses ACLR register. advantage accessing ACLR register rather than register that allows simultaneous overflow function reading free running counter random times (for example, measure elapsed time) without risk clearing erroneously. timer affected WAIT mode. HALT mode, counter stops counting until mode exited. Counting then resumes from previous count (Device awakened interrupt) from reset count (Device awakened Reset). 11.3.3.2 External Clock external clock (where available) selected CC0=1 CC1=1 register. status EXEDG register determines type level transition external clock EXTCLK that will trigger free running counter. counter synchronised with falling edge internal clock. minimum four falling edges clock must occur between consecutive active edges external clock; thus external clock frequency must less than quarter clock frequency.
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16-BIT TIMER (Cont'd) Figure Counter Timing Diagram, internal clock divided
CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFD FFFE FFFF 0000 0001 0002 0003
Figure Counter Timing Diagram, internal clock divided
CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 0001
Figure Counter Timing Diagram, internal clock divided
CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000
Note: Device reset state when internal reset signal high, when Device running.
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16-BIT TIMER (Cont'd) 11.3.3.3 Input Capture this section, index, because there input capture functions 16-bit timer. input capture 16-bit registers (IC1R IC2R) used latch value free running counter after transition detected ICAPi (see figure
ICiR Byte ICiHR Byte ICiLR
ICiR register read-only register. active transition software programmable through IEDGi Control Registers (CRi). Timing resolution count free running counter: (fCPU/CC[1:0]). Procedure: input capture function select following register: Select timer clock (CC[1:0]) (see Table Clock Control Bits). Select edge active transition ICAP2 with IEDG2 (the ICAP2 must configured floating input). select following register: ICIE generate interrupt after input capture coming from either ICAP1 ICAP2 Select edge active transition ICAP1 with IEDG1 (the ICAP1pin must configured floating input).
When input capture occurs: ICFi set. ICiR register contains value free running counter active transition ICAPi (see Figure 49). timer interrupt generated ICIE cleared register. Otherwise, interrupt remains pending until both conditions become true. Clearing Input Capture interrupt request (i.e. clearing ICFi bit) done steps: Reading register while ICFi set. access (read write) ICiLR register. Notes: After reading ICiHR register, transfer input capture data inhibited ICFi will never until ICiLR register also read. ICiR register contains free running counter value which corresponds most recent input capture. input capture functions used together even timer also uses output compare functions. pulse Mode mode only input capture used. alternate inputs (ICAP1 ICAP2) always directly connected timer. transitions these pins activate input capture function. Moreover ICAPi configured input second output, interrupt generated user toggle output ICIE set. This avoided input capture function disabled reading ICiHR (see note used with interrupt order measure event that beyond timer range (FFFFh).
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16-BIT TIMER (Cont'd) Figure Input Capture Block Diagram
ICAP1 ICAP2 EDGE DETECT CIRCUIT2 EDGE DETECT CIRCUIT1
ICIE
(Control Register
IEDG1
(Status Register) IC2R Register IC1R Register
ICF1 ICF2
16-BIT
(Control Register
IEDG2
16-BIT FREE RUNNING
COUNTER
Figure Input Capture Timing Diagram
TIMER CLOCK COUNTER REGISTER ICAPi ICAPi FLAG ICAPi REGISTER Note: active edge rising edge. FF03 FF01 FF02 FF03
Note: time between event ICAPi appearance corresponding flag from clock cycles. This depends moment when ICAP event happens relative timer clock.
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16-BIT TIMER (Cont'd) 11.3.3.4 Output Compare this section, index, because there output compare functions 16-bit timer. This function used control output waveform indicate when period time elapsed. When match found between Output Compare register free running counter, output compare function: Assigns pins with programmable value OCIE Sets flag status register Generates interrupt enabled 16-bit registers Output Compare Register (OC1R) Output Compare Register (OC2R) contain value compared counter register each timer clock cycle.
OCiR Byte OCiHR Byte OCiLR
OCMPi takes OLVLi value (OCMPi latch forced during reset). timer interrupt generated OCIE register cleared register (CC). OCiR register value required specific timing application calculated using following formula:
OCiR
fCPU
PRESC
Where: Output compare period seconds) fCPU clock frequency hertz) PRESC Timer prescaler factor depending CC[1:0] bits, Table Clock Control Bits) timer clock external clock, formula
These registers readable writable affected timer hardware. reset event changes OCiR value 8000h. Timing resolution count free running counter: (fCPU/CC[1:0]). Procedure: output compare function, select following register: OCiE output needed then OCMPi dedicated output compare signal. Select timer clock (CC[1:0]) (see Table Clock Control Bits). select following register: Select OLVLi applied OCMPi pins after match occurs. OCIE generate interrupt needed. When match found between OCRi register register: OCFi set.
OCiR fEXT
Where:
fEXT
Output compare period seconds) External timer clock frequency hertz)
Clearing output compare interrupt request (i.e. clearing OCFi bit) done Reading register while OCFi set. access (read write) OCiLR register. following procedure recommended prevent OCFi from being between time read write OCiR register: Write OCiHR register (further compares inhibited). Read register (first step clearance OCFi bit, which already set). Write OCiLR register (enables output compare function clears OCFi bit).
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16-BIT TIMER (Cont'd) Notes: After processor write cycle OCiHR register, output compare function inhibited until OCiLR register also written. OCiE set, OCMPi general port OLVLi will appear when match found interrupt could generated OCIE set. When timer clock fCPU/2, OCFi OCMPi while counter value equals OCiR register value (see Figure page 77). This behaviour same mode. When timer clock fCPU/4, fCPU/8 external clock mode, OCFi OCMPi while counter value equals OCiR register value plus (see Figure page 77). output compare functions used both generating external events OCMPi pins even input capture mode also used. value 16-bit OCiR register OLVi should changed after each successful comparison order control output waveform establish elapsed timeout. Figure Output Compare Block Diagram
Forced Compare Output capability When FOLVi software, OLVLi copied OCMPi pin. OLVi toggled order toggle OCMPi when enabled (OCiE bit=1). OCFi then hardware, thus interrupt request generated. FOLVLi bits have effect both pulse mode mode.
FREE RUNNING COUNTER 16-bit OUTPUT COMPARE CIRCUIT 16-bit 16-bit
OC1E OC2E
(Control Register (Control Register
OCIE FOLV2 FOLV1 OLVL2 OLVL1 Latch
OCMP1 OCMP2
OC1R Register
OCF1 OCF2
Latch
OC2R Register (Status Register)
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16-BIT TIMER (Cont'd) Figure Output Compare Timing Diagram, fTIMER =fCPU/2
INTERNAL CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER (OCRi) OUTPUT COMPARE FLAG (OCFi) OCMPi (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
Figure Output Compare Timing Diagram, fTIMER =fCPU/4
INTERNAL CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER (OCRi) COMPARE REGISTER LATCH OUTPUT COMPARE FLAG (OCFi) OCMPi (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
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16-BIT TIMER (Cont'd) 11.3.3.5 Pulse Mode Pulse mode enables generation pulse when external event occurs. This mode selected register. pulse mode uses Input Capture1 function Output Compare1 function. Procedure: pulse mode: Load OC1R register with value corresponding length pulse (see formula opposite column). Select following register: Using OLVL1 bit, select level applied OCMP1 after pulse. Using OLVL2 bit, select level applied OCMP1 during pulse. Select edge active transition ICAP1 with IEDG1 (the ICAP1 must configured floating input). Select following register: OC1E bit, OCMP1 then dedicated Output Compare function. bit. Select timer clock CC[1:0] (see Table Clock Control Bits). pulse mode cycle When event occurs ICAP1 ICR1 Counter OCMP1 OLVL2 Counter reset FFFCh ICF1 When Counter OC1R
Clearing Input Capture interrupt request (i.e. clearing ICFi bit) done steps: Reading register while ICFi set. access (read write) ICiLR register. OC1R register value required specific timing application calculated using following formula: OCiR Value
fCPU
PRESC
Where: Pulse period seconds) fCPU clock frequency hertz) PRESC Timer prescaler factor depending CC[1:0] bits, Table Clock Control Bits) timer clock external clock formula OCiR fEXT Where: Pulse period seconds) External timer clock frequency hertz) fEXT When value counter equal value contents OC1R register, OLVL1 output OCMP1 pin, (See Figure 53). Notes: OCF1 cannot hardware pulse mode OCF2 generate Output Compare interrupt. When Pulse Width Modulation (PWM) Pulse Mode (OPM) bits both set, mode only active one. OLVL1=OLVL2 continuous signal will seen OCMP1 pin. ICAP1 used perform input capture. ICAP2 used perform input capture (ICF2 IC2R loaded) user must take care that counter reset each time valid edge occurs ICAP1 ICF1 also generates interrupt ICIE set. When pulse mode used OC1R dedicated this mode. Nevertheless OC2R OCF2 used indicate period time been elapsed cannot generate output waveform because level OLVL2 dedicated pulse mode.
OCMP1 OLVL1
When valid event occurs ICAP1 pin, counter value loaded ICR1 register. counter then initialized FFFCh, OLVL2 output OCMP1 ICF1 set. Because ICF1 when active edge occurs, interrupt generated ICIE set.
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16-BIT TIMER (Cont'd) Figure Pulse Mode Timing Example
IC1R COUNTER ICAP1 OCMP1 OLVL2 OLVL1 OLVL2 01F8 FFFC FFFD FFFE 01F8 2ED0 2ED1 2ED2 2ED3 2ED3 FFFC FFFD
compare1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure Pulse Width Modulation Mode Timing Example
COUNTER 34E2 FFFC FFFD FFFE OCMP1 OLVL2
2ED0 2ED1 2ED2
34E2
FFFC
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2=
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16-BIT TIMER (Cont'd) 11.3.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables generation signal with frequency pulse length determined value OC1R OC2R registers. Pulse Width Modulation mode uses complete Output Compare function plus OC2R register, this functionality used when mode activated. mode, double buffering implemented output compare registers. values written OC1R OC2R registers loaded their respective shadow registers (double buffer) only period (OC2) avoid spikes output (OCMP1). shadow registers contain reference values comparison "double buffering" mode. Note: There locking mechanism transferring OCiR value buffer. After write OCiHR register, transfer compare value buffer inhibited until OCiLR also written. Unlike Output Compare mode, compare function always enabled mode. Procedure pulse width modulation mode: Load OC2R register with value corresponding period signal using formula opposite column. Load OC1R register with value corresponding period pulse (OLVL1=0 OLVL2=1) using formula opposite column. Select following register: Using OLVL1 bit, select level applied OCMP1 after successful comparison with OC1R register. Using OLVL2 bit, select level applied OCMP1 after successful comparison with OC2R register. Select following register: OC1E bit: OCMP1 then dedicated output compare function. bit. Select timer clock (CC[1:0]) (see Table
Clock Control Bits). Pulse Width Modulation cycle When Counter OC1R
OCMP1 OLVL1
When Counter OC2R
OCMP1 OLVL2 Counter reset FFFCh ICF1
OLVL1=1 OLVL2=0 length positive pulse difference between OC2R OC1R registers. OLVL1=OLVL2 continuous signal will seen OCMP1 pin. OCiR register value required specific timing application calculated using following formula: OCiR Value
fCPU
PRESC
Where: Signal pulse period seconds) fCPU clock frequency hertz) PRESC Timer prescaler factor depending CC[1:0] bits, Table Clock Control Bits) timer clock external clock formula OCiR fEXT Where: Signal pulse period seconds) External timer clock frequency hertz) fEXT Output Compare event causes counter initialized FFFCh (See Figure Notes: OCF1 OCF2 bits cannot hardware mode therefore Output Compare interrupt inhibited. ICF1 hardware when counter reaches OC2R value produce timer interrupt ICIE cleared.
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16-BIT TIMER (Cont'd) mode ICAP1 used perform input capture because disconnected timer. ICAP2 used perform input capture (ICF2 IC2R loaded) user must take care that counter reset each period 11.3.4 Power Modes
Mode WAIT
ICF1 also generates interrupt ICIE set. When Pulse Width Modulation (PWM) Pulse Mode (OPM) bits both set, mode only active one.
Description effect 16-bit Timer. Timer interrupts cause Device exit from WAIT mode. 16-bit Timer registers frozen. HALT mode, counter stops counting until
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