3V/5V RANGE 8-BIT WITH 4/8K ROM, 10-BIT ADC, TIMERS, Memories 4/8
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ST72323
3V/5V RANGE 8-BIT WITH 4/8K ROM, 10-BIT ADC, TIMERS,
Memories 4/8K with read-out protection capability bytes Compatible with Flash superset ST72F324B Clock, Reset Supply Management Clock sources: crystal/ceramic resonator oscillators, internal oscillator bypass external clock Four Power Saving Modes: Halt, Active-Halt, Wait Slow Interrupt Management Nested interrupt controller interrupt vectors plus TRAP RESET external interrupt lines vectors) Ports 32/24 multifunctional bidirectional lines 22/17 alternate function lines 12/10 high sink outputs Timers Main Clock Controller with: Real time base, Beep Clock-out capabilities Configurable watchdog timer 16-bit Timer with: input capture, output compare, external clock input, pulse generator modes 16-bit Timer with: input captures, output compares, pulse generator modes
LQFP44
LQFP48
LQFP32
SO34
SDIP32
Communications Interface synchronous serial interface Analog Peripheral (low current coupling) 10-bit with robust input ports Instruction 8-bit Data Manipulation Basic Instructions main Addressing Modes Unsigned Multiply Instruction Development Tools Full hardware/software development package In-Circuit Testing capability
ST72323x1
Device Summary
Features
Program memory bytes (stack) bytes Voltage Range Temp. Range Packages
ST72323Lx1
ST72323Lx2
ST72323x2
(256) (256) 2.85V 3.6V 3.8V 5.5V -40°C +85°C -40°C +125°C LQFP48 LQFP44 10x10 SO34, LQFP32 7x7, SDIP32
Rev.
April 2006 1/140
This preliminary information product development undergoing evaluation. Details subject change without notice.
Table Contents
INTRODUCTION DESCRIPTION REGISTER MEMORY CENTRAL PROCESSING UNIT INTRODUCTION MAIN FEATURES REGISTERS
SUPPLY, RESET CLOCK MANAGEMENT MULTI-OSCILLATOR (MO) RESET SEQUENCE MANAGER (RSM) 5.2.1 Introduction 5.2.2 Asynchronous External RESET 5.2.3 External Power-On RESET 5.2.4 Internal Watchdog RESET INTERRUPTS INTRODUCTION
MASKING PROCESSING FLOW INTERRUPTS POWER MODES CONCURRENT NESTED MANAGEMENT INTERRUPT REGISTER DESCRIPTION EXTERNAL INTERRUPTS 6.6.1 Port Interrupt Sensitivity EXTERNAL INTERRUPT CONTROL REGISTER (EICR)
POWER SAVING MODES INTRODUCTION SLOW MODE WAIT MODE ACTIVE-HALT HALT MODES
7.4.1 ACTIVE-HALT MODE 7.4.2 HALT MODE PORTS INTRODUCTION 8.2.1 Input Modes 8.2.2 Output Modes 8.2.3 Alternate Functions PORT IMPLEMENTATION
FUNCTIONAL DESCRIPTION
POWER MODES INTERRUPTS
8.5.1 Port Implementation ON-CHIP PERIPHERALS WATCHDOG TIMER (WDG) 140. 9.1.1 Introduction 9.1.2 Main Features
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Table Contents
9.1.3 Functional Description 9.1.4 Program Watchdog Timeout 9.1.5 Power Modes 9.1.6 Hardware Watchdog Option 9.1.7 Using Halt Mode with (WDGHALT option) 9.1.8 Interrupts 9.1.9 Register Description MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK BEEPER (MCC/RTC) 9.2.1 Programmable Clock Prescaler 9.2.2 Clock-out Capability 9.2.3 Real Time Clock Timer (RTC) 9.2.4 Beeper 9.2.5 Power Modes 9.2.6 Interrupts 9.2.7 Register Description 16-BIT TIMER 9.3.1 Introduction 9.3.2 Main Features 9.3.3 Functional Description 9.3.4 Power Modes 9.3.5 Interrupts 9.3.6 Summary Timer modes 9.3.7 Register Description SERIAL PERIPHERAL INTERFACE (SPI) 9.4.1 Introduction 9.4.2 Main Features 9.4.3 General Description 9.4.4 Clock Phase Clock Polarity 9.4.5 Error Flags 9.4.6 Power Modes 9.4.7 Interrupts 9.4.8 Register Description 10-BIT CONVERTER (ADC) 9.5.1 Introduction 9.5.2 Main Features 9.5.3 Functional Description 9.5.4 Power Modes 9.5.5 Interrupts 9.5.6 Register Description INSTRUCTION 10.1 ADDRESSING MODES 10.1.1 10.1.2 10.1.3 10.1.4 10.1.5 10.1.6 10.1.7 Inherent Immediate Direct Indexed Offset, Short, Long) Indirect (Short, Long) Indirect Indexed (Short, Long) Relative mode (Direct, Indirect)
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Table Contents
10.2 INSTRUCTION GROUPS ELECTRICAL CHARACTERISTICS 11.1 PARAMETER CONDITIONS 11.1.1 Minimum Maximum values 11.1.2 Typical values 11.1.3 Typical curves 11.1.4 Loading capacitor 11.1.5 input voltage 11.2 ABSOLUTE MAXIMUM RATINGS 11.2.1 Voltage Characteristics 11.2.2 Current Characteristics 11.2.3 Thermal Characteristics 11.3 OPERATING CONDITIONS
11.3.1 Operating Conditions (ST72323 devices) 11.3.2 Operating Conditions (ST72323L devices) 11.4 SUPPLY CURRENT CHARACTERISTICS 11.4.1 Supply Clock Managers 11.4.2 On-Chip Peripherals 11.5 CLOCK TIMING CHARACTERISTICS 11.5.1 General Timings 11.5.2 External Clock Source 11.5.3 Crystal Ceramic Resonator Oscillators 11.5.4 Oscillators 11.6 MEMORY CHARACTERISTICS
11.6.1 Hardware Registers 11.7 CHARACTERISTICS 11.7.1 Functional (Electro Magnetic Susceptibility) 11.7.2 Electro Magnetic Interference (EMI) 11.7.3 Absolute Maximum Ratings (Electrical Sensitivity) 11.8 PORT CHARACTERISTICS
11.8.1 General Characteristics 11.8.2 Output Driving Current 11.9 CONTROL CHARACTERISTICS 11.9.1 Asynchronous RESET 11.9.2 ICCSEL 11.10 TIMER PERIPHERAL CHARACTERISTICS 11.10.116-Bit Timer 11.11 COMMUNICATION INTERFACE CHARACTERISTICS 11.11.1SPI Serial Peripheral Interface 11.12 10-BIT CHARACTERISTICS 11.12.1Analog Power Supply Reference Pins 11.12.2General Design Guidelines 11.12.3ADC Accuracy PACKAGE CHARACTERISTICS 12.1 PACKAGE MECHANICAL DATA 12.2 THERMAL CHARACTERISTICS
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Table Contents
12.3 SOLDERING INFORMATION ST72323 DEVICE CONFIGURATION ORDERING INFORMATION 13.1 FLASH OPTION BYTES (ST72F324B COMPATIBLE SUPERSET) 13.2 DEVICE ORDERING INFORMATION TRANSFER CUSTOMER CODE 13.3 VERSION-SPECIFIC SALES CONDITIONS 13.4 ORDERING INFORMATION COMPATIBLE FLASH DEVICES 13.5 DEVELOPMENT TOOLS 13.5.1 Socket Emulator Adapter Information 13.6 APPLICATION NOTES KNOWN LIMITATIONS 14.1 UNEXPECTED RESET FETCH 14.2 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE 14.3 EXTERNAL INTERRUPT MISSED 14.4 16-BIT TIMER MODE 14.5 ST72F324B COMPATIBLE FLASH DEVICES 14.5.1 Internal Operation REVISION HISTORY
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ST72323
INTRODUCTION
ST72323L ST72323 devices members microcontroller family designed operating range. 32/34-pin devices designed midrange applications 42/44/48-pin devices target same range applications requiring more than ports. devices based common industrystandard 8-bit core, featuring enhanced instrucFigure Device Block Diagram
8-BIT CORE RESET ICCSEL CONTROL
tion available with program memory. Under software control, devices placed WAIT, SLOW, ACTIVE-HALT HALT mode, reducing power consumption when application idle stand-by state. enhanced instruction addressing modes offer both power flexibility software developers, enabling design highly efficient compact application code. addition standard 8-bit data management, microcontrollers feature manipulation, unsigned multiplication indirect addressing modes.
PROGRAM MEMORY (4/8K Bytes) (384 Bytes)
WATCHDOG OSC1 OSC2 ADDRESS DATA MCC/RTC/BEEP
PORT
PORT PF7:6,4,2:0 bits devices) bits devices) TIMER BEEP PE1:0 bits) PORT
PA7:3 bits devices) bits devices)
PORT
PB4:0 bits devices) bits devices)
PORT TIMER PORT PD5:0 bits devices) bits devices) VAREF VSSA 10-BIT PC7:0 bits)
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DESCRIPTION
Figure 48-Pin Device Pinout
(HS) AIN0 AIN1 AIN2 AIN3 AIN4 AIN5
VAREF VSSA AIN8 BEEP (HS) (HS) OCMP1_A AIN10 ICAP1_A (HS) EXTCLK_A (HS) VDD_0 VSS_0 N.C. N.C.
ICCSEL (HS) (HS) (HS) (HS) (HS) AIN15 ICCCLK MOSI AIN14 MISO ICCDATA (HS) ICAP1_B (HS) ICAP2_B OCMP1_B AIN13 OCMP2_B AIN12
VDD_2 OSC1 OSC2 VSS_2 RESET N.C. N.C.
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Figure 44-Pin LQFP Package Pinouts
(HS) AIN0 AIN1 AIN2 AIN3 AIN4
AIN5 VAREF VSSA AIN8 BEEP (HS) (HS) OCMP1_A AIN10 ICAP1_A (HS) EXTCLK_A (HS) VDD_0 VSS_0
VDD_2 OSC1 OSC2 VSS_2 RESET ICCSEL (HS) (HS) (HS) (HS)
(HS) AIN15 ICCCLK MOSI AIN14 MISO ICCDATA (HS) ICAP1_B (HS) ICAP2_B OCMP1_B AIN13 OCMP2_B AIN12
(HS) 20mA high sink capability associated external interrupt vector
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DESCRIPTION (Cont'd) Figure 32-Pin SDIP Package Pinout
(HS) AIN0 AIN1 VAREF VSSA AIN8 BEEP (HS) OCMP1_A AIN10 ICAP1_A (HS) EXTCLK_A (HS) AIN12 OCMP2_B AIN13 OCMP1_B ICAP2_B (HS) ICAP1_B (HS) ICCDATA/ MISO AIN14 MOSI
VDD_2 OSC1 OSC2 VSS_2 RESET ICCSEL (HS) (HS) (HS) (HS) AIN15 ICCCLK (HS) 20mA high sink capability associated external interrupt vector
Figure 32-Pin LQFP Package Pinout
VAREF VSSA AIN8 BEEP (HS) OCMP1_A AIN10 ICAP1_A (HS) EXTCLK_A (HS) AIN12 OCMP2_B
AIN13 OCMP1_B ICAP2_B (HS) ICAP1_B (HS) ICCDATA MISO AIN14 MOSI ICCCLK AIN15 (HS)
AIN1 AIN0 (HS) VDD_2
OSC1 OSC2 VSS_2 RESET ICCSEL (HS) (HS) (HS)
(HS) 20mA high sink capability associated external interrupt vector
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DESCRIPTION (Cont'd) Figure 34-Pin Package Pinout
(HS) AIN0 AIN1 VAREF VSSA AIN8 BEEP (HS) OCMP1_A AIN10 ICAP1_A (HS) EXTCLK_A (HS) AIN12 OCMP2_B AIN13 OCMP1_B ICAP2_B (HS) ICAP1_B (HS) ICCDATA/ MISO AIN14 MOSI
VDD_2 OSC1 OSC2 VSS_2 RESET ICCSEL (HS) (HS) (HS) (HS) AIN15 ICCCLK (HS) 20mA high sink capability associated external interrupt vector
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DESCRIPTION (Cont'd) external connection guidelines, refer "ELECTRICAL CHARACTERISTICS" page Legend Abbreviations Table Type: input, output, supply Input level: Dedicated analog input In/Output level: CMOS 0.3VDD/0.7VDD CMOS 0.3VDD/0.7VDD with input trigger Output level: 20mA high sink N-buffer only) Port control configuration: Input: float floating, weak pull-up, interrupt analog ports Output: open drain push-pull Refer "I/O PORTS" page more details software configuration ports. RESET configuration each shown bold. This configuration valid long device reset state. Table Device Description
LQFP48 LQFP44 LQFP32 Type SDIP32 SO34 Name Level Output Input Port Input float Main function Output (after reset) Port Port Port Port Port Port Port Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input
Alternate Function
(HS) PD0/AIN0 PD1/AIN1 PD2/AIN2 PD3/AIN3 PD4/AIN4 PD5/AIN5
VAREF VSSA PF0/MCO/AIN8 (HS)/BEEP (HS) PF4/OCMP1_A/ AIN10
Analog Reference Voltage Analog Ground Voltage Port Port Port Port Port Port Timer OutADC Analog Compare Input Timer Input Capture Timer External Clock Source Main clock (fCPU) Analog Input
Beep signal output
(HS)/ICAP1_A
(HS)/ EXTCLK_A VDD_0 VSS_0 PC0/OCMP2_B/ AIN12
Digital Main Supply Voltage Digital Ground Voltage Port Timer OutADC Analog Compare Input
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LQFP48 LQFP44 LQFP32 Type SDIP32 SO34 Name
Level Output Input
Port Input float
Main function Output (after reset)
Alternate Function
PC1/OCMP1_B/ AIN13
Port Port Port Port
Timer OutADC Analog Compare Input Timer Input Capture Timer Input Capture Master Slave Data Master Slave Data Serial Clock Slave Select (active low) Data Input Analog Input Clock Output Analog Input
(HS)/ICAP2_B (HS)/ICAP1_B PC4/MISO/ ICCDATA
PC5/MOSI/AIN14 PC6/SCK/ICCCLK PC7/SS/AIN15 (HS) (HS)
Port Port Port Port
connected connected Port Port Port Port Must tied low. priority maskable interrupt. Digital Ground Voltage Resonator oscillator inverter output External clock input Resonator oscillator inverter input Digital Main Supply Voltage Port Port Port Port Port Port
(HS) (HS) (HS) ICCSEL RESET VSS_2 OSC2 OSC1 VDD_2
Notes: interrupt input column, "eiX" defines associated external interrupt vector. weak pull-up column (wpu) merged with interrupt column (int), then configuration pull-up interrupt input, else configuration floating interrupt input. open drain output column, defines true open drain (P-Buffer protection diode implemented). "I/O PORTS" page Section 11.8 PORT CHARACTER-
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ISTICS more details. OSC1 OSC2 pins connect crystal/ceramic resonator, external source on-chip oscillator; Section INTRODUCTION Section 11.5 CLOCK TIMING CHARACTERISTICS more details. chip, each port pads. Pads that bonded external pins input pull-up configuration after reset. configuration these pads must kept reset state avoid added current consumption.
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REGISTER MEMORY
shown Figure capable addressing bytes memories registers. available memory locations consist bytes register locations, bytes 8Kbytes user program memory. space includes bytes stack from 0100h 01FFh. Figure Memory
0000h 007Fh 0080h
highest address bytes contain user reset interrupt vectors. IMPORTANT: Memory locations marked "Reserved" must never accessed. Accessing reseved area have unpredictable effects device.
Registers (see Table
0080h
(384 Bytes)
01FFh 0200h
Short Addressing (zero page)
00FFh 0100h
Bytes Stack
01FFh
Reserved
0FFFh 1000h
Program Memory (8K)
FFDFh FFE0h FFFFh
Interrupt Reset Vectors (see Table
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Table Hardware Register
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 0030h MCCSR MCCBCR WATCHDOG WDGCR SPIDR SPICR SPICSR ISPR0 ISPR1 ISPR2 ISPR3 EICR Block Register Label PADR PADDR PAOR PBDR PBDDR PBOR PCDR PCDDR PCOR PDADR PDDDR PDOR PEDR PEDDR PEOR PFDR PFDDR PFOR Register Name Port Data Register Port Data Direction Register Port Option Register Port Data Register Port Data Direction Register Port Option Register Port Data Register Port Data Direction Register Port Option Register Port Data Register Port Data Direction Register Port Option Register Port Data Register Port Data Direction Register Port Option Register Port Data Register Port Data Direction Register Port Option Register Reset Status 00h1) 00h1) 00h1) 00h1) 00h1) 00h1) Remarks R/W2) R/W2)
Port
Port
Port
Port
Port
Port
Reserved Area Bytes)
Data Register Control Register Control/Status Register Interrupt Software Priority Register Interrupt Software Priority Register Interrupt Software Priority Register Interrupt Software Priority Register External Interrupt Control Register Reserved Area Byte) Watchdog Control Register Reserved Area Byte) Main Clock Control Status Register Main Clock Controller: Beep Control Register
Reserved Area Bytes)
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Address 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 006Fh 0070h 0071h 0072h 0073h 007Fh
Block
Register Label TACR2 TACR1 TACSR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR
Register Name Timer Control Register Timer Control Register Timer Control/Status Register Timer Input Capture High Register Timer Input Capture Register Timer Output Compare High Register Timer Output Compare Register Timer Counter High Register Timer Counter Register Timer Alternate Counter High Register Timer Alternate Counter Register Timer Input Capture High Register Timer Input Capture Register Timer Output Compare High Register Timer Output Compare Register Reserved Area Byte)
Reset Status xxxx x0xxb
Remarks Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only
TIMER
TIMER
TBCR2 TBCR1 TBCSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR
Timer Control Register Timer Control Register Timer Control/Status Register Timer Input Capture High Register Timer Input Capture Register Timer Output Compare High Register Timer Output Compare Register Timer Counter High Register Timer Counter Register Timer Alternate Counter High Register Timer Alternate Counter Register Timer Input Capture High Register Timer Input Capture Register Timer Output Compare High Register Timer Output Compare Register
xxxx x0xxb
Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only
Reserved Area Bytes)
ADCCSR ADCDRH ADCDRL
Control/Status Register Data High Register Data Register Reserved Area Bytes)
Read Only Read Only
Legend: x=undefined, R/W=read/write Notes: contents port registers readable only output configuration. input configuration, values pins returned instead register contents. bits associated with unavailable pins must always keep their reset value.
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CENTRAL PROCESSING UNIT
INTRODUCTION This full 8-bit architecture contains internal registers allowing efficient 8-bit data manipulation. MAIN FEATURES
REGISTERS registers shown Figure present memory mapping accessed specific instructions. Accumulator Accumulator 8-bit general purpose register used hold operands results arithmetic logic calculations manipulate data. Index Registers These 8-bit registers used create effective addresses temporary storage areas data manipulation. (The Cross-Assembler generates precede instruction (PRE) indicate that following instruction refers register.) register affected interrupt automatic procedures. Program Counter (PC) program counter 16-bit register containing address next instruction executed CPU. made 8-bit registers (Program Counter which LSB) (Program Counter High which MSB).
Enable executing basic instructions Fast 8-bit 8-bit multiply main addressing modes (with indirect addressing mode) 8-bit index registers 16-bit stack pointer power HALT WAIT modes Priority maskable hardware interrupts Non-maskable software/hardware interrupts
Figure Registers
RESET VALUE RESET VALUE RESET VALUE PROGRAM COUNTER RESET VALUE RESET VECTOR FFFEh-FFFFh CONDITION CODE REGISTER RESET VALUE STACK POINTER RESET VALUE STACK HIGHER ADDRESS Undefined Value INDEX REGISTER INDEX REGISTER ACCUMULATOR
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CENTRAL PROCESSING UNIT (Cont'd) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx
Zero. This cleared hardware. This indicates that result last arithmetic, logical data manipulation zero. result last operation different from zero. result last operation zero. This accessed JREQ JRNE test instructions. Carry/borrow. This cleared hardware software. indicates overflow underflow occurred during last arithmetic operation. overflow underflow occurred. overflow underflow occurred. This driven instructions tested JRNC instructions. also affected "bit test branch", shift rotate instructions. Interrupt Management Bits Interrupt combination bits gives current interrupt software priority.
Interrupt Software Priority Level (main) Level Level Level interrupt disable)
8-bit Condition Code register contains interrupt masks four flags representative result instruction just executed. This register also handled PUSH instructions. These bits individually tested and/or controlled specific instructions. Arithmetic Management Bits Half carry. This hardware when carry occurs between bits during instructions. reset hardware during same instructions. half carry occurred. half carry occurred. This tested using JRNH instruction. useful arithmetic subroutines. Negative. This cleared hardware. representative result sign last arithmetic, logical data manipulation. It's copy result bit. result last operation positive null. result last operation negative (i.e. most significant logic This accessed JRMI JRPL instructions.
These bits set/cleared hardware when entering interrupt. loaded value given corresponding bits interrupt software priority registers (IxSPR). They also set/ cleared software with RIM, SIM, IRET, HALT, PUSH/POP instructions. interrupt management chapter more details.
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CENTRAL PROCESSING UNIT (Cont'd) Stack Pointer (SP) Read/Write Reset Value:
Stack Pointer 16-bit register which always pointing next free location stack. then decremented after data been pushed onto stack incremented before data popped from stack (see Figure Since stack bytes deep, most significant bits forced hardware. Following Reset, after Reset Stack Pointer instruction (RSP), Stack Pointer contains reset value (the bits set) which stack higher address. Figure Stack Manipulation Example
CALL Subroutine 0100h Interrupt Event PUSH
least significant byte Stack Pointer (called directly accessed instruction. Note: When lower limit exceeded, Stack Pointer wraps around stack upper limit, without indicating stack overflow. previously stored information then overwritten therefore lost. stack also wraps case underflow. stack used save return address during subroutine call context during interrupt. user also directly manipulate stack means PUSH instructions. case interrupt, stored first location pointed Then other registers stored next locations shown Figure When interrupt received, decremented context pushed stack. return from interrupt, incremented context popped from stack. subroutine call occupies locations interrupt five locations stack area.
IRET
01FFh
Stack Higher Address 01FFh Stack Lower Address 0100h
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SUPPLY, RESET CLOCK MANAGEMENT
device includes range utility features securing application critical situations (for example case power brown-out), reducing number external components. overview shown Figure more details, refer dedicated parametric section. Figure Clock, Reset Supply Block Diagram
OSC2 OSC1 MULTIOSCILLATOR (MO) MAIN CLOCK CONTROLLER WITH REALTIME CLOCK (MCC/RTC)
Main features Reset Sequence Manager (RSM) Multi-Oscillator Clock Management (MO) Crystal/Ceramic resonator oscillators Internal oscillator
fOSC
DIVIDER
fOSC2
fCPU
peripherals
RESET SEQUENCE RESET MANAGER (RSM)
WATCHDOG TIMER (WDG)
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MULTI-OSCILLATOR (MO) main clock generated three different source types coming from multioscillator block: external source crystal ceramic resonator oscillators internal high frequency oscillator Each oscillator optimized given frequency range terms consumption selectable through option byte. associated hardware configurations shown Table Refer electrical characteristics section more details. Caution: OSC1 and/or OSC2 pins must left unconnected. purposes Failure Mode Effect Analysis, should noted that OSC1 and/or OSC2 pins left unconnected, main oscillator start and, this configuration, could generate fOSC clock frequency excess allowed maximum (>16MHz.), putting unsafe/undefined state. product behaviour must therefore considered undefined when pins left unconnected. External Clock Source this external clock mode, clock signal (square, sinus triangle) with ~50% duty cycle drive OSC1 while OSC2 tied ground. Crystal/Ceramic Oscillators This family oscillators advantage producing very accurate rate main clock ST7. selection within list oscillators with different frequency ranges done option byte order reduce consumption (refer Section 13.1 page more details frequency ranges). this mode multioscillator, resonator load capacitors have placed close possible oscillator pins order minimize output distortion start-up stabilization time. loading capacitance values must adjusted according selected oscillator. These oscillators stopped during RESET phase avoid losing time oscillator start-up phase. Internal Oscillator This oscillator allows cost solution main clock using only internal resistor capacitor. Internal oscillator mode drawback lower frequency accuracy should used applications that require accurate timing. this mode, oscillator pins have tied ground. Table Clock Sources
Hardware Configuration
External Clock
OSC1 OSC2
EXTERNAL SOURCE
Crystal/Ceramic Resonators
OSC1 OSC2
LOAD CAPACITORS
Internal Oscillator
OSC1 OSC2
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RESET SEQUENCE MANAGER (RSM) 5.2.1 Introduction reset sequence manager includes three RESET sources shown Figure External RESET source pulse Internal WATCHDOG RESET These sources RESET always kept during delay phase. RESET service routine vector fixed addresses FFFEh-FFFFh memory map. basic RESET sequence consists phases shown Figure Active Phase depending RESET source 4096 clock cycle delay (selected option byte) RESET vector fetch 4096 clock cycle delay allows oscillator stabilise ensures that recovery taken place from Reset state. shorter longer clock cycle delay should selected option byte correspond stabilization time external oscillator used application. RESET vector fetch phase duration clock cycles. Figure RESET Sequence Phases 5.2.2 Asynchronous External RESET RESET both input open-drain output with integrated weak pull-up resistor. This pull-up fixed value varies accordance with input voltage. pulled external circuitry reset device. Electrical Characteristic section more details. RESET signal originating from external source must have duration least th(RSTL)in order recognized. This detection asynchronous therefore enter reset state even HALT mode. RESET asynchronous signal which plays major role performance. noisy environment, recommended follow guidelines mentioned electrical characteristics section. 5.2.3 External Power-On RESET start microcontroller correctly, user must ensure means external reset circuit that reset signal held until over minimum level specified selected fOSC frequency. proper reset signal slow rising supply generally provided external network connected RESET pin. 5.2.4 Internal Watchdog RESET Starting from Watchdog counter underflow, device RESET acts output that pulled during least tw(RSTL)out.
RESET
Active Phase INTERNAL RESET 4096 CLOCK CYCLES FETCH VECTOR
Figure Reset Block Diagram
RESET
Filter INTERNAL RESET
PULSE GENERATOR
WATCHDOG RESET
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INTERRUPTS
INTRODUCTION enhanced interrupt management provides following features: Hardware interrupts Software interrupt (TRAP) Nested concurrent interrupt management with flexible interrupt priority level management: software programmable nesting levels interrupt vectors fixed hardware maskable events: RESET, TRAP This interrupt management based register (I1:0), Interrupt software priority registers (ISPRx), Fixed interrupt vector addresses located high addresses memory (FFE0h FFFFh) sorted hardware priority order. This enhanced interrupt controller guarantees full upward compatibility with standard (not nested) interrupt controller. MASKING PROCESSING FLOW interrupt masking managed bits register ISPRx registers which give interrupt software priority level each interrupt vector (see Table processing flow shown Figure Figure Interrupt Processing Flowchart
RESET PENDING INTERRUPT TRAP Interrupt same lower software priority than current I1:0 Interrupt higher software priority than current
When interrupt request serviced: Normal processing suspended current instruction execution. registers saved onto stack. bits register according corresponding values ISPRx registers serviced interrupt vector. then loaded with interrupt vector interrupt service first instruction interrupt service routine fetched (refer "Interrupt Mapping" table vector addresses). interrupt service routine should with IRET instruction which causes contents saved registers recovered from stack. Note: consequence IRET instruction, bits will restored from stack program previous level will resume. Table Interrupt Software Priority Levels
Interrupt software priority Level (main) Level Level Level interrupt disable) Level
High
FETCH NEXT INSTRUCTION
INTERRUPT STAYS PENDING
"IRET"
RESTORE FROM STACK
EXECUTE INSTRUCTION
STACK LOAD I1:0 FROM INTERRUPT REG. LOAD FROM INTERRUPT VECTOR
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INTERRUPTS (Cont'd) Servicing Pending Interrupts several interrupts pending same time, interrupt taken into account determined following two-step process: highest software priority interrupt serviced, several interrupts have same software priority then interrupt with highest hardware priority serviced first. Figure describes this decision process. Figure Priority Decision Process
PENDING INTERRUPTS
vector loaded register bits disable interrupts (level These sources allow processor exit HALT mode. TRAP (Non Maskable Software Interrupt) This software interrupt serviced when TRAP instruction executed. will serviced according flowchart Figure RESET RESET source highest priority ST7. This means that first current routine highest software priority (level highest hardware priority. RESET chapter more details. Maskable Sources Maskable interrupt vector sources serviced corresponding interrupt enabled interrupt software priority ISPRx registers) higher than currently being serviced register). these conditions false, interrupt latched thus remains pending. External Interrupts External interrupts allow processor exit from HALT power mode. External interrupt sensitivity software selectable through External Interrupt Control register (EICR). External interrupt triggered edge will latched interrupt request automatically cleared upon entering interrupt service routine. several input pins group connected same interrupt line selected simultaneously, these will logically ORed. Peripheral Interrupts Usually peripheral interrupts cause exit from HALT mode except those mentioned "Interrupt Mapping" table. peripheral interrupt occurs when specific flag peripheral status registers corresponding enable peripheral control register. general sequence clearing interrupt based access status register followed read write associated register. Note: clearing sequence resets internal latch. pending interrupt (i.e. waiting being serviced) will therefore lost clear sequence executed.
Same
SOFTWARE PRIORITY
Different
HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED
When interrupt request serviced immediately, latched then processed when software priority combined with hardware priority becomes highest one. Note hardware priority exclusive while software not. This allows previous process succeed with only interrupt. Note RESET TRAP considered having highest software priority decision process. Different Interrupt Vector Sources interrupt source types managed interrupt controller: non-maskable type (RESET,TRAP) maskable type (external from internal peripherals). Non-Maskable Sources These sources processed regardless state bits register (see Figure 13). After stacking registers (except RESET), corresponding
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INTERRUPTS (Cont'd) INTERRUPTS POWER MODES interrupts allow processor exit WAIT power mode. contrary, only external other specified interrupts allow processor exit from HALT modes (see column "Exit from HALT" "Interrupt Mapping" table). When several pending interrupts present while exiting HALT mode, first serviced only interrupt with exit from HALT mode capability selected through same decision process shown Figure Note: interrupt, that able Exit from HALT mode, pending with highest priority when exiting HALT mode, this interrupt serviced after first serviced. Figure Concurrent Interrupt Management
TRAP SOFTWARE PRIORITY LEVEL
CONCURRENT NESTED MANAGEMENT following Figure Figure show different interrupt management modes. first called concurrent mode does allow interrupt interrupted, unlike nested mode Figure interrupt hardware priority given this order from lowest highest: MAIN, IT4, IT3, IT2, IT1, IT0. software priority given each interrupt. Warning: stack overflow occur without notifying software failure.
HARDWARE PRIORITY
TRAP MAIN MAIN
Figure Nested Interrupt Management
TRAP
SOFTWARE PRIORITY LEVEL
HARDWARE PRIORITY
TRAP MAIN MAIN
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USED STACK BYTES
USED STACK BYTES
ST72323
INTERRUPTS (Cont'd) INTERRUPT REGISTER DESCRIPTION REGISTER INTERRUPT BITS Read/Write Reset Value: 111x 1010 (xAh)
ISPR0
INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX) Read/Write (bit ISPR3 read only) Reset Value: 1111 1111 (FFh)
I1_3 I1_7 I0_3 I0_7 I1_2 I1_6 I0_2 I0_6 I1_1 I1_5 I0_1 I0_5 I0_9 I1_0 I1_4 I1_8 I0_0 I0_4 I0_8
Software Interrupt Priority These bits indicate current interrupt software priority.
Interrupt Software Priority Level (main) Level Level Level interrupt disable*) Level
ISPR1 ISPR2 ISPR3
I1_11 I0_11 I1_10 I0_10 I1_9
I1_13 I0_13 I1_12 I0_12
High
These bits set/cleared hardware when entering interrupt. loaded value given corresponding bits interrupt software priority registers (ISPRx). They also set/cleared software with RIM, SIM, HALT, WFI, IRET PUSH/POP instructions (see "Interrupt Dedicated Instruction Set" table). *Note:TRAP RESET events interrupt level program.
These four registers contain interrupt software priority each interrupt vector. Each interrupt vector (except RESET TRAP) corresponding bits these registers where software priority stored. This correspondance shown following table.
Vector address FFFBh-FFFAh FFF9h-FFF8h FFE1h-FFE0h ISPRx bits I1_0 I0_0 bits* I1_1 I0_1 bits I1_13 I0_13 bits
Each I1_x I0_x value ISPRx registers same meaning bits register. Level written (I1_x=1, I0_x=0). this case, previously stored value kept. (example: previous=CFh, write=64h, result=44h) RESET, TRAP vectors have software priorities. When serviced, bits register both set. Caution: I1_x I0_x bits modified while interrupt executed following behaviour considered: interrupt still pending (new interrupt flag cleared) software priority higher than previous one, interrupt re-entered. Otherwise, software priority stays unchanged next interrupt request (after IRET interrupt
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INTERRUPTS (Cont'd)
Table Dedicated Interrupt Instruction
Instruction HALT IRET JRNM TRAP Description Entering Halt mode Interrupt routine return Jump I1:0=11 (level Jump I1:0<>11 from Stack Enable interrupt (level set) Disable interrupt (level set) Software trap Wait interrupt I1:0=11 I1:0<>11 Load I1:0 Load I1:0 Software Function/Example
Note: During execution interrupt routine, HALT, POPCC, RIM, instructions change current software priority next IRET instruction previously mentioned instructions.
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INTERRUPTS (Cont'd) Table Interrupt Mapping
Exit from Priority HALT/ Order ACTIVE HALT Higher Priority SPICSR TASR TBSR Lower Priority
Source Block
Description
Register Label
Address Vector
RESET TRAP TIMER TIMER MCC/RTC
Reset Software interrupt used Main clock controller time base interrupt External interrupt port A3.0 External interrupt port F2.0 External interrupt port B3.0 External interrupt port B7.4 used peripheral interrupts TIMER peripheral interrupts TIMER peripheral interrupts used used
FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h
MCCSR
EXTERNAL INTERRUPTS 6.6.1 Port Interrupt Sensitivity external interrupt sensitivity controlled IPA, ISxx bits EICR register (Figure 17). This control allows have fully independent external interrupt source sensitivities. Each external interrupt source generated four five) different events pin: Falling edge Rising edge Falling rising edge
Falling edge level Rising edge high level (only ei2) guarantee correct functionality, sensitivity bits EICR register modified only when bits register both (level This means that interrupts must disabled before changing sensitivity. pending interrupts cleared writing different value ISx[1:0], bits EICR.
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Figure External Interrupt Control bits
PORT INTERRUPT PAOR.3 PADDR.3
EICR IS20 IS21 INTERRUPT SOURCE
SENSITIVITY CONTROL
PORT [2:0] INTERRUPTS PFOR.2 PFDDR.2 EICR IS20 IS21
SENSITIVITY CONTROL
INTERRUPT SOURCE
PORT [3:0] INTERRUPTS PBOR.3 PBDDR.3
EICR IS10 IS11
SENSITIVITY CONTROL
INTERRUPT SOURCE
PORT INTERRUPT PBOR.4 PBDDR.4
EICR IS10 IS11 INTERRUPT SOURCE
SENSITIVITY CONTROL
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INTERRUPTS (Cont'd) EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read/Write Reset Value: 0000 0000 (00h)
IS11 IS10 IS21 IS20
IS2[1:0] sensitivity interrupt sensitivity, defined using IS2[1:0] bits, applied following external interrupts:
(port A3.0) IS1[1:0] sensitivity interrupt sensitivity, defined using IS1[1:0] bits, applied following external interrupts: (port B3.0)
External Interrupt Sensitivity IS11 IS10 Falling edge level Rising edge only Falling edge only Rising edge high level Falling edge only Rising edge only External Interrupt Sensitivity IS21 IS20 Falling edge level Rising edge only Falling edge only Rising edge high level Falling edge only Rising edge only
Rising falling edge
Rising falling edge
(port F2.0)
IS21 IS20 External Interrupt Sensitivity Falling edge level Rising edge only Falling edge only Rising falling edge
(port
IS11 IS10 External Interrupt Sensitivity Falling edge level Rising edge only Falling edge only Rising falling edge
These bits written only when register both (level Interrupt polarity port This used invert sensitivity port [3:0] external interrupts. cleared software only when register both (level sensitivity inversion Sensitivity inversion Bits Reserved, must always kept cleared.
These bits written only when register both (level Interrupt polarity port This used invert sensitivity port [3:0] external interrupts. cleared software only when register both (level sensitivity inversion Sensitivity inversion
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INTERRUPTS (Cont'd) Table Nested Interrupts Register Reset Values
Address (Hex.) 0024h Register Label ISPR0 Reset Value ISPR1 Reset Value ISPR2 Reset Value ISPR3 Reset Value EICR Reset Value I1_3 0025h I1_7 I1_11 I0_7 I0_11 I1_6 I1_10 I0_6 I0_10 I0_3 I1_2 I0_2 I1_1 I1_5 I0_5 TIMER I1_9 I0_9 I1_13 IS20 I0_13 I0_1 I1_4 I0_4 TIMER I1_8 I0_8 I1_12 I0_12
0026h
0027h 0028h
IS11
IS10
IS21
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POWER SAVING MODES
INTRODUCTION give large measure flexibility application terms power consumption, four main power saving modes implemented (see Figure 18): SLOW, WAIT (SLOW WAIT), ACTIVE HALT HALT. After RESET normal operating mode selected default (RUN mode). This mode drives device (CPU embedded peripherals) means master clock which based main oscillator frequency divided multiplied (fOSC2). From mode, different power saving modes selected setting relevant register bits calling specific software instruction whose action depends oscillator status. Figure Power Saving Mode Transitions
High
fOSC2/2 fOSC2/4 fOSC2
SLOW MODE This mode targets: reduce power consumption decreasing internal clock device, adapt internal clock frequency (fCPU) available supply voltage. SLOW mode controlled three bits MCCSR register: which enables disables Slow mode bits which select internal slow frequency (fCPU). this mode, master clock frequency (fOSC2) divided peripherals clocked this lower frequency (fCPU). Note: SLOW-WAIT mode activated when entering WAIT mode while device already SLOW mode. Figure SLOW Mode Clock Transitions
SLOW MCCSR WAIT SLOW WAIT ACTIVE HALT HALT POWER CONSUMPTION
fCPU
fOSC2 CP1:0
SLOW FREQUENCY REQUEST
NORMAL MODE REQUEST
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POWER SAVING MODES (Cont'd) WAIT MODE WAIT mode places power consumption mode stopping CPU. This power saving mode selected calling `WFI' instruction. peripherals remain active. During WAIT mode, I[1:0] bits register forced `10', enable interrupts. other registers memory remain unchanged. remains WAIT mode until interrupt RESET occurs, whereupon Program Counter branches starting address interrupt Reset service routine. will remain WAIT mode until Reset Interrupt occurs, causing wake Refer Figure Figure WAIT Mode Flow-chart
OSCILLATOR PERIPHERALS I[1:0] BITS
INSTRUCTION
RESET INTERRUPT OSCILLATOR PERIPHERALS I[1:0] BITS
4096 CLOCK CYCLE DELAY
OSCILLATOR PERIPHERALS I[1:0] BITS
FETCH RESET VECTOR SERVICE INTERRUPT
Note: Before servicing interrupt, register pushed stack. I[1:0] bits register current software priority level interrupt routine recovered when register popped.
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POWER SAVING MODES (Cont'd) ACTIVE-HALT HALT MODES ACTIVE-HALT HALT modes lowest power consumption modes MCU. They both entered executing `HALT' instruction. decision enter either ACTIVE-HALT HALT mode given MCC/RTC interrupt enable flag (OIE MCCSR register).
MCCSR Power Saving Mode entered when HALT instruction executed HALT mode ACTIVE-HALT mode
pending option byte). Otherwise, enters HALT mode remaining tDELAY period. Figure ACTIVE-HALT Timing Overview
ACTIVE 4096 HALT CYCLE DELAY RESET INTERRUPT
HALT INSTRUCTION [MCCSR.OIE=1]
FETCH VECTOR
Figure ACTIVE-HALT Mode Flow-chart 7.4.1 ACTIVE-HALT MODE ACTIVE-HALT mode lowest power consumption mode with real time clock available. entered executing `HALT' instruction when Main Clock Controller Status register (MCCSR) (see Section page more details MCCSR register). exit ACTIVE-HALT mode reception either MCC/RTC interrupt, specific interrupt (see Table "Interrupt Mapping," page RESET. When exiting ACTIVEHALT mode means interrupt, 4096 cycle delay occurs. resumes operation servicing interrupt fetching reset vector which woke (see Figure 22). When entering ACTIVE-HALT mode, I[1:0] bits register forced `10b' enable interrupts. Therefore, interrupt pending, wakes immediately. ACTIVE-HALT mode, only main oscillator associated counter (MCC/RTC) running keep wake-up time base. other peripherals clocked except those which their clock supply from another clock generator (such external auxiliary oscillator). safeguard against staying locked ACTIVEHALT mode provided oscillator interrupt. Note: soon interrupt capability oscillators selected (MCCSR.OIE set), entering ACTIVE-HALT mode while Watchdog active does generate RESET. This means that device cannot spend more than defined delay this power saving mode. CAUTION: When exiting ACTIVE-HALT mode following interrupt, MCCSR register must cleared before tDELAY after interrupt occurs (tDELAY 4096 tCPU delay deHALT INSTRUCTION (MCCSR.OIE=1) OSCILLATOR PERIPHERALS I[1:0] BITS
RESET
INTERRUPT
OSCILLATOR PERIPHERALS I[1:0] BITS
4096 CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS I[1:0] BITS
FETCH RESET VECTOR SERVICE INTERRUPT
Notes: This delay occurs only exits ACTIVEHALT mode means RESET. Peripheral clocked with external clock source still active. Only MCC/RTC interrupt some specific interrupts exit from ACTIVE-HALT mode (such external interrupt). Refer Table "Interrupt Mapping," page more details. Before servicing interrupt, register pushed stack. I[1:0] bits register current software priority level interrupt routine restored when register popped.
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POWER SAVING MODES (Cont'd) 7.4.2 HALT MODE HALT mode lowest power consumption mode MCU. entered executing `HALT' instruction when Main Clock Controller Status register (MCCSR) cleared (see Section page more details MCCSR register). exit HALT mode reception either specific interrupt (see Table "Interrupt Mapping," page RESET. When exiting HALT mode means RESET interrupt, oscillator immediately turned 4096 cycle delay used stabilize oscillator. After start delay, resumes operation servicing interrupt fetching reset vector which woke (see Figure 24). When entering HALT mode, I[1:0] bits register forced `10b'to enable interrupts. Therefore, interrupt pending, wakes immediately. HALT mode, main oscillator turned causing internal processing stopped, including operation on-chip peripherals. peripherals clocked except ones which their clock supply from another clock generator (such external auxiliary oscillator). compatibility Watchdog operation with HALT mode configured "WDGHALT" option option byte. HALT instruction when executed while Watchdog system enabled, generate Watchdog RESET (see Section 13.1 page 125) more details. Figure HALT Timing Overview
HALT 4096 CYCLE DELAY RESET INTERRUPT FETCH VECTOR FETCH RESET VECTOR SERVICE INTERRUPT
Figure HALT Mode Flow-chart
HALT INSTRUCTION (MCCSR.OIE=0) ENABLE WDGHALT WATCHDOG RESET OSCILLATOR PERIPHERALS I[1:0] BITS WATCHDOG DISABLE
RESET INTERRUPT OSCILLATOR PERIPHERALS I[1:0] BITS 4096 CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS I[1:0] BITS
HALT INSTRUCTION [MCCSR.OIE=0]
Notes: WDGHALT option bit. option byte section more details. Peripheral clocked with external clock source still active. Only some specific interrupts exit from HALT mode (such external interrupt). Refer Table "Interrupt Mapping," page more details. Before servicing interrupt, register pushed stack. I[1:0] bits register current software priority level interrupt routine recovered when register popped.
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POWER SAVING MODES (Cont'd) 7.4.2.1 Halt Mode Recommendations Make sure that external event available wake microcontroller from Halt mode. When using external interrupt wake microcontroller, reinitialize corresponding "Input Pull-up with Interrupt" before executing HALT instruction. main reason this that wrongly configured external interference unforeseen logical condition. same reason, reinitialize level sensitiveness each external interrupt precautionary measure. opcode HALT instruction 0x8E. avoid unexpected HALT instruction program counter failure, advised clear occurrences data value 0x8E from memory. example, avoid defining constant with value 0x8E. HALT instruction clears interrupt mask register allow interrupts, user choose clear pending interrupt bits before executing HALT instruction. This avoids entering other peripheral interrupt routines after executing external interrupt routine corresponding wake-up event (reset external interrupt).
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PORTS
INTRODUCTION ports offer different functional modes: transfer data through digital inputs outputs specific pins: external interrupt generation alternate signal input/output on-chip peripherals. port contains pins. Each programmed independently digital input (with without interrupt generation) digital output. FUNCTIONAL DESCRIPTION Each port main registers: Data Register (DR) Data Direction Register (DDR) optional register: Option Register (OR) Each programmed using corresponding register bits registers: corresponding port. same correspondence used register. following description takes into account register, (for specific ports which provide this register refer Port Implementation section). generic block diagram shown Figure 8.2.1 Input Modes input configuration selected clearing corresponding register bit. this case, reading register returns digital value applied external pin. Different input modes selected software through register. Notes: Writing register modifies latch value does affect status. When switching from input output mode, register written first drive correct level soon port configured output. read/modify/write instructions (BSET BRES) modify register External interrupt function When configured Input with Interrupt, event this generate external interrupt request CPU. Each independently generate interrupt request. interrupt sensitivity independently programmable using sensitivity bits EICR register. Each external interrupt vector linked dedicated group port pins (see pinout description interrupt section). several input pins selected simultaneously interrupt sources, these first detected according sensitivity bits EICR register then logically ORed. external interrupts hardware interrupts, which means that request latch (not accessible directly application) automatically cleared when corresponding interrupt vector fetched. clear unwanted pending interrupt software, sensitivity bits EICR register must modified. 8.2.2 Output Modes output configuration selected setting corresponding register bit. this case, writing register applies this digital value through latch. Then reading register returns previously stored value. different output modes selected software through register: Output push-pull open-drain. register value output status:
Push-pull Open-drain Floating
8.2.3 Alternate Functions When on-chip peripheral configured pin, alternate function automatically selected. This alternate function takes priority over standard programming. When signal coming from on-chip peripheral, automatically configured output mode (push-pull open drain according peripheral). When signal going on-chip peripheral, must configured input mode. this case, state also digitally readable addressing register. Note: Input pull-up configuration cause unexpected value input alternate peripheral input. When on-chip peripheral input output, this configured input floating mode.
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PORTS (Cont'd) Figure Port General Block Diagram
REGISTER ACCESS ALTERNATE OUTPUT ALTERNATE ENABLE
P-BUFFER (see table below) PULL-UP (see table below)
PULL-UP CONDITION implemented N-BUFFER CMOS SCHMITT TRIGGER ANALOG INPUT DIODES (see table below)
EXTERNAL INTERRUPT SOURCE (eix)
Table Port Mode Options
Configuration Mode Input Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Pull-Up P-Buffer Diodes
Output
Legend: implemented implemented activated implemented activated
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DATA
ALTERNATE INPUT
(see note)
Note: diode implemented true open drain pads. local protection between implemented protect device against positive stress.
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PORTS (Cont'd) Table Port Configurations
Hardware Configuration
IMPLEMENTED TRUE OPEN DRAIN PORTS PULL-UP CONDITION REGISTER ACCESS
REGISTER
DATA
INPUT
ALTERNATE INPUT EXTERNAL INTERRUPT SOURCE (eix) INTERRUPT CONDITION ANALOG INPUT IMPLEMENTED TRUE OPEN DRAIN PORTS
OPEN-DRAIN OUTPUT
REGISTER ACCESS
REGISTER
DATA
ALTERNATE ENABLE
ALTERNATE OUTPUT
PUSH-PULL OUTPUT
IMPLEMENTED TRUE OPEN DRAIN PORTS
REGISTER ACCESS
REGISTER
DATA
ALTERNATE ENABLE
ALTERNATE OUTPUT
Notes: When port input configuration associated alternate function enabled output, reading register will read alternate function output status. When port output configuration associated alternate function enabled input, alternate function reads status given register content.
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PORTS (Cont'd) CAUTION: alternate function must activated long configured input with interrupt, order avoid generating spurious interrupts. Analog alternate function When used input, must configured floating input. analog multiplexer (controlled registers) switches analog voltage present selected common analog rail which connected input. recommended change voltage level loading port while conversion progress. Furthermore recommended have clocking pins located close selected analog pin. WARNING: analog input voltage level must within limits stated absolute maximum ratings. PORT IMPLEMENTATION hardware implementation each port depends settings registers specific feature port such Input true open drain. Switching these ports from state another should done sequence that prevents unwanted side effects. Recommended safe transitions illustrated Figure Other transitions potentially risky should avoided, since they likely present unwanted side-effects such spurious interrupt generation.
Figure Interrupt Port State Transitions
INPUT floating/pull-up interrupt
INPUT floating (reset state)
OUTPUT open-drain
OUTPUT push-pull
DDR,
POWER MODES
Mode WAIT HALT Description effect ports. External interrupts cause device exit from WAIT mode. effect ports. External interrupts cause device exit from HALT mode.
INTERRUPTS external interrupt event generates interrupt corresponding configuration selected with registers interrupt mask register active (RIM instruction).
Interrupt Event External interrupt selected external event Enable Event Control Flag DDRx Exit from Wait Exit from Halt
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PORTS (Cont'd) 8.5.1 Port Implementation port register configurations summarised follows. Standard Ports PA5:4, PC7:0, PD5:0, PE1:0, PF7:6,
MODE floating input pull-up input open drain output push-pull output
PA3, PB3, (without pull-up)
MODE floating input floating interrupt input open drain output push-pull output
True Open Drain Ports PA7:6
MODE floating input open drain (high sink ports)
Interrupt Ports PB4, PB2:0, PF1:0 (with pull-up)
MODE floating input pull-up interrupt input open drain output push-pull output
Table Port Configuration
Port name
PA7:6 PA5:4 PB4, PB2:0 PC7:0 PD5:0 PE1:0 PF7:6, PF1:0
Input
floating floating floating floating floating floating floating floating floating floating floating pull-up floating interrupt floating interrupt pull-up interrupt pull-up pull-up pull-up pull-up floating interrupt pull-up interrupt
Output
true open-drain open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull open drain push-pull
Port
Port Port Port Port Port
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PORTS (Cont'd) Table Port Register Reset Values
Address (Hex.) Register Label
Reset Value port registers 0000h PADR 0001h PADDR 0002h PAOR 0003h PBDR 0004h PBDDR 0005h PBOR 0006h PCDR 0007h PCDDR 0008h PCOR 0009h PDDR 000Ah PDDDR 000Bh PDOR 000Ch PEDR 000Dh PEDDR 000Eh PEOR 000Fh PFDR 0010h PFDDR 0011h PFOR
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ON-CHIP PERIPHERALS
WATCHDOG TIMER (WDG) 9.1.1 Introduction Watchdog timer used detect occurrence software fault, usually generated external interference unforeseen logical conditions, which causes application program abandon normal sequence. Watchdog circuit generates reset expiry programmed time period, unless program refreshes counter's contents before becomes cleared. 9.1.2 Main Features Programmable free-running downcounter Programmable reset Reset watchdog activated) when reaches zero Optional reset HALT instruction (configurable option byte) Hardware Watchdog selectable option byte 9.1.3 Functional Description counter value stored Watchdog Control register (WDGCR bits T[6:0]), decremented every 16384 fOSC2 cycles (approx.), length timeout period programmed user increments. watchdog activated (the WDGA set) when 7-bit timer (bits T[6:0]) rolls over from becomes cleared), initiates reset cycle pulling reset typically 500ns. application program must write WDGCR register regular intervals during normal operation prevent reset. This downcounter free-running: counts down even watchdog disabled. value stored WDGCR register must between C0h: WDGA (watchdog enabled) prevent generating immediate reset T[5:0] bits contain number increments which represents time delay before watchdog produces reset (see Figure Approximate Timeout Duration). timing varies between minimum maximum value unknown status prescaler when writing WDGCR register (see Figure 29). Following reset, watchdog disabled. Once activated cannot disabled, except reset. used generate software reset (the WDGA cleared). watchdog activated, HALT instruction will generate Reset.
Figure Watchdog Block Diagram
RESET
fOSC2 MCC/RTC
WATCHDOG CONTROL REGISTER (WDGCR) WDGA
6-BIT DOWNCOUNTER (CNT)
12-BIT COUNTER
TB[1:0] bits (MCCSR Register)
PRESCALER
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WATCHDOG TIMER (Cont'd) 9.1.4 Program Watchdog Timeout Figure shows linear relationship between 6-bit value loaded Watchdog Counter (CNT) resulting timeout duration milliseconds. This used quick calculation without taking timing variations into account. Figure Approximate Timeout Duration
more precision needed, formulae Figure Caution: When writing WDGCR register, always write avoid generating immediate reset.
Value (hex.)
Watchdog timeout (ms) MHz. fOSC2
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WATCHDOG TIMER (Cont'd) Figure Exact Timeout Duration (tmin tmax) WHERE: tmin0 (LSB 128) tOSC2 tmax0 16384 tOSC2 tOSC2 125ns fOSC2=8 Value T[5:0] bits WDGCR register bits) values from table below depending timebase selected TB[1:0] bits MCCSR register
(MCCSR Reg.) (MCCSR Reg.) Selected MCCSR Timebase 10ms 25ms
calculate minimum Watchdog Timeout (tmin):
THEN
min0 16384 osc2 osc2
ELSE min0 16384 4CNT 4CNT calculate maximum Watchdog Timeout (tmax):
THEN max0 16384 osc2 ELSE max0 16384 4CNT 4CNT
osc2
Note: above formulae, division results must rounded down next integer value. Example: With timeout selected MCCSR register
Value T[5:0] Bits WDGCR Register (Hex.) Min. Watchdog Timeout (ms) tmin 1.496 Max. Watchdog Timeout (ms) tmax 2.048 128.552
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WATCHDOG TIMER (Cont'd) 9.1.5 Power Modes Mode SLOW WAIT Description effect Watchdog. effect Watchdog.
MCCSR register WDGHALT Option Byte Watchdog reset generated. enters Halt mode. Watchdog counter decremented once then stops counting longer able generate watchdog reset until receives external interrupt reset. external interrupt received, Watchdog restarts counting after 4096 clocks. reset generated, Watchdog disabled (reset state) unless Hardware Watchdog selected option byte. application recommendations Section 9.1.7 below. reset generated. reset generated. enters Active Halt mode. Watchdog counter decremented. stop counting. When receives oscillator interrupt external interrupt, Watchdog restarts counting immediately. When receives reset Watchdog restarts counting after 4096 clocks.
HALT
9.1.6 Hardware Watchdog Option Hardware Watchdog selected option byte, watchdog always active WDGA WDGCR used. Refer Option Byte description. 9.1.7 Using Halt Mode with (WDGHALT option) following recommendation applies Halt mode used when watchdog enabled. Before executing HALT instruction, refresh counter, avoid unexpected reset immediately after waking microcontroller. 9.1.8 Interrupts None.
9.1.9 Register Description CONTROL REGISTER (WDGCR) Read/Write Reset Value: 0111 1111 (7Fh)
WDGA
WDGA Activation bit. This software only cleared hardware after reset. When WDGA watchdog generate reset. Watchdog disabled Watchdog enabled Note: This used hardware watchdog option enabled option byte. T[6:0] 7-bit counter (MSB LSB). These bits contain value watchdog counter. decremented every 16384 fOSC2 cycles (approx.). reset produced when rolls over from becomes cleared).
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Table Watchdog Timer Register Reset Values
Address (Hex.) 002Ah Register Label WDGCR Reset Value WDGA
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK BEEPER (MCC/RTC) Main Clock Controller consists three different functions: programmable clock prescaler clock-out signal supply external devices real time clock timer with interrupt capability Each function used independently simultaneously. 9.2.1 Programmable Clock Prescaler programmable clock prescaler supplies clock internal peripherals. manages SLOW power saving mode (See Section SLOW MODE more details). prescaler selects fCPU main clock frequency controlled three bits MCCSR register: CP[1:0] SMS. 9.2.2 Clock-out Capability clock-out capability alternate function port that outputs fCPU clock drive external devices. controlled MCCSR register. CAUTION: When selected, clock suspends clock during ACTIVE-HALT mode. 9.2.3 Real Time Clock Timer (RTC) counter real time clock timer allows interrupt generated based accurate real time clock. Four different time bases depending directly fOSC2 available. whole functionality controlled four bits MCCSR register: TB[1:0], OIF. When interrupt enabled (OIE set), enters ACTIVE-HALT mode when HALT instruction executed. Section ACTIVE-HALT HALT MODES more details. 9.2.4 Beeper beep function controlled MCCBCR register. output three selectable frequencies BEEP (I/O port alternate function).
Figure Main Clock Controller (MCC/RTC) Block Diagram
MCCBCR BEEP BEEP SIGNAL SELECTION
12-BIT COUNTER
WATCHDOG TIMER
MCCSR fOSC2
MCC/RTC INTERRUPT
fCPU
CLOCK PERIPHERALS
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont'd) 9.2.5 Power Modes CP[1:0] clock prescaler Mode Description These bits select clock prescaler which effect MCC/RTC peripheral. applied different slow modes. Their action WAIT MCC/RTC interrupt cause device exit conditioned setting bit. These from WAIT mode. bits cleared software
ACTIVEHALT effect MCC/RTC counter (OIE set), registers frozen. MCC/RTC interrupt cause device exit from ACTIVE-HALT mode. MCC/RTC counter registers frozen. MCC/RTC operation resumes when woken interrupt with "exit from HALT" capability. fCPU SLOW mode fOSC2 fOSC2 fOSC2 fOSC2
HALT
9.2.6 Interrupts MCC/RTC interrupt event generates interrupt MCCSR register interrupt mask register active (RIM instruction).
Interrupt Event Time base overflow event Enable Event Control Flag Exit from Wait Exit from Halt
Slow mode select This cleared software. Normal mode. fCPU fOSC2 Slow mode. fCPU given CP1, Section SLOW MODE Section MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK BEEPER (MCC/RTC) more details. TB[1:0] Time base control These bits select programmable divider time base. They cleared software.
Time Base Counter Prescaler OSC2 =4MHz fOSC2=8MHz 16000 20ms 50ms 10ms 25ms 32000 80000 200000
Note: MCC/RTC interrupt wakes from ACTIVE-HALT mode, from HALT mode.
9.2.7 Register Description CONTROL/STATUS REGISTER (MCCSR) Read/Write Reset Value: 0000 0000 (00h)
modification time base taken into account current period (previously set) avoid unwanted time shift. This allows this time base real time clock. Oscillator interrupt enable This cleared software. Oscillator interrupt disabled Oscillator interrupt enabled This interrupt used exit from ACTIVEHALT mode. When this set, calling software HALT instruction enters ACTIVE-HALT power saving mode.
Main clock selection This enables alternate function port. cleared software. alternate function disabled (I/O free general-purpose I/O) alternate function enabled (fCPU port) Note: reduce power consumption, function active ACTIVE-HALT mode.
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont'd) BEEP CONTROL REGISTER (MCCBCR) Oscillator interrupt flag This hardware cleared software Read/Write reading MCCSR register. indicates when Reset Value: 0000 0000 (00h) that main oscillator reached selected elapsed time (TB1:0). Timeout reached Timeout reached CAUTION: BRES BSET instructions must used MCCSR register avoid Reserved, must kept cleared. unintentionally clearing bit. BC[1:0] Beep control These bits select beep capability.
~2-KHz ~1-KHz ~500-Hz Beep mode with fOSC2=8MHz Output Beep signal ~50% duty cycle
beep output signal available ACTIVEHALT mode disabled reduce consumption. Table Main Clock Controller Register Reset Values
Address (Hex.) 002Ch 002Dh Register Label MCCSR Reset Value MCCBCR Reset Value
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16-BIT TIMER 9.3.1 Introduction timer consists 16-bit free-running counter driven programmable prescaler. used variety purposes, including pulse length measurement input signals (input capture) generation output waveforms (output compare PWM). Pulse lengths waveform periods modulated from microseconds several milliseconds using timer prescaler clock prescaler. Some devices have on-chip 16-bit timers. They completely independent, share resources. They synchronized after reset long timer clock frequencies modified. This description covers 16-bit timers. devices with timers, register names prefixed with (Timer (Timer 9.3.2 Main Features Programmable prescaler: fCPU divided Overflow status flag maskable interrupt External clock input (must least times slower than clock speed) with choice active edge Output Compare functions each with: dedicated 16-bit registers dedicated programmable signals dedicated status flags dedicated maskable interrupt Input Capture functions each with: dedicated 16-bit registers dedicated active edge selection signals dedicated status flags dedicated maskable interrupt Pulse width modulation mode (PWM) pulse mode Reduced Power Mode alternate functions ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* Block Diagram shown Figure *Note: Some timer pins available (not bonded) some devices. Refer device description. When reading input signal non-bonded pin, value will always `1'. 9.3.3 Functional Description 9.3.3.1 Counter main block Programmable Timer 16-bit free running upcounter associated 16-bit registers. 16-bit registers made 8-bit registers called high low. Counter Register (CR): Counter High Register (CHR) most significant byte Byte). Counter Register (CLR) least significant byte Byte). Alternate Counter Register (ACR) Alternate Counter High Register (ACHR) most significant byte Byte). Alternate Counter Register (ACLR) least significant byte Byte). These read-only 16-bit registers contain same value with difference that reading ACLR register does clear (Timer overflow flag), located Status register, (SR), (see note paragraph titled 16-bit read sequence). Writing register ACLR register resets free running counter FFFCh value. Both counters have reset value FFFCh (this only value which reloaded 16-bit timer). reset value both counters also FFFCh Pulse mode mode. timer clock depends clock control bits register, illustrated Table Clock Control Bits. value counter register repeats every 131072, 262144 524288 clock cycles depending CC[1:0] bits. timer frequency fCPU/2, fCPU/4, fCPU/8 external frequency.
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16-BIT TIMER (Cont'd) Figure Timer Block Diagram
INTERNAL fCPU MCU-PERIPHERAL INTERFACE 8-bit buffer EXEDG EXTCLK COUNTER REGISTER ALTERNATE COUNTER REGISTER CC[1:0] TIMER INTERNAL OVERFLOW DETECT CIRCUIT OUTPUT COMPARE REGISTER OUTPUT COMPARE REGISTER INPUT CAPTURE REGISTER INPUT CAPTURE REGISTER high high high high
high
OUTPUT COMPARE CIRCUIT
EDGE DETECT CIRCUIT1
ICAP1
EDGE DETECT CIRCUIT2
ICAP2
LATCH1
ICF1 OCF1 ICF2 OCF2 TIMD
OCMP1 OCMP2
LATCH2
(Control/Status Register)
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
OC1E OC2E
IEDG2 EXEDG
(Control Register
(Control Register
(See note) TIMER INTERRUPT
Note: interrupt requests have separate vectors then last present (See device Interrupt Vector Table)
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16-BIT TIMER (Cont'd) 16-bit read sequence: (from either Counter Register Alternate Counter Register). Beginning sequence Read Byte Other instructions Read Byte Sequence completed user must read Byte first, then Byte value buffered automatically. This buffered value remains unchanged until 16-bit read sequence completed, even user reads Byte several times. After complete reading sequence, only register ACLR register read, they return Byte count value time read. Whatever timer mode used (input capture, output compare, pulse mode mode) overflow occurs when counter rolls over from FFFFh 0000h then: register set. timer interrupt generated TOIE register register cleared. these conditions false, interrupt remains pending issued soon they both true.
Returns buffered
Byte buffered
Byte value
Clearing overflow interrupt request done steps: Reading register while set. access (read write) register. Notes: cleared accesses ACLR register. advantage accessing ACLR register rather than register that allows simultaneous overflow function reading free running counter random times (for example, measure elapsed time) without risk clearing erroneously. timer affected WAIT mode. HALT mode, counter stops counting until mode exited. Counting then resumes from previous count (MCU awakened interrupt) from reset count (MCU awakened Reset). 9.3.3.2 External Clock external clock (where available) selected CC0=1 CC1=1 register. status EXEDG register determines type level transition external clock EXTCLK that will trigger free running counter. counter synchronized with falling edge internal clock. minimum four falling edges clock must occur between consecutive active edges external clock; thus external clock frequency must less than quarter clock frequency.
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16-BIT TIMER (Cont'd) Figure Counter Timing Diagram, internal clock divided
CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFD FFFE FFFF 0000 0001 0002 0003
Figure Counter Timing Diagram, internal clock divided
CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 0001
Figure Counter Timing Diagram, internal clock divided
CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000
Note: reset state when internal reset signal high, when running.
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16-BIT TIMER (Cont'd) 9.3.3.3 Input Capture this section, index, because there input capture functions 16-bit timer. 16-bit input capture registers (IC1R IC2R) used latch value free running counter after transition detected ICAPi (see figure
ICiR Byte ICiHR Byte ICiLR
ICiR register read-only register. active transition software programmable through IEDGi Control Registers (CRi). Timing resolution count free running counter: (fCPU/CC[1:0]). Procedure: input capture function select following register: Select timer clock (CC[1:0]) (see Table Clock Control Bits). Select edge active transition ICAP2 with IEDG2 (the ICAP2 must configured floating input input with pull-up without interrupt this configuration available). select following register: ICIE generate interrupt after input capture coming from either ICAP1 ICAP2 Select edge active transition ICAP1 with IEDG1 (the ICAP1pin must configured floating input input with pullup without interrupt this configuration available).
When input capture occurs: ICFi set. ICiR register contains value free running counter active transition ICAPi (see Figure 36). timer interrupt generated ICIE cleared register. Otherwise, interrupt remains pending until both conditions become true. Clearing Input Capture interrupt request (i.e. clearing ICFi bit) done steps: Reading register while ICFi set. access (read write) ICiLR register. Notes: After reading ICiHR register, transfer input capture data inhibited ICFi will never until ICiLR register also read. ICiR register contains free running counter value which corresponds most recent input capture. input capture functions used together even timer also uses output compare functions. pulse Mode mode only Input Capture used. alternate inputs (ICAP1 ICAP2) always directly connected timer. transitions these pins activates input capture function. Moreover ICAPi pins configured input second output, interrupt generated user toggles output ICIE set. This avoided input capture function disabled reading ICiHR (see note used with interrupt generation order measure events that beyond timer range (FFFFh).
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16-BIT TIMER (Cont'd) Figure Input Capture Block Diagram
ICAP1 ICAP2 EDGE DETECT CIRCUIT2 EDGE DETECT CIRCUIT1
ICIE
(Control Register
IEDG1
(Status Register) IC2R Register IC1R Register
ICF1 ICF2
16-BIT 16-BIT FREE RUNNING COUNTER
(Control Register
IEDG2
Figure Input Capture Timing Diagram
TIMER CLOCK COUNTER REGISTER ICAPi ICAPi FLAG ICAPi REGISTER Note: rising edge active edge. FF03 FF01 FF02 FF03
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16-BIT TIMER (Cont'd) 9.3.3.4 Output Compare this section, index, because there output compare functions 16-bit timer. This function used control output waveform indicate when period time elapsed. When match found between Output Compare register free running counter, output compare function: Assigns pins with programmable value OCiE Sets flag status register Generates interrupt enabled 16-bit registers Output Compare Register (OC1R) Output Compare Register (OC2R) contain value compared counter register each timer clock cycle.
OCiR Byte OCiHR Byte OCiLR
OCMPi takes OLVLi value (OCMPi latch forced during reset). timer interrupt generated OCIE register cleared register (CC). OCiR register value required specific timing application calculated using following formula:
OCiR
fCPU
PRESC
Where: Output compare period seconds) fCPU clock frequency hertz) PRESC Timer prescaler factor depending CC[1:0] bits, Table Clock Control Bits) timer clock external clock, formula
These registers readable writable affected timer hardware. reset event changes OCiR value 8000h. Timing resolution count free running counter: (fCPU/CC[1:0]). Procedure: output compare function, select following register: OCiE output needed then OCMPi dedicated output compare signal. Select timer clock (CC[1:0]) (see Table Clock Control Bits). select following register: Select OLVLi applied OCMPi pins after match occurs. OCIE generate interrupt needed. When match found between OCRi register register: OCFi set.
OCiR fEXT
Where:
fEXT
Output compare period seconds) External timer clock frequency hertz)
Clearing output compare interrupt request (i.e. clearing OCFi bit) done Reading register while OCFi set. access (read write) OCiLR register. following procedure recommended prevent OCFi from being between time read write OCiR register: Write OCiHR register (further compares inhibited). Read register (first step clearance OCFi bit, which already set). Write OCiLR register (enables output compare function clears OCFi bit).
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16-BIT TIMER (Cont'd) Notes: After processor write cycle OCiHR register, output compare function inhibited until OCiLR register also written. OCiE set, OCMPi general port OLVLi will appear when match found interrupt could generated OCIE set. When timer clock fCPU/2, OCFi OCMPi while counter value equals OCiR register value (see Figure page 59). This behaviour same mode. When timer clock fCPU/4, fCPU/8 external clock mode, OCFi OCMPi while counter value equals OCiR register value plus (see Figure page 59). output compare functions used both generating external events OCMPi pins even input capture mode also used. value 16-bit OCiR register OLVi should changed after each successful comparison order control output waveform establish elapsed timeout. Figure Output Compare Block Diagram
Forced Compare Output capability When FOLVi software, OLVLi copied OCMPi pin. OLVi toggled order toggle OCMPi when enabled (OCiE bit=1). OCFi then hardware, thus interrupt request generated. FOLVLi bits have effect both pulse mode mode.
FREE RUNNING COUNTER 16-bit OUTPUT COMPARE CIRCUIT 16-bit 16-bit
OC1E OC2E
(Control Register (Control Register
OCIE FOLV2 FOLV1 OLVL2 OLVL1 Latch
OCMP1 OCMP2
OC1R Register
OCF1 OCF2
Latch
OC2R Register (Status Register)
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16-BIT TIMER (Cont'd) Figure Output Compare Timing Diagram, fTIMER =fCPU/2
INTERNAL CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER (OCRi) OUTPUT COMPARE FLAG (OCFi) OCMPi (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
Figure Output Compare Timing Diagram, fTIMER =fCPU/4
INTERNAL CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER (OCRi) COMPARE REGISTER LATCH OUTPUT COMPARE FLAG (OCFi) OCMPi (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
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16-BIT TIMER (Cont'd) 9.3.3.5 Pulse Mode Pulse mode enables generation pulse when external event occurs. This mode selected register. pulse mode uses Input Capture1 function Output Compare1 function. Procedure: pulse mode: Load OC1R register with value corresponding length pulse (see formula opposite column). Select following register: Using OLVL1 bit, select level applied OCMP1 after pulse. Using OLVL2 bit, select level applied OCMP1 during pulse. Select edge active transition ICAP1 with IEDG1 (the ICAP1 must configured floating input). Select following register: OC1E bit, OCMP1 then dedicated Output Compare function. bit. Select timer clock CC[1:0] (see Table Clock Control Bits). pulse mode cycle When event occurs ICAP1 ICR1 Counter OCMP1 OLVL2 Counter reset FFFCh ICF1 When Counter OC1R
Clearing Input Capture interrupt request (i.e. clearing ICFi bit) done steps: Reading register while ICFi set. access (read write) ICiLR register. OC1R register value required specific timing application calculated using following formula: OCiR Value
fCPU
PRESC
Where: Pulse period seconds) fCPU clock frequency hertz) PRESC Timer prescaler factor depending CC[1:0] bits, Table Clock Control Bits) timer clock external clock formula OCiR fEXT Where: Pulse period seconds) External timer clock frequency hertz) fEXT When value counter equal value contents OC1R register, OLVL1 output OCMP1 pin, (See Figure 40). Notes: OCF1 cannot hardware pulse mode OCF2 generate Output Compare interrupt. When Pulse Width Modulation (PWM) Pulse Mode (OPM) bits both set, mode only active one. OLVL1=OLVL2 continuous signal will seen OCMP1 pin. ICAP1 used perform input capture. ICAP2 used perform input capture (ICF2 IC2R loaded) user must take care that counter reset each time valid edge occurs ICAP1 ICF1 also generates interrupt ICIE set. When pulse mode used OC1R dedicated this mode. Nevertheless OC2R OCF2 used indicate period time been elapsed cannot generate output waveform because level OLVL2 dedicated pulse mode.
OCMP1 OLVL1
Then, valid event ICAP1 pin, counter initialized FFFCh OLVL2 loaded OCMP1 pin, ICF1 value FFFDh loaded IC1R register. Because ICF1 when active edge occurs, interrupt generated ICIE set.
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16-BIT TIMER (Cont'd) Figure Pulse Mode Timing Example
IC1R COUNTER ICAP1 OCMP1 OLVL2 OLVL1 OLVL2 01F8 FFFC FFFD FFFE 01F8 2ED0 2ED1 2ED2 2ED3 2ED3 FFFC FFFD
compare1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure Pulse Width Modulation Mode Timing Example with Output Compare Functions
COUNTER 34E2 FFFC FFFD FFFE OCMP1 OLVL2
2ED0 2ED1 2ED2
34E2
FFFC
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2=
Note: timers with only Output Compare register, fixed frequency signal generated using output compare counter overflow define pulse length.
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16-BIT TIMER (Cont'd) 9.3.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables generation signal with frequency pulse length determined value OC1R OC2R registers. Pulse Width Modulation mode uses complete Output Compare function plus OC2R register, this functionality used when mode activated. mode, double buffering implemented output compare registers. values written OC1R OC2R registers taken into account only period (OC2) avoid spikes output (OCMP1). Procedure pulse width modulation mode: Load OC2R register with value corresponding period signal using formula opposite column. Load OC1R register with value corresponding period pulse (OLVL1=0 OLVL2=1) using formula opposite column. Select following register: Using OLVL1 bit, select level applied OCMP1 after successful comparison with OC1R register. Using OLVL2 bit, select level applied OCMP1 after successful comparison with OC2R register. Select following register: OC1E bit: OCMP1 then dedicated output compare function. bit. Select timer clock (CC[1:0]) (see Table Clock Control Bits). Pulse Width Modulation cycle When Counter OC1R
OLVL1=1 OLVL2=0 length positive pulse difference between OC2R OC1R registers. OLVL1=OLVL2 continuous signal will seen OCMP1 pin. OCiR register value required specific timing application calculated using following formula: OCiR Value
fCPU
PRESC
Where: Signal pulse period seconds) fCPU clock frequency hertz) PRESC Timer prescaler factor depending CC[1:0] bits, Table Clock Control Bits) timer clock external clock formula OCiR fEXT Where: Signal pulse period seconds) fEXT External timer clock frequency hertz) Output Compare event causes counter initialized FFFCh (See Figure Notes: After write instruction OCiHR register, output compare function inhibited until OCiLR register also written. OCF1 OCF2 bits cannot hardware mode therefore Output Compare interrupt inhibited. ICF1 hardware when counter reaches OC2R value produce timer interrupt ICIE cleared. mode ICAP1 used perform input capture because disconnected timer. ICAP2 used perform input capture (ICF2 IC2R loaded) user must take care that counter reset each period ICF1 also generates interrupt ICIE set. When Pulse Width Modulation (PWM) Pulse Mode (OPM) bits both set, mode only active one.
OCMP1 OLVL1
When Counter OC2R
OCMP1 OLVL2 Counter reset FFFCh ICF1
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16-BIT TIMER (Cont'd) 9.3.4 Power Modes
Mode WAIT Description effect 16-bit Timer. Timer interrupts cause device exit from WAIT mode. 16-bit Timer registers frozen. HALT mode, counter stops counting until Halt mode exited. Counting resumes from previous count when woken interrupt with "exit from HALT mode" capability from counter reset value when woken RESET. input capture event occurs ICAPi pin, input capture detection circuitry armed. Consequently, when woken interrupt with "exit from HALT mode" capability, ICFi set, counter value present when exiting from HALT mode captured into ICiR register.
HALT
9.3.5 Interrupts
Interrupt Event Input Capture event/Counter reset mode Input Capture event Output Compare event (not available mode) Output Compare event (not available mode) Timer Overflow event Event Flag ICF1 ICF2 OCF1 OCF2 Enable Control ICIE OCIE TOIE Exit from Wait Exit from Halt
Note: 16-bit Timer interrupt events connected same interrupt vector (see Interrupts chapter). These events generate interrupt corresponding Enable Control interrupt mask register reset (RIM instruction). 9.3.6 Summary Timer modes
MODES Input Capture and/or Output Compare and/or Pulse Mode Mode Input Capture TIMER RESOURCES Input Capture Output Compare Output Compare Partially Recommended1) Recommended3)
note Section 9.3.3.5 Pulse Mode note Section 9.3.3.5 Pulse Mode note Section 9.3.3.6 Pulse Width Modulation Mode
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16-BIT TIMER (Cont'd) 9.3.7 Register Description Each Timer associated with three control status registers, with pairs data registers (16-bit values) relating input captures, output compares, counter alternate counter. CONTROL REGISTER (CR1) Read/Write Reset Value: 0000 0000 (00h)
FOLV2 Forced Output Compare This cleared software. effect OCMP2 pin. Forces OLVL2 copied OCMP2 pin, OC2E even there successful comparison. FOLV1 Forced Output Compare This cleared software. effect OCMP1 pin. Forces OLVL1 copied OCMP1 pin, OC1E even there successful comparison. OLVL2 Output Level This copied OCMP2 whenever successful comparison occurs with OC2R register OCxE register. This value copied OCMP1 Pulse Mode Pulse Width Modulation mode. IEDG1 Input Edge This determines which type level transition ICAP1 will trigger capture. falling edge triggers capture. rising edge triggers capture. OLVL1 Output Level OLVL1 copied OCMP1 whenever successful comparison occurs with OC1R register OC1E register.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
ICIE Input Capture Interrupt Enable. Interrupt inhibited. timer interrupt generated whenever ICF1 ICF2 register set. OCIE Output Compare Interrupt Enable. Interrupt inhibited. timer interrupt generated whenever OCF1 OCF2 register set. TOIE Timer Overflow Interrupt Enable. Interrupt inhibited. timer interrupt enabled whenever register set.
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16-BIT TIMER (Cont'd) CONTROL REGISTER (CR2) Read/Write Reset Value: 0000 0000 (00h)
OC1E OC2E IEDG2 EXEDG
Pulse Width Modulation. mode active. mode active, OCMP1 outputs programmable cyclic signal; length pulse depends value OC1R register; period depends value OC2R register. CC[1:0] Clock Control. timer clock mode depends these bits: Table Clock Control Bits
Timer Clock fCPU fCPU fCPU External Clock (where available)
OC1E Output Compare Enable. This used only output signal from timer OCMP1 (OLV1 Output Compare mode, both OLV1 OLV2 one-pulse mode). Whatever value OC1E bit, Output Compare function timer remains active. OCMP1 alternate function disabled (I/O free general-purpose I/O). OCMP1 alternate function enabled. OC2E Output Compare Enable. This used only output signal from timer OCMP2 (OLV2 Output Compare mode). Whatever value OC2E bit, Output Compare function timer remains active. OCMP2 alternate function disabled (I/O free general-purpose I/O). OCMP2 alternate function enabled. Pulse Mode. Pulse Mode active. Pulse Mode active, ICAP1 used trigger pulse OCMP1 pin; active transition given IEDG1 bit. length generated pulse depends contents OC1R register.
Note: external clock available, programming external clock configuration stops counter. IEDG2 Input Edge This determines which type level transition ICAP2 will trigger capture. falling edge triggers capture. rising edge triggers capture. EXEDG External Clock Edge. This determines which type level transition external clock EXTCLK will trigger counter register. falling edge triggers counter register. rising edge triggers counter register.
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16-BIT TIMER (Cont'd) CONTROL/STATUS REGISTER (CSR) Read/Write (bits read only) Reset Value: xxxx x0xx (xxh)
ICF1 OCF1 ICF2 OCF2 TIMD
Note: Reading writing ACLR register does clear TOF. ICF2 Input Capture Flag input capture (reset value). input capture occurred ICAP2 pin. clear this bit, first read register, then read write byte IC2R (IC2LR) register. OCF2 Output Compare Flag match (reset value). content free running counter matched content OC2R register. clear this bit, first read register, then read write byte OC2R (OC2LR) register. TIMD Timer disable. This cleared software. When set, freezes timer prescaler counter disabled output functions (OCMP1 OCMP2 pins) reduce power consumption. Access timer registers still available, allowing timer configuration changed, counter reset, while disabled. Timer enabled Timer prescaler, counter outputs disabled Bits Reserved, must kept cleared.
ICF1 Input Capture Flag input capture (reset value). input capture occurred ICAP1 counter reached OC2R value mode. clear this bit, first read register, then read write byte IC1R (IC1LR) register. OCF1 Output Compare Flag match (reset value). content free running counter matched content OC1R register. clear this bit, first read register, then read write byte OC1R (OC1LR) register. Timer Overflow Flag. timer overflow (reset value). free running counter rolled over from FFFFh 0000h. clear this bit, first read register, then read write byte (CLR) register.
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16-BIT TIMER (Cont'd) INPUT CAPTURE HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This 8-bit read only register that contains high part counter value (transferred input capture event).
OUTPUT COMPARE HIGH REGISTER (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This 8-bit register that contains high part value compared register.
INPUT CAPTURE REGISTER (IC1LR) Read Only Reset Value: Undefined This 8-bit read only register that contains part counter value (transferred input capture event).
OUTPUT COMPARE REGISTER (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This 8-bit register that contains part value compared register.
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16-BIT TIMER (Cont'd) OUTPUT COMPARE HIGH REGISTER (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This 8-bit register that contains high part value compared register.
ALTERNATE COUNTER HIGH REGISTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This 8-bit register that contains high part counter value.
OUTPUT COMPARE REGISTER (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This 8-bit register that contains part value compared register.
ALTERNATE COUNTER REGISTER (ACLR) Read Only Reset Value: 1111 1100 (FCh) This 8-bit register that contains part counter value. write this register resets counter. access this register after access register does clear register.
COUNTER HIGH REGISTER (CHR) Read Only Reset Value: 1111 1111 (FFh) This 8-bit register that contains high part counter value.
INPUT CAPTURE HIGH REGISTER (IC2HR) Read Only Reset Value: Undefined This 8-bit read only register that contains high part counter value (transferred Input Capture event).
COUNTER REGISTER (CLR) Read Only Reset Value: 1111 1100 (FCh) This 8-bit register that contains part counter value. write this register resets counter. access this register after accessing register clears bit.
INPUT CAPTURE REGISTER (IC2LR) Read Only Reset Value: Undefined This 8-bit read only register that contains part counter value (transferred Input Capture event).
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16-BIT TIMER (Cont'd) Table 16-Bit Timer Register Reset Values
Address (Hex.) Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Register Label Reset Value Reset Value Reset Value IC1HR Reset Value IC1LR Reset Value OC1HR Reset Value OC1LR Reset Value OC2HR Reset Value OC2LR Reset Value Reset Value Reset Value ACHR Reset Value ACLR Reset Value IC2HR Reset Value IC2LR Reset Value ICIE OC1E ICF1 OCIE OC2E OCF1 TOIE FOLV21 ICF2 FOLV1 OCF2 OLVL2 TIMD IEDG1 IEDG2 OLVL1 EXEDG
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SERIAL PERIPHERAL INTERFACE (SPI) 9.4.1 Introduction Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. system consist master more slaves however interface master multi-master system. 9.4.2 Main Features Full duplex synchronous transfers lines) Simplex synchronous transfers lines) Master slave operation master mode frequencies (fCPU/4 max.) fCPU/2 max. slave mode frequency (see note) Management software hardware Programmable clock polarity phase transfer interrupt flag Write collision, Master Mode Fault Overrun flags Note: slave mode, continuous transmission possible maximum frequency software overhead clearing status flags initiate next transmission sequence. 9.4.3 General Description Figure shows serial peripheral interface (SPI) block diagram. There registers: Control Register (SPICR) Control/Status Register (SPICSR) Data Register (SPIDR) connected external devices through pins: MISO: Master Slave data MOSI: Master Slave data SCK: Serial Clock masters input slaves
Figure Serial Peripheral Interface Block Diagram
Data/Address SPIDR Read Read Buffer Interrupt request
MOSI MISO
8-Bit Shift Register
SPIF WCOL MODF
SPICSR
Write
STATE CONTROL
SPIE
SPICR
SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER CONTROL SERIAL CLOCK GENERATOR
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SERIAL PERIPHERAL INTERFACE (Cont'd) Slave select: This input signal acts `chip select' master communicate with slaves individually avoid contention data lines. Slave inputs driven standard ports master MCU. 9.4.3.1 Functional Description basic example interconnections between single master single slave illustrated Figure MOSI pins connected together MISO pins connected together. this data transferred serially between master slave (most significant first). Figure Single Master/ Single Slave Application
communication always initiated master. When master device transmits data slave device MOSI pin, slave device responds sending data master device MISO pin. This implies full duplex communication with both data data synchronized with same clock signal (which provided master device pin). single data line, MISO MOSI pins must connected each node this case only simplex communication possible). Four possible data/clock timing relationships chosen (see Figure master slave must programmed with same timing mode.
MASTER MSBit LSBit MISO MISO MSBit
SLAVE LSBit
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
MOSI
MOSI
CLOCK GENERATOR
used managed software
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SERIAL PERIPHERAL INTERFACE (Cont'd) 9.4.3.2 Slave Select Management alternative using control Slave Select signal, application choose manage Slave Select signal software. This configured SPICSR register (see Figure software management, external free other application uses internal signal level driven writing SPICSR register. Master mode: internal must held high continuously
Slave Mode: There cases depending data/clock timing relationship (see Figure 44): CPHA=1 (data latched clock edge): internal must held during entire transmission. This implies that single slave applications either tied VSS, made free standard managing function software (SSM= SSI=0 SPICSR register) CPHA=0 (data latched clock edge): internal must held during byte transmission pulled high between each byte allow slave write shift register. pulled high, Write Collision error will occur when slave writes shift register (see Section 9.4.5.3).
Figure Generic Timing Diagram
MOSI/MISO Master Slave CPHA=0) Slave CPHA=1)
Byte
Byte
Byte
Figure Hardware/Software Slave Select Management
external
internal
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SERIAL PERIPHERAL INTERFACE (Cont'd) 9.4.3.3 Master Mode Operation master mode, serial clock output pin. clock frequency, polarity phase configured software (refer description SPICSR register). Note: idle state must correspond polarity selected SPICSR register pulling CPOL=1 pulling down CPOL=0). operate master mode, perform following steps order: Write SPICR register: Select clock frequency configuring SPR[2:0] bits. Select clock polarity clock phase configuring CPOL CPHA bits. Figure shows four possible configurations. Note: slave must have same CPOL CPHA settings master. Write SPICSR register: Either clear high complete byte transmit sequence. Write SPICR register: MSTR bits Note: MSTR bits remain only high). Important note: SPICSR register written first, SPICR register setting (MSTR bit) taken into account. transmit sequence begins when software writes byte SPIDR register. 9.4.3.4 Master Mode Transmit Sequence When software writes SPIDR register, data byte loaded into 8-bit shift register then shifted serially MOSI most significant first. When data transfer complete: SPIF hardware interrupt request generated SPIE interrupt mask register cleared. Clearing SPIF performed following software sequence: access SPICSR register while SPIF read SPIDR register.
Note: While SPIF set, writes SPIDR register inhibited until SPICSR register read. 9.4.3.5 Slave Mode Operation slave mode, serial clock received from master device. operate slave mode: Write SPICSR register perform following actions: Select clock polarity clock phase configuring CPOL CPHA bits (see Figure 46). Note: slave must have same CPOL CPHA settings master. Manage described Section 9.4.3.2 Figure CPHA=1 must held continuously. CPHA=0 must held during byte transmission pulled between each byte slave write shift register. Write SPICR register clear MSTR enable functions. 9.4.3.6 Slave Mode Transmit Sequence When software writes SPIDR register, data byte loaded into 8-bit shift register then shifted serially MISO most significant first. transmit sequence begins when slave device receives clock signal most significant data MOSI pin. When data transfer complete: SPIF hardware interrupt request generated SPIE interrupt mask register cleared. Clearing SPIF performed following software sequence: access SPICSR register while SPIF set. write read SPIDR register. Notes: While SPIF set, writes SPIDR register inhibited until SPICSR register read. SPIF cleared during second transmission; however, must cleared before second SPIF order prevent Overrun condition (see Section 9.4.5.2).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 9.4.4 Clock Phase Clock Polarity Four possible timing relationships chosen software, using CPOL CPHA bits (See Figure 46). Note: idle state must correspond polarity selected SPICSR register pulling CPOL=1 pulling down CPOL=0). combination CPOL clock polarity CPHA (clock phase) bits selects data capture clock edge Figure Data Clock Timing Diagram
Figure shows transfer with four combinations CPHA CPOL bits. diagram interpreted master slave timing diagram where pin, MISO pin, MOSI directly connected between master slave device. Note: CPOL changed communication byte boundaries, must disabled resetting bit.
CPHA
(CPOL (CPOL
MISO (from master) MOSI (from slave) slave)
CAPTURE STROBE
MSBit
Bit3
LSBit
MSBit
Bit3
LSBit
CPHA
(CPOL (CPOL
MISO (from master) MOSI (from slave) slave)
CAPTURE STROBE
MSBit
Bit3
LSBit
MSBit
Bit3
LSBit
Note: This figure should used replacement parametric information. Refer Electrical Characteristics chapter.
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SERIAL PERIPHERAL INTERFACE (Cont'd) 9.4.5 Error Flags 9.4.5.1 Master Mode Fault (MODF) Master mode fault occurs when master device pulled low. When Master mode fault occurs: MODF interrupt request generated SPIE set. reset. This blocks output from device disables peripheral. MSTR reset, thus forcing device into slave mode. Clearing MODF done through software sequence: read access SPICSR register while MODF set. write SPICR register. Notes: avoid conflicts application with multiple slaves, must pulled high during MODF clearing sequence. MSTR bits restored their original state during after this clearing sequence. Hardware does allow user MSTR bits while MODF except MODF clearing sequence. 9.4.5.2 Overrun Condition (OVR) overrun condition occurs, when master device sent data byte slave device
cleared SPIF issued from previously transmitted byte. When Overrun occurs: interrupt request generated SPIE set. this case, receiver buffer contains byte sent after SPIF last cleared. read SPIDR register returns this byte. other bytes lost. cleared reading SPICSR register. 9.4.5.3 Write Collision Error (WCOL) write collision occurs when software tries write SPIDR register while data transfer taking place with external device. When this happens, transfer continues uninterrupted; software write will unsuccessful. Write collisions occur both master slave mode. also Section 9.4.3.2 Slave Select Management. Note: "read collision" will never occur since received data byte placed buffer which access always synchronous with operation. WCOL SPICSR register write collision occurs. interrupt generated when WCOL (the WCOL status flag only). Clearing WCOL done through software sequence (see Figure 47).
Figure Clearing WCOL (Write Collision Flag) Software Sequence Clearing sequence after SPIF (end data byte transfer) Step Read SPICSR
RESULT
Step
Read SPIDR
SPIF WCOL=0
Clearing sequence before SPIF (during data byte transfer) Step Step Read SPICSR
RESULT
Read SPIDR
WCOL=0
Note: Writing SPIDR register instead reading does reset WCOL
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SERIAL PERIPHERAL INTERFACE (Cont'd) 9.4.5.4 Single Master Systems typical single master system configured, using master four MCUs slaves (see Figure 48). master device selects individual slave devices using four pins parallel port control four pins slave devices. pins pulled high during reset since master device ports will forced inputs that time, thus disabling slave devices.
Note: prevent conflict MISO line master allows only active slave device during transmission. more security, slave device respond master with received data byte. Then master will receive previous byte back from slave device MISO MOSI pins connected slave written SPIDR register. Other transmission security methods ports handshake lines data bytes with command fields.
Figure Single Master Multiple Slave Configuration
Slave MOSI MISO Slave
Slave
Slave
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO Master Ports
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SERIAL PERIPHERAL INTERFACE (Cont'd) 9.4.6 Power Modes
Mode WAIT Description effect SPI. interrupt events cause device exit from WAIT mode. registers frozen. HALT mode, inactive. operation resumes when woken interrupt with "exit from HALT mode" capability. data received subsequently read from SPIDR register when software running (interrupt vector fetching). several data received before wakeup event, then overrun error generated. This error detected after fetch interrupt routine that woke device.
HALT
Note: When waking from Halt mode, remains Slave mode, recommended perform extra communications cycle bring from Halt mode state normal state. exits from Slave mode, returns normal state immediately. Caution: wake from Halt mode only Slave Select signal (external SPICSR register) when enters Halt mode. Slave selection configured external (see Section 9.4.3.2), make sure master drives level when slave enters Halt mode. 9.4.7 Interrupts
Interrupt Event Event Flag SPIF MODF SPIE Enable Control Exit from Wait Exit from Halt
9.4.6.1 Using wakeup from Halt mode slave configuration, able wakeup device from HALT mode through SPIF interrupt. data received subsequently read from SPIDR register when software running (interrupt vector fetch). multiple data transfers have been performed before software clears SPIF bit, then hardware.
Transfer Event Master Mode Fault Event Overrun Error
Note: interrupt events connected same interrupt vector (see Interrupts chapter). They generate interrupt corresponding Enable Control interrupt mask
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SERIAL PERIPHERAL INTERFACE (Cont'd) 9.4.8 Register Description CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh)
SPIE SPR2 MSTR CPOL CPHA SPR1 SPR0
SPIE Serial Peripheral Interrupt Enable. This cleared software. Interrupt inhibited interrupt generated whenever SPIF=1, MODF=1 OVR=1 SPICSR register Serial Peripheral Output Enable. This cleared software. also cleared hardware when, master mode, SS=0 (see Section 9.4.5.1 Master Mode Fault (MODF)). cleared reset, peripheral initially connected external pins. pins free general purpose alternate functions enabled SPR2 Divider Enable. This cleared software cleared reset. used with SPR[1:0] bits baud rate. Refer Table Master mode Frequency. Divider enabled Divider disabled Note: This effect slave mode. MSTR Master Mode. This cleared software. also cleared hardware when, master mode, SS=0 (see Section 9.4.5.1 Master Mode Fault (MODF)). Slave mode Master mode. function changes from input output functions MISO MOSI pins reversed.
CPOL Clock Polarity. This cleared software. This determines idle state serial Clock. CPOL affects both master slave modes. level idle state high level idle state Note: CPOL changed communication byte boundaries, must disabled resetting bit. CPHA Clock Phase. This cleared software. first clock transition first data capture edge. second clock transition first capture edge. Note: slave must have same CPOL CPHA settings master. Bits SPR[1:0] Serial Clock Frequency. These bits cleared software. Used with SPR2 bit, they select baud rate serial clock output master mode. Note: These bits have effect slave mode. Table Master mode Frequency Serial Clock fCPU/4 fCPU/8 fCPU/16 fCPU/32 fCPU/64 fCPU/128 SPR2 SPR1 SPR0
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SERIAL PERIPHERAL INTERFACE (Cont'd) CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h)
SPIF WCOL MODF
Reserved, must kept cleared. Output Disable. This cleared software. When set, disables alternate function output (MOSI master mode MISO slave mode) output enabled SPE=1) output disabled Management. This cleared software. When set, disables alternate function uses value instead. Section 9.4.3.2 Slave Select Management. Hardware management managed external pin) Software management (internal signal controlled bit. External free general-purpose I/O) Internal Mode. This cleared software. acts `chip select' controlling level slave select signal when set. Slave selected Slave deselected DATA REGISTER (SPIDR) Read/Write Reset Value: Undefined
SPIF Serial Peripheral Data Transfer Flag (Read only). This hardware when transfer been completed. interrupt generated SPIE=1 SPICR register. cleared software sequence access SPICSR register followed write read SPIDR register). Data transfer progress flag been cleared. Data transfer between device external device been completed. Note: While SPIF set, writes SPIDR register inhibited until SPICSR register read. WCOL Write Collision status (Read only). This hardware when write SPIDR register done during transmit sequence. cleared software sequence (see Figure 47). write collision occurred write collision been detected Overrun error (Read only). This hardware when byte currently being received shift register ready transferred into SPIDR register while SPIF (See Section 9.4.5.2). interrupt generated SPIE SPICR register. cleared software reading SPICSR register. overrun error Overrun error detected MODF Mode Fault flag (Read only). This hardware when pulled master mode (see Section 9.4.5.1 Master Mode Fault (MODF)). interrupt generated SPIE=1 SPICSR register. This cleared software sequence access SPICR register while MODF=1 followed write SPICR register). master mode fault detected fault master mode been detected
SPIDR register used transmit receive data serial bus. master device, write this register will initiate transmission/reception another byte. Notes: During last clock cycle SPIF set, copy received data byte shift register moved buffer. When user reads serial peripheral data register, buffer actually being read. While SPIF set, writes SPIDR register inhibited until SPICSR register read. Warning: write SPIDR register places data directly into shift register transmission. read SPIDR register returns value located buffer content shift register (see Figure 42).
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SERIAL PERIPHERAL INTERFACE (Cont'd) Table Register Reset Values
Address (Hex.) 0021h 0022h 0023h Register Label SPIDR Reset Value SPICR Reset Value SPICSR Reset Value SPIE SPIF SPR0
WCOL
SPR2
MSTR MODF
CPOL
CPHA
SPR1
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10-BIT CONVERTER (ADC) 9.5.1 Introduction on-chip Analog Digital Converter (ADC) peripheral 10-bit, successive approximation converter with internal sample hold circuitry. This peripheral multiplexed analog input channels (refer device description) that allow peripheral convert analog voltage levels from different sources. result conversion stored 10-bit Data Register. converter controlled through Control/Status Register. Figure Block Diagram 9.5.2 Main Features 10-bit conversion channels with multiplexed input Linear successive approximation Data register (DR) which contains results Conversion complete status flag On/off reduce consumption) block diagram shown Figure
fCPU
fADC
SPEED ADON SPEED
ADCCSR
AIN0
AIN1
ANALOG
AINx
ANALOG DIGITAL CONVERTER
ADCDRH
ADCDRL
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10-BIT CONVERTER (ADC) (Cont'd) 9.5.3 Functional Description conversion monotonic, meaning that result never decreases analog input does never increases analog input does not. input voltage (VAIN) greater than VAREF (high-level voltage reference) then conversion result ADCDRH register ADCDRL register (without overflow indication). input voltage (VAIN) lower than VSSA (lowlevel voltage reference) then conversion result ADCDRH ADCDRL registers 00h. converter linear digital result conversion stored ADCDRH ADCDRL registers. accuracy conversion described Electrical Characteristics Section. RAIN maximum recommended impedance analog input signal. impedance high, this will result loss accuracy leakage sampling being completed alloted time. 9.5.3.1 Converter Configuration analog input ports must configured input, pull-up, interrupt. Refer chapter. Using these pins analog inputs does affect ability port read logic input. ADCCSR register: Select CS[3:0] bits assign analog channel convert. 9.5.3.2 Starting Conversion ADCCSR register: ADON enable converter start conversion. From this time performs continuous conversion selected channel. When conversion complete: hardware. result ADCDR registers. read ADCDRH resets bit. read bits, perform following steps: Poll Read ADCDRL register Read ADCDRH register. This clears automatically. Note: data latched, both high data register must read before next conversion complete, recommended disable interrupts while reading conversion result. read only bits, perform following steps: Poll Read ADCDRH register. This clears automatically. 9.5.3.3 Changing conversion channel application change channels during conversion. When software modifies CH[3:0] bits ADCCSR register, current conversion stopped, cleared, converter starts converting newly selected channel. 9.5.4 Power Modes Note: converter disabled resetting ADON bit. This feature allows reduced power consumption when conversion needed. Mode WAIT Description effect Converter Converter disabled. After wakeup from Halt mode, Converter requires stabilization time tSTAB (see Electrical Characteristics) before accurate conversions performed.
HALT
9.5.5 Interrupts None.
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10-BIT CONVERTER (ADC) (C
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