Manages Fast Ethernet ports 8-Gigabit Ethernet ports Ethernet interfac

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Manages Fast Ethernet ports 8-Gigabit Ethernet ports Ethernet interfac

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AL300A Revision Switch Management Engine
Manages Fast Ethernet ports 8-Gigabit Ethernet ports Ethernet interface host dual channel On-chip buffers network management frame from host Glueless interface Intel 80486 Power MPC801 series microprocessors. Interfaces easily modern 32bit Provides Spanning Tree support switch ports Allayer's Compliant Ethernet-like Bridge MIB. Compliant RMON Etherstats allow support first four groups RMON channels also provide bridging function access 3.3V operation Packaged 208-pin PQFP
AL300A management device Allayer's RoXchip set. This management engine provides Interface Ethernet gathers required statistics support popular SNMP based management. AL300A supports Ethernet-like MIB, MIB, RMON MIB. also supports other management variables particular Allayer's switch chipset, such trunking port groups port security enable/disable.
Packet Receive Data
Packet Transmit Data Path Interface System Control Interface
Event Counter
SRAM
Figure
System Block Diagram
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AL300A Revision
This document contains proprietary information which shall reproduced, transferred other documents, used other purpose without prior written consent Allayer Communications.
Disclaimer Allayer Communications reserves right make changes, without notice, product(s) described information contained herein order improve design and/or performance. Allayer Communications assumes responsibility liability these products, conveys license title under patent copyright these products, makes representations warranties that these products free from patent copyright infringement unless otherwise specified.
Life Support Applications Allayer Communications products designed life support appliances, systems, devices where malfunctions reasonably expected result personal injury.
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Table Contents
AL300A Overview. Descriptions. Functional Description. Description Microprocessor Interface Services 3.2.1 3.2.2 Types Interface. Services
Spanning Tree Support. Interrupt Mechanism System Status Configuration. Statistics Collection. Port Related Etherstat Access. RMON Host Group Access.
Register Descriptions. Registers Host Memory Structure Reading Counters Mechanism.
Services: Host Frame Transmission Reception. Frame Reception 6.1.1 Receive Descriptor Field. Frame Transmission. Address Table Update Access.
Microprocessor Interface Description MPC801 Type Interface (P_SEL 7.1.1 7.1.2 7.1.3 7.1.4 7.2.1 7.2.2 7.2.3 Read Cycle Timing Write Cycle Timing AL300A MPC801 Burst Cycles. Relinquishing Read/Write Cycle Timing Burst Cycle Transfer. Relinquishing
Type Interface (P_SEL
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AL300A Revision
Signal Timing Specification Assignments Electrical Specifications AL300A Mechanical Data
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AL300A Revision
AL300A Overview
AL300A provides necessary functions provide network management agent based Fast Ethernet Gigabit Ethernet Switching Systems. AL300A designed interface Motorola PowerPC Series Intel Series without glue-logic, although AL300A could interface with 32-bit microprocessor (non-PCI bus) with little effort glue logic. following five fundamental functions built into AL300A. Provides services transmit receive Ethernet frames from high-speed dual channels. Gathers address updates real-time Bridge support. conjunction with Ethernet Switch devices, provide Spanning-Tree support. Provides access internal registers switch devices their associated devices. Provides Ethernet related (EtherType), related, RMON network statistics counters counters port). AL300A transmits receives Ethernet frames dual channels, receive transmit. When sending frames, prepares frames memory issues transmit command, along with frames address size, AL300A. AL300A then transmits frame from memory proper output port. When receiving frames, AL300A stores frames next available frame buffer receive buffers keeps channel. AL300A receives frames addressed itself, special frames that trapped AL300A (BPDU, Multicast Broadcast, GARP, etc.). AL300A also gathers real time address change information from optionally forwards channel. Every time address change information received, stored memory, every time bytes worth this message stored, optionally interrupted. Switching Devices (such AL101, AL116, etc.) provide built-in spanning-tree functions such spanning-tree port state control BPDU frame trapping CPU. Switch Devices support Learning, Blocking, Forwarding, etc., spanning tree states. Learning Blocking states, BPDU frames still received transmitted switch ports. AL300A provides access registers address tables Switching Devices remote register access command. issues remote register read write command AL300A. AL300A then performs access sets status (done) optionally interrupt CPU. vendor unique IEEE standard registers (100BASE-T registers) accessible this interface well. AL300A also provides network statistics counters support RMON groups through (EtherStats, History, History Control, Alarm) well Ethernet-Like MIB. counters 32-bit counters except octet counters, which 64-bit counters. RMON host groups (Top Talker, etc.) also implemented AL300A, host number limited one. useful track host, such network file server, these counters.
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AL300A Revision
PQFP Package
ROCTL0 ROCTL1
ROCTL2
ROCTL3
ROCTL4 ROCTL5
TEST0 ROCTLH
ROCTL6 ROCTL7
TEST3
TEST2
TEST1
ROD9 ROD10 ROD11
ROD12 ROD13
ROD14
ROD15
ROD16
ROD17
ROD18
ROD19 ROD20
ROD21 ROD22
ROD23
RODH
ROD0 ROD1
ROD2
ROD3
ROD4
ROD5 ROD6
ROD7
ROD8
RICTLH RICTL0 RICTL1 RICTL2 RICTL3 RICTL4 RICTL5 RICTL6 RICTL7 RIDH RID0 RID1 RID2 RID3 RID4 RID5 RID6 RID7 RID8 RID9 RICLK RID10 RID11 RID12 RID13 RID14 RID15 RID16 RID17 RID18 RID19 RID20 RID21 RID22 RID23 RID24 RID25 RID26 RID27 RID28 RID29
ROD24 ROD25
ROD26 ROD27 ROD28 ROD29 ROD30 ROD31 P_RST P_Sel P_D31 P_D30 P_D29 P_D28 P_D27 P_D26 P_D25 P_D24 P_CLK P_D23 P_D22 P_D21 P_D20 P_D19 P_D18 P_D17 P_D16 P_D15 P_D14 P_D13 P_D12 P_D11 P_D10 P_D9 P_D8 P_D7 P_D6
BURST#
RID30
RID31
BDIP#
INT#
BRDY
MST# P_A2
P_D0 P_D1
P_D2
P_D3 P_D4
P_A9 P_A10
P_A14
P_A13
P_A17
Figure
AL300A Diagram
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P_A19
P_A11 P_A12
P_A15 P_A16
P_A18
P_D5
P_A3 P_A4
P_A5
P_A6
P_A7
P_A8
AL300A Revision
Descriptions
Table Processor Interface
NAME P_D[31:0] P_A[19:2] P_BURST#/MIO P_BB#/CD P_TS#/ADS# P_TA#/RDY# P_CS# P_INT# P_BDIP#/BLAST# NC/BRDY# P_BR#/HOLD P_BG#/HLDA P_MST# P_SEL TYPE DESCRIPTION Processor Data [31:0] Processor Address [19:2] Processor Burst (MPC801) Processor Memory/IO (486) Processor Busy Processor Command/Data Processor Transfer Start Processor Address Strobe Processor Read/Write Control Processor Transfer Acknowledge Processor Data Ready Processor Chip Select Processor Interrupt Request Processor Burst Progress Processor Burst Last Connection Processor Burst Ready Processor Access Request Processor Hold Processor Access Grant Processor Hold Acknowledge Processor Master Processor Protocol Select MPC801 Processor Reset Processor Clock
P_RST# P_CLK
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AL300A Revision
Table Output Interface
NAME ROD[31:0] RODH ROCTL[7:0] ROCTLH TYPE DESCRIPTION Output Data [31:0] Output Data Header Output Control [7:0] Output Control Header
Table Input Interface
NAME RID[31:0] RIDH RICTL[7:0] RICTLH RICLK TYPE DESCRIPTION Input Data [31:0] Input Data Header Input Control [7:0] Input Control Header System Clock
Table Test
NAME TESTO[3] TESTO[2] TESTO[1] TESTO[0] TYPE Test Output Test Output Test Output Test Output DESCRIPTION
Table Power Miscellaneous
NAME (3.3V) TYPE Connection Ground Supply Voltage DESCRIPTION
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AL300A Revision
Functional Description
AL300A integrates necessary functions support network management based Fast Ethernet gigabit Ethernet switches. provides following functions: Provides services transmit receive Ethernet frames from bus. Serves proxy access internal registers devices their associated devices. Gathers maintains Ethernet related, related, RMON network statistics counters. Gathers address table maintains changes Bridge support.
P_D[0:31] P_A[2:19] TS#/ADS# TA#/RDY# Burst#/MIO PDIP#/BLAST BR#/HOLD BG#/HLDA RST# BB#/CD NC/BRDY MST# SRAM Event Counter System Control RID[0:31] RIDH RICTL[0:7] RICTLH Interface Packet Transmit Data Path Packet Recieve Data Path Interface
Figure
AL300A Functional Block Diagram
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AL300A Revision
Description
switch system shown Figure 24-port 10/100 Mbit/s switch with Gigabit Ethernet ports. This system utilizes Allayer's proprietary architecture. ring structure that serves system backplane. Ring composed data ring control ring. data ring used transfer frame data, events, system configuration, status report messages. control ring used communicate Ring protocol messages among devices that switch backbone resources data transfer data ring. Each device ring input interface receiving data frames ring protocol messages from upstream device, output interface transmitting data frames ring protocol messages downstream device. AL300A resides Ring serves proxy between host management processor Bus. communication between host devices done through AL300A. When routing added (such AL3000 series device), AL300A programmed relinquish some interface functions such device.
AL300A
AL100A
AL100A
AL100A
AL1000
Figure
Managed Switch Using with Mbps Ports Gbps Ports
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AL300A Revision
Microprocessor Interface Services
3.2.1 Types Interface interface 32-bit wide interface that optimized both MPC801 type 486-type interface's. used select desired interface. Interface other 32-bit microprocessor accomplished with simple glue logic. microprocessor interface allows gain access AL300A devices Bus. registers statistics switch chips associated devices accessible this interface. Through AL300A's indirect register access (IRA), registers, SGRAM, EEPROM, on-chip address tables, content also accessible. These functions will described management functions AL300A. 3.2.2 Services AL300A also provides services between management interface Bus. 802.1d BPDU, well designated management frames received switch port, will delivered through AL300A processor. locally generated frames will delivered through AL300A network ports. incoming direction, frame data destined will downloaded from ring will delivered dedicated byte block host memory location allocated through Receive Channel, along with receiving port byte block sectioned into buffer sizes provide total receive buffers. buffers used sequence buffers full, AL300A will discard frames. outgoing direction, frame data generated will into host memory location allocated CPU. AL300A will transfer outgoing frame through Transmit Channel onto Ring, which will deliver frame right network port transmission. AL300A will generate (IEEE 802.3 FCS) field frame data. AL300A will automatically generate padding frame length less than legal size frame (i.e. illegally short frame will sent is). controls frame destination port supplying transmit port each frame transmitted. AL300A uses Transmit Channel control transmit flow.
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AL300A Revision
HOST MEMORY
Address Convergence Table
AL300A Packet Recieve Buffer Blocks 2Kbyte)
System Registers
Packet Transmission Buffer(s) (CPU Maintains Buffer Structure) Statistics Counters
Optional Copy Statistics Counter
Figure
AL300A Host Memory Requirements Access
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AL300A Revision
Spanning Tree Support
AL300A capability support implementation Spanning Tree Protocol. ports chip programmed port state required Spanning Tree Protocol. port Block-N-Listen State Learning State, frame forwarded only BPDU frame, otherwise frame discarded. outgoing frames except outgoing BPDUs will masked from path PHY. port Forwarding State, frame forwarded BPDU frame. source addresses incoming frames from will learned then forwarded based switch routing decision. outgoing frames will transmitted PHY. port learning, source addresses incoming frames from will learned. incoming frames except incoming BPDUs from will discarded after being learned, while outgoing frames except outgoing BPDUs will masked from path PHY.
Interrupt Mechanism
When AL300A configured enable interrupt, will generate interrupt whenever bits Interrupt Source Status Register [31:24] set. required read this register differentiate type interrupt execute appropriate interrupt service routine. When AL300A interrupt disabled, must poll interrupt source registers keep track AL300A's operation status.
System Status Configuration
also various configurations status registers devices, such AL100A AL1022, ensure proper operation system AL300A. system configuration, operation status polling, Spanning Tree Protocol, port status control, address table access, management entity access operations will through this path. issues Indirect Access Read (Write) command AL300A which turn will translate command into command message transfer message targeted device through Ring. response from AL100A/AL1022 comes back through Ring while AL300A will store access result Indirect Access Result Register, notify through interrupt mechanism. will read Indirect Access Register access result. system port configuration status register definitions refer individual device data sheets. following limited list features that configured devices through this interface: trunking ports Full half-duplex mode operation management, e.g. auto-negotiation results, speed selection, etc. address table management including static entry, aging, etc.
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AL300A Revision
Override serial EEPROM interface EEPROM-free configuration Enable/disable port security Port monitoring support through port-mirroring Select flow control (IEEE 802.1x full-duplex, back-pressure options half-duplex) Port based VLAN setup Multicast/Broadcast trapping enable/disable Broadcast storm control each switch port enable/disable
Statistics Collection
AL300A accumulates SNMP RMON management through Receive Events Transmit Events sent from devices (AL100 series AL1000 series switches) through Ring. AL300A collects network port activity statistics stores them internal management support. Each statistical entry 32-bit counter except byte byte counters that both 64-bit counters. AL300A will maintain these statistics each network ports respectively. Refer table definition each count. AL300A capability collect Port Related Etherstat RMON Host Group MIB. Source Host Destination Host supports limited capability RMON Host related group MIB. AL300A will store these statistics on-chip registers. RMON Host Counter currently supported AL1022 AL1023.
Port Related Etherstat Access
accesses entry either through direct memory mapped access through indirect access operation host memory. operation, first writes access command into Command Register, indicating specific entry block wants read. AL300A then transfers block data bytes) memory interrupts host process interrupt enabled. count rolls over when counter full. internal architecture, dual gigabit device (AL1022) present Bus, KMEN mode (register must system register device gigabit also needs match gigabit device that enables AL300A access statistics stored gigabit device direct memory access. This procedure does have followed only indirect access statistics used. This separate mechanism necessary support statistic collection gigabit speeds.
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AL300A Revision
RMON Host Group Access
access Host counts reading on-chip Host registers. This group provides limited support RMON Host related groups, (i.e. Host groups where equal This particularly useful client-server environment where server host node interest. Host count will cleared zero when Host Count Unhold command (command type register issued. Before changes host, should issue Host Count Hold command (command type register freeze this group until read. After changes host complete, issue Host Count Unhold command this group counters reset accumulate host based hosts. access AL1022 Host counts issuing AL1022 Access command. also clear AL1022 Host counts AL1022 Access command.
Register Descriptions
There eight system registers control AL300A's operations associated devices. eight registers provide some host group statistics associated with RMON, memory mapped address space that provides access Ethernet Statistics. Ethernet statistics includes counters needed support Ethernet-like interface MIB, management MIB, 802.1d Bridge MIB, RMON Etherstats group MIB. RMON Etherstats group allows implementers provide first four groups (Etherstats, History, History Control, Alarm) RMON with complete accuracy. System Register used setup AL300A, interrupt masks read results. System Register also contains status command process. System Register used issue commands devices ring receive results back either through 16-bit result register through transfer results contain block information, such address table). System Register contains receive buffer status. Each corresponds each receive buffer ownership. means corresponding buffer owned host been processed, means corresponding buffer free used reception frame. System Register contains interrupt vector used vectored interrupt cycle. This only used Intel mode. System Register reserved Allayer's test mode. register initialized "0"s should accessed. Writing into this register does affect operation this chip. system registers only accessible through slave access, Ethernet Statistics registers available through both slave access transfer mode host memory block.
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AL300A Revision
Table Register Structure AL300A
REGISTER 800-829 840-869 880-8A9 8C0-8E9 900-929 940-969 980-9A9 9C0-9E9 A00-A29 A40-A69 A80-AA9 AC0-AE9 ACCESS READ READ READ READ READ READ READ READ READ READ READ READ READ READ READ READ READ READ READ READ DEFAULT 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4000 0000 0000 0000 REGISTER NAME Configuration Configuration Interrupt Status Command Indirect Access Result Shadow Register Frame Interrupt Vector [7:0] Test Command Host Host Host Host Host Device Revision Matrix Matrix Reserved Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts.
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AL300A Revision
Table Register Structure AL300A (Continued)
B00-B29 B40-B69 B80-BA9 BC0-BE9 C00-C29 C40-C69 C80-CA9 CC0-CE9 D00-D29 D40-D69 D80-DA9 DC0-DE9 E00-E29 E40-E69 E80-EA9 EC0-EE9 F00-F29 F40-F69 F80-FA9 FC0-FE9 READ READ READ READ READ READ READ READ READ READ READ READ READ READ READ READ READ READ READ READ Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts. Device Port counts.
Note: device AL1022 series gigabit switch, only port counts valid this device Register KMEN, KMFREQ, enabling support AL1022 statistics update.
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AL300A Revision
Table Configuration Register (Register
NAME DESCRIPTION Interrupt Mask Gigabit Access Done Interrupt Source. Disable interrupt. Enable interrupt. Interrupt Mask Incoming Frame Block Transfer Done Interrupt Source CPU). Disable interrupt. Enable interrupt. Interrupt Mask Clear Done Interrupt Source. Disable interrupt. Enable interrupt. Interrupt Mask Outgoing Frame Block Transfer Done Interrupt Source (from CPU). Disable interrupt. Enable interrupt. Interrupt Mask Read Done Interrupt Source. Disable interrupt. Enable interrupt. Interrupt Mask Indirect Access Done Interrupt Source. Disable interrupt. Enable interrupt. Interrupt Mask Transmit Error Buffer Underflow. Disable interrupt. Enable interrupt. Interrupt Mask Table Convergence Ready Read. Disable interrupt. Enable interrupt. Maximum Allowable Frame Length (not including preamble+SFD). 1536 (^h0600) byte maximum value. Resolution: Byte Reserved Disable Table Convergence Message CPU. Table convergence message enable. Table convergence message disable. Disable Frame Transfers. Allow transfer frame to/from CPU. allow transfer frame to/from CPU. Dynamic Bandwidth Increment Disable Data Transfer CPU. Enable Disable
ClrMIB
RdMIB
23~13
MaxPL<10:0> Reserved Tbdisable
DisPktTx
INCDis
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AL300A Revision
Table Configuration Register (Register (Continued)
MaxSBW<3:0> Maximum Source Bandwidth. Controls maximum channel bandwidth ring. bandwidth Mbit/s increment. recommendation this setting eight. Maximum Link Bandwidth. Controls total bandwidth ring (aggregated bandwidth channels). recommended value
MaxLBW<4:0>
Table Configuration Register (Register
31~6 NAME Reserved RMode Mode. Selects Ring performance optimized. Targeted mixture 10/100 1000 switches. Targeted 1000 switches only. AL1022 Frequency. Selects AL1022 update intervals. Updated every 0.44ms. Updated every 0.88ms. Updated every 1.32ms. Updated every 1.76ms. AL1022 Enable Automatic Updates into this Device. Disable updates. Enable updates. AL1022 Device Updated Automatic Update. DESCRIPTION
KMFREQ
KMEN
Table Interrupt Status Ring Device Command Register (Register
NAME GMADone DESCRIPTION Gigabit Access Command (for AL1022) Completed. done. Done Incoming Frame Transfer Done CPU). done. Done Clear Command Completed. done. Done Outgoing Frame Block Transfer Done (from CPU). done. Done
InPDone
ClrMIBDone
OutPDone
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AL300A Revision
Table Interrupt Status Ring Device Command Register (Register (Continued)
RdMIBDone Read Command (for AL300A) Completed. done. Done Indirect Register Access Done. done. Done Transmit Error Buffer Underflow. error. Error word Table Convergence Written Read. ready. Ready
IRADone
TEBU
23~21 20~17
Reserved TB_shadow Shadow Register Table Convergence Messages. Each represents entry being full ready processing. 0000: None entry full. xxx1: first entry full. xx1x: second entry full. x1xx: third entry full. 1xxx: fourth entry full. Type Incoming Frame. (Valid with InPDone=1) Regular BPDU Source Device Incoming Frame. (Valid with InPDone=1) Device Device Device Device Source Port Incoming Frame. (Valid with InPDone=1) 000: Port 001: Port 010: Port 011: Port 100: Port 101: Port 110: Port 111: Port Byte Count Last Word Last Block Incoming Frame. (Valid with InPDone=1) bytes. byte. bytes. bytes.
InType
15~14
InDevID <1:0>
13~11
InPID<2:0>
10~9
InBCount
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AL300A Revision
Table Interrupt Status Ring Device Command Register (Register (Continued)
InLWCount Longword Count Last Block Incoming Frame. (Valid with InPDone=1) 0000 0000: longwords. 0000 0001~1 1111 1111: longword longwords.
Table Command Register (Register
31~28 NAME CMDType DESCRIPTION Command Type. 0000: Indirect access read. 0001: Indirect access write. 0010: table convergence base address. 0011: Reserved 0100: Host count hold. 0101: Host count unhold (clear host counters). 0110: Incoming frame transfer initialization. 0111: Outgoing frame transfer initialization. 1000: Outgoing frame transfer notification. 1001: Read AL300A port information. 1010: Clear AL300A port information. 1011: Reserved 1100: Access AL1022 port information. 1101~1111: Reserved Attributes Associated with Command Type.
27~0
Attributes
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AL300A Revision
Indirect Access Read Indirect Access Read command allows host read 16-bit data from device. When this register initiates read, results available Register (the Indirect Read Result Register.) Upon completion command, AL300A sets IRAD (bit Register which must clear before next Indirect Access Read Write operation. DeviceID<1:0> field device number device read, RegIndex<7:0> register address this device. addition, Indirect Access Done Interrupt could generated enabled. Tables available registers specified their respective data sheet.
Table Indirect Access Read (Register <31:16>)
NAME Bits Value CMDType<3:0> 31:28 0000 DeviceID<1:0> 27:26 Device RegIndex<7:0> 25:18 Device Register Index RESERVED 17:16 Don't Care
Table Indirect Access Read (Register <15:0>)
NAME Bits Value RESERVED 15:0 Don't Care
Indirect Access Write Indirect Access Write command allows host write 16-bit data device. Writing this register initiates write operation with Write-Data<15:0>. Upon completion command, AL300A sets IRAD (bit Register which must clear before next Indirect Access Read Write operation. DeviceID<1:0> field device number device read, Register-Index<7:0> register address this device. addition, Indirect Access Done Interrupt could generated enabled. Tables available registers specified their respective data sheet.
Table Indirect Access Write (Register <31:16>)
NAME Bits Value CMDType<3:0> 31:28 0001 DeviceID<1:0> 27:26 Device REGISTERINDEX<7:0> 25:18 Device Register Index RESERVED 17:16 Don't Care
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AL300A Revision
Table Indirect Access Write (Register <15:0>)
NAME Bits Value WRITEDATA<15:0> 15:0 Write Data 15:0
Table Convergence Base Address Table Convergence Base Address command allows host starting address byte block host memory store address convergence messages. This base address should once during system initialization. base address another value, then AL300A does reset internal message-write-pointer starting address. AL300A this case would continue write next memory location using base address.
Table Table Convergence Base Address (Register <31:16>)
NAME Bits Value CMDType<3:0> 31:28 0010 RESERVED 27:16 Don't Care
Table Table Convergence Base Address (Register <15:0>)
NAME Bits Value RESERVED 15:9 Don't Care TCBaseAddrs<8:0> Table Convergence Base Address<19:11>
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AL300A Revision
Host Count Hold Host Count Hold command compliment Host Count Unhold command used control RMON host group counters. Host Count Hold command stops counters same time while Host Count Unhold command clears Host Count Registers starts counting again. Host Count Hold command useful when several addresses tracked through time sampling method. critical that devices initialized same host Source Destination address host tracking. they initialized same value, host counters will meaningful.
Table Host Count Hold (Register <31:16>)
NAME Bits Value CMDType<3:0> 31:28 0100 RESERVED 27:16 Don't Care
Table Host Count Hold (Register <15:0>)
NAME Bits Value RESERVED 15:0 Don't Care
Host Count Unhold Host Count Unhold command allows host clear Host Count zero.
Table Host Count Hold (Register <31:16>)
NAME Bits Value CMDType<3:0> 31:28 0101 RESERVED 27:16 Don't Care
Table Host Count Unhold (Register <15:0>)
NAME Bits Value RESERVED 15:0 Don't Care
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AL300A Revision
Receive Frame Buffer Initialization Receive Frame Buffer Initialization command allows host starting address byte block host memory used receive buffers bytes each. This base address should once during system initialization. base address another value, then AL300A does reset internal receive-buffer-pointer starting address. AL300A this case would continue write next buffer location using base address, while frame reception process would corrupted. last five bits Receive Buffer Base Address must zero AL300A address bytes continuous host memory.
Table Receive Frame Buffer Initialization (Register <31:16>)
NAME Bits Value CMDType<3:0> 31:28 0110 RESERVED 27:16 Don't Care
Table Receive Frame Buffer Initialization (Register <15:0>)
NAME Bits Value RESERVED 15:9 Don't Care RxPckBAddrs<8:0> Receive Frame Buffer Base Address<19:11>
Transmit Frame Initialization Transmit Frame Initialization command allows host starting address transmit buffer host memory size next frame transmitted. host must provide frames total word count many bytes last word because memory accessed word.
Table Transmit Frame Initialization (Register <31:16>)
NAME Bits Value CMDType<3:0> 31:28 0111 ByteCntLW<1:0> 27:26 Byte Count Last Word<1:0> WordCnt<8:0> 25:17 Word Count Frame<8:0> RESERVED Don't Care
Table Transmit Frame Initialization (Register <15:0>)
NAME Bits Value RESERVED 15:9 Don't Care TxPckBAddrs<8:0> Outgoing Frame Host Memory Base Address<19:11>
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AL300A Revision
Transmit Frame Transfer Notification Transmit Frame Transfer Notification command notifies AL300A transmit frame specified Transmit Frame Initialization device port specified.
Table Transmit Frame Transfer Notification (Register <31:16>)
NAME Bits Value CMDType <3:0> 31:28 1000 PcKDST <1:0> 27:26 Outgoing Frame Destination Device ID<1:0> PrtMap <7:0> 25:18 Outgoing Frame Port Map<7:0> PckType Frame BPDU RESERVED Don't Care
Table Transmit Frame Transfer Notification (Register <15:0>)
NAME Bits Value RESERVED 15:0 Don't Care
Read AL300A Port Information Read AL300A Port Information command copies Statistics Counters stored AL300A's internal registers host memory transfers. There total 32-bit counters port each port uses bytes memory spaces. total possible number ports (four devices eight ports). Therefore, address space required counters bytes. host must provide base address <19:13> MIBAdrsBase<6:0> field.
Table Read Al300A Port Information (Register <31:16>)
NAME Bits Value CMDType<3:0> 31:28 1001 MIBRdDevID<1:0> 27:26 Read Device ID<1:0> MIBRdPrtID<2:0> 25:23 Read Port ID<2:0> RESERVED 22:16 Don't Care
Table Read AL300A Port Information (Register <15:0>)
NAME Bits Value RESERVED 15:7 Don't Care MIBAdrsBase<6:0> Host Base Address<19:13>
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AL300A Revision
Clear AL300A Port Information Clear AL300A Port Information command clears statistics stored AL300A's internal registers. clear entire statistics counter table, each port each device must cleared separately through this command. This should done after every global reset.
Table Clear AL300A Port Information (Register <31:16>)
NAME Bits Value CMDType<3:0> 31:28 1010 MIBRdDevID<1:0> 27:26 Clear Device ID<1:0> MIBRdPrtID<2:0> 25:23 Clear Port ID<2:0> RESERVED 22:16 Don't Care
Table Clear AL300A Port Information (Register <15:0>)
NAME Bits Value RESERVED 15:0 Don't Care
Access AL1022 Port Information Access AL1022 Port Information command copies Statistics Counters stored AL1022's internal registers host memory transfers. Since only ports exist device instead eight ports 10/100 Mbit/s devices, BlkOffset<5:0> address field added AL1022 port address. addition, AL1022 contains counter opposed 10/100 Mbit/s switch devices. Therefore, AL1022 takes less memory space than eight port devices. more base address added smaller host memory allocation. eight port switch devices, device ID<1:0> port ID<2:0> used addition host base address. AL1022 case, BlkOffset<5:0> replaces device ID<1:0> port ID<2:0>.
Table Access AL1022 Port Information (Register <31:16>)
NAME Bits Value CMDType<3:0> 31:28 1100 BlkOffset<5:0> 27:23 Gigabit Host Base Address<12:7> GMIBDevID<1:0> 22:21 AL1022 Device ID<1:0> RESERVED 20:16 Don't Care
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AL300A Revision
Table Access AL1022 Port Information (Register <15:0>)
NAME Bits Value RESERVED 15:10 Don't Care GCMDType<2:0> Command Type<2:0> 000: Port0 read. 001: Port1 read. 010: Host read. 011: Reserved. 100: Port0 clear. 101: Port1 clear. 110: Host clear. 111: Register hold. GMIBAdrsBase<6:0> Gigabit Host Base Address<19:13>
Register Indirect Access Result Register After executing Indirect Access Read command data returned stored Indirect Access Result Register.
Table Indirect Access Result Register (Register <31:16>)
NAME Bits Value RESERVED 31:16 Valid
Table Indirect Access Result Register (Register <15:0>)
NAME Bits Value IRAdata<15:0> 15:0 Indirect Access Result Data<15:0>
Table Shadow Register Receive Buffer Ownership (Register
31:0 NAME MemoryVLD DESCRIPTION corresponding memory space occupied unread frames. corresponds highest address buffer zero corresponds lowest address buffer (i.e. base address +0).
Note: This register indicates availability receive frame buffer host memory. AL300A uses Shadow Register identify which block receive frame buffer available transfer frame. host must clear that corresponds block buffer when finished reading frame.
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Table Interrupt Vector Register (Intel Mode Only/Register
31:8 NAME Reserved Interrupt Vector Reserved Interrupt Base Vector. Used during vectored interrupt. DESCRIPTION
Table Test Register (Register
31:0 NAME Reserved Must zeros. DESCRIPTION
Note: This register reserved factory test purpose only. Values must zero.
Table Host Register (Register
31:29 28:27 26:24 23:0 NAME Reserved SDevID SPID HOutOctets Reserved Source Device [1:0] Source Port [2:0] Number octets transmitted from host specified MAC, including octets frames. DESCRIPTION
Table Host Register (Register
31:16 15:0 NAME HOutPkts HOutErrors DESCRIPTION Number frames transmitted from host specified address, including frames. Number frames transmitted from host specified address.
Table Host Register (Register
31:16 15:0 NAME HOutBcsts HOutBcsts DESCRIPTION Number good broadcast frames transmitted from host specified address. Number good multicast frames transmitted from host specified address.
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Table Host Register (Register
31:0 NAME HInOctets DESCRIPTION Number octets transmitted host specified MAC, including octets frames.
Table Host Register (Register
31:24 23:0 NAME DevRev<7:0> HinPkts<23:0> DESCRIPTION Revision Number. value this field contains revision number current device. lowest revision number 01h. Number good frames transmitted host specified MAC.
Table Matrix Register (Register
31:24 23:0 NAME Reserved MatrixOctets <23:0> Reserved Number octets contained frames transmitted from host specified host specified MAC. DESCRIPTION
Table Matrix Register (Register
31:16 15:0 NAME MatrixPkts MatrixErrors DESCRIPTION Number frames transmitted from host specified host specified MAC, including frames. Number frames transmitted from host specified host specified MAC.
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Registers
Registers 0800 through 0FFF Ethernet Statistics Counter Registers AL300A.
Table 100Mbit/s Registers AL300A
REGISTER DEVICE ID[1:0] PORT ID[2:0]
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Table 100Mbit/s Registers AL300A
counters bits, start address Hex. index description each respective Mb/s port listed following table. Refer second table Gbit/s port counter mapping.
Table 100Mbit/s Register Descriptions
ID[5:0] NAME RxUcstPkts RxBcstPkts RxMcstPkts RxPausePkts RxFCSErrors 0Collisions 1Collisions MultiCollision TxUcstPkts TxBcstPkts TxMcstPkts TxPausePkts FloodPkts FilterPkts DESCRIPTIONS Number good unicast frames received. Number good broadcast frames received. Number good multicast frames received. Number 802.3x Pause frames received. Number frames received proper size with error non-integral number octets. Number frames which transmission process experienced collisions. Number frames which transmission process experienced collision. Number frames which transmission process experienced fifteen collisions. Number good unicast frames transmitted. Number good broadcast frames transmitted. Number good multicast frames transmitted. Number 802.3x Pause frames transmitted. Number good frames that were flooded switch system unknown destinations. Number good frames that were filtered switch system because destination resides same network segment receiving port.
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Table 100Mbit/s Register Descriptions (Continued)
BufFullDrops StormDrops Number good frames that were dropped because input frame buffer full. Number good broadcast multicast frames dropped many broadcast multicast frames accumulated input buffer. Number frames (including frames) received that were octets length. Number frames (including frames) received that were between octets length. Number frames (including frames) received that were between octets length. Number frames (including frames) received that were between octets length. Number frames (including frames) received that were between 1023 octets length. Number frames (including frames) received that were between 1024 maximum octets (specified system configuration software) length. Number times which transmission fails excessive collisions. Number times collision detected later than times into frame transmission. Number frames (including frames) transmitted that were octets length. Number frames (including frames) transmitted that were between octets length. Number frames (including frames) transmitted that were between octets length. Number frames (including frames) transmitted that were between octets length. Number frames (including frames) transmitted that were between 1023 octets length. Number frames (including frames) transmitted that were between 1024 maximum octets (specified system configuration software) length. Upper 32-bit count number received octets data (including those frames). Lower 32-bit count number received octets data (including those frames).
Rx64Octets Rx65To127 Rx128To255 Rx256To511 Rx512To1023 Rx1024ToMAX
TxExcessCOLs TxLateCOLs Tx64Bytes Tx65To127 Tx128To255 Tx256To511 Tx512To1023 Tx1024ToMAX
RxOctets RxOctets
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Table 100Mbit/s Register Descriptions (Continued)
TxOctets TxOctets RxFragments RxJabbers Upper 32-bit count number transmitted octets data (including those frames). Lower 32-bit count number transmitted octets data (including those frames). Number frames received that were less than octets long with either error alignment error. Number frames received that were greater than maximum octets (specified system configuration software) long with either error alignment error. Number frames received proper size with error non-integral number octets. Number frame received proper size experienced symbol error during frame reception. Number good frames that were dropped because violation switch security rules. Number good frames that were dropped because source destination exist different VLAN domains. Number frames received that were less than octets long without error alignment error. Number frames received that were greater than maximum octets (specified system configuration software) long without error alignment error.
RxAlignErrors RxSymbolErrors SecurityDrops VLANDrops
Undersized Oversized
counters bits, start address Hex. index description each respective Gbit/s port listed following table.
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Table Gbit/s Registers AL300A
REGISTER DEVICE ID[1:0] PORT
Table Gbit/s Register Descriptions
ID[4:0] NAME RxUcstPkts TxUcstPkts RxBcstPkts TxBcstPkts RxMcstPkts TxMcstPkts RxPausePkts TxPausePkts RxFCSErrors RxSymbolErrors Rx64Octets Tx64Bytes Rx65To127 DESCRIPTION Number good unicast frames received. Number good unicast frames transmitted. Number good broadcast frames received. Number good broadcast frames transmitted. Number good multicast frames received. Number good multicast frames transmitted. Number 802.3x Pause frames received. Number 802.3x Pause frames transmitted. Number frames received proper size with error integral number octets. Number frame received proper size experienced symbol error during frame reception. Number frames (including frames) received that were octets length. Number frames (including frames) transmitted that were octets length. Number frames (including frames) received that were between octets length.
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Table Gbit/s Register Descriptions (Continued)
Tx65To127 Rx128To255 Tx128To255 Rx256To511 Tx256To511 Rx512To1023 Tx512To1023 Rx1024ToMAX Number frames (including frames) transmitted that were between octets length. Number frames (including frames) received that were between octets length. Number frames (including frames) transmitted that were between octets length. Number frames (including frames) received that were between octets length. Number frames (including frames) transmitted that were between octets length. Number frames (including frames) received that were between 1023 octets length. Number frames (including frames) transmitted that were between 1023 octets length. Number frames (including frames) received that were between 1024 maximum octets (specified system configuration software) length. Number frames (including frames) transmitted that were between 1024 maximum octets (specified system configuration software) length. Number frames received that were less than octets long with either error alignment error. Number frames received that were greater than maximum octets (specified system configuration software) long with either error alignment error. Number good frames that were flooded switch system unknown destinations. Number good frames that were filtered switch system because destination resides same network segment receiving port. Number good frames that were dropped because input frame buffer full. Number good broadcast multicast frames dropped many broadcast multicast frames accumulated input buffer. Upper 32-bit count number received octets data (including those frames).
Tx1024ToMAX
RxFragments RxJabbers
FloodPkts FilterPkts
BufFullDrops StormDrops
RxOctets
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Table Gbit/s Register Descriptions (Continued)
RxOctets TxOctets TxOctets Lower 32-bit count number received octets data (including those frames). Upper 32-bit count number transmitted octets data (including those frames). Lower 32-bit count number transmitted octets data (including those frames).
Host Memory Structure
When Read AL300A Port Information command executed, words port information copied host memory location starting base address address offset each port. instance, base address 002, Device Port first information (RxUcstPkts) 20'h01040. base address kept constant subsequent execution command ports read, following table content would result host memory. system where there more than dual-gigabit devices, Read AL300A Port Information command only method access gigabit device counters second, third, fourth gigabit devices. first gigabit device counters still accessed through KMEN mode setting device field Register information AL1022 stored AL1022. order access AL1022 information, Access AL1022 Port Information command should issued. AL300A stores values received from AL1022 host memory through channel. After transfer, AL300A sets GMADone interrupt bit, will asserted GMADoneMask interrupt register active.
Reading Counters Mechanism
AL300A allows user read block port information with command (Read AL300A Port information Access AL1022 Port information.) AL300A also allows user read single AL300A count register read method. (See register definition detail.)
Table Counters Mechanism
ADDRESS OFFSET [10:0] 11'h000 11'h040 11'h080 11'h0C0 11'h100 DEVICE [1:0] PORT [2:0]
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Table Counters Mechanism (Continued)
11'h140 11'h180 11'h1C0 11'h200 11'h240 11'h280 11'h2C0 11'h300 11'h340 11'h380 11'h3C0 11'h400 11'h440 11'h480 11'h4C0 11'h500 11'h540 11'h580 11'h5C0 11'h600 11'h640 11'h680 11'h6C0 11'h700 11'h740 11'h780 11'h7C0
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Services: Host Frame Transmission Reception
Frame Reception
When DisPktTx (Register configured "0," AL300A provides services between switching fabric. AL300A receives 802.1d BPDU well data frames (for CPU) from network port which will delivered processor memory DMA. Similarly, AL300A receives generated 802.1d BPDU well regular data frames from DMA, AL300A delivers network ports interface. When frame transferred from network ports CPU, frame well receiving port frame type) forwarded AL300A. AL300A then transfers frame free receive buffer host memory receive channel. AL300A uses first receive buffer (one with lowest address) total receive buffers sequence. After using 32nd buffer, buffer pointer wraps around writes block location buffer available. Each time transfers frame, will interrupt receive interrupt enabled. AL300A communicates status buffer ownership with using 32-bit receive buffer shadow register. These bits also replicated frame descriptor status word, which located last longword location every receive buffer. Each shadow register valid indicate whether particular location memory space owned AL300A. After every successful reception, AL300A sets corresponding shadow register well frame descriptor status word. These bits AL300A, then reset after processes respective receive buffer. instance 32-bits Receive Buffer Shadow Register "1," which indicates incoming buffer full, host memory processed frames CPU. AL300A only checks shadow register content buffer ownership does check owner frame descriptor status word before using respective buffer.
Receive Buffer
Ethernet Frames 1536 Bytes
Receive Buffer
Receive Buffer Status Register Receive Buffer
Figure
Frame Reception
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Receive services should initialized below. Initialize address table devices with Host address input static entry. Initialize devices direct BPDU other special detectable frames (such IGMP) host. Initialize system registers. Enable frame reception through DisPktTx (Register 10). device initiates frame transfer from ports AL300A. frame could either Unicast (host address) address, Broadcast, BPDU, Unknown Destination Unicast Flood, Port Monitoring Copied frames, based setting individual devices. Once receive FIFO enough data transfer host memory, receive channel arbitrates bus, once granted, writes frames free receive buffer. transfers 64-bytes (16-bus cycles) every transfer. free buffer available, frame dropped error status set. After entire frame written, writes receive buffer status word into last longword buffer. After frame transfer finished, engine issues receive interrupt enabled). Note: Because many different frame types directed devices, host must examine destination address every frame determine frame type.
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6.1.1 Receive Descriptor Field Descriptor field last word incoming buffer space, AL300A uses this field communicate status information about received frame.
Table Receive Descriptor Field
NAME DESCRIPTION Current receive buffer frame process. This AL300A cleared CPU. also needs clear corresponding Shadow Register (register after freeing this buffer. case conflict between Shadow Register this bit, AL300A uses information Shadow Register. Always Type Incoming Frame. (Valid with InPDone=1) Regular BPDU Source Device Incoming Frame. (Valid with InPDone=1) Device Device Device Device Source Port Incoming Frame. (Valid with InPDone=1) 000: Port 001: Port 010: Port 011: Port 100: Port 101: Port 110: Port 111: Port Byte Count Last Word Last Block Incoming Frame. (Valid with InPDone=1) bytes 01~11: byte bytes Word Count Last Block Incoming Frame. (Valid with InPDone=1) 0_0000_0000: words 000000001~111111111: word words
30~17
Reserved InType
15~14
InDevID
13~11
InPID
10~9
InBCount
InWCount
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Frame Transmission
When data transferred from network ports, frame data generated will into host memory location allocated CPU. AL300A transfers outgoing frame through Transmit Channel onto Ring which will deliver frame right network port transmission. AL300A always generates field frame data, sends whole frame through Ring destination port(s). AL300A does enforce legal frame length. supplies AL300A with destination port every frame generated. Transmit channel operates below. initiates transmission writing frame destination(s) frame type (BPDU regular) data into AL300A command register. (Issue command "Outgoing Frame Transfer Notification" which Command Type will then authorize outgoing frame transfer AL300A writing Command Register with block location host memory, number word byte count which indicates size transfer. (Issue command "Outgoing Frame Transfer Initialization," Command Type engine arbitrates mastership, once granted, transfers frame data from host memory FIFO. After frame transfer finished, engine issues interrupt enabled) notifying frame transfer from host memory. There static transmit buffer structure assumed AL300A. host processes create manage many transmit buffers needed.
Address Table Update Access
Whenever AL300A receives table convergence messages, stores changes (using Table Convergence Message format) dedicated byte host memory. Each entry takes eight bytes, therefore buffer stores address updates. AL300A uses 4-bit registers communicate status Table Convergence Message buffers with CPU. AL300A will interrupt after memory (256 messages) space full table convergence (register unmasked. determine validity message reading valid each entry. bytes address buffer memory space must initialized "0"s upon host initialization. host process option either process message buffer though polling slow intervals enable interrupt process address changes blocks entries. This address update buffer sorted contain duplicate addresses. Because this buffer contains address changes, particular address re-learned. recommended that host process copy content buffer then sort based address, remove redundant entries. When handling redundant messages, discard address that older, case address update occurred result network node being moved from port another port. Alternatively, individual address could read from devices performing Indirect Read command through command register. Each read operation reads 16-bit data, requires four indirect read cycles receive address. 4096 indirect read command cycles needed read address table from each device. Because address table same among devices, only device needs read given
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system table convergence mode set. address convergence entry format follows:
Table Upper 32-Bit Word Address Entry
31~30 NAME Reserved Always Address Valid. AL300A cleared CPU. Table entry valid. Table entry valid. Source Port Trunking Mode. SrcPID field reflects trunk SrcPID field reflects port Device Device Device Device Device Source Port Incoming Frame. 000: Port 001: Port 010: Port 011: Port 100: Port 101: Port 110: Port 111: Port Older Addresses have Higher Value. Most Significant 16-bit Address Learned. DESCRIPTION
27~26
SrcDevID
25~23
SrcPID
22~16 15~0
TimeStamp MACAddr<47:32>
Table Lower 32-Bit Word Address Entry
31~0 NAME MACAddr<31:0> DESCRIPTION Least Significant 32-bit Address Learned.
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Microprocessor Interface Description
MPC801 Type Interface (P_SEL
MPC801 only access management functions AL300A using single beat read/ write cycles. MPC801 must assert when accessing AL300A. burst cycle related signals such BURST# BDIP# will ignored. During data transfer phase, data transferred from MPC801 AL300A write cycles from AL300A MPC801 read cycle. avoid electrical contention, MPC801 considers "one dead clock cycle" when switching between drivers. MPC801 stop driving data soon samples signal asserted rising edge CLKout signal. read cycle MPC801 accepts data contents valid rising edge CLKout signal which signal sample asserted. 7.1.1 Read Cycle Timing basic read cycle begins with arbitration, followed address assertion (transfer start). After receiving address, AL300A returns data asserts (transfer acknowledge) reads data. typical read operation shown Figure
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CLKout
Receive grant busy negated
Assert BB#, Drive address assert
A[0:31]
RD/WR#
TSIZ[0:1]
BURST#
DATA
Data valid
Figure
Single Beat Read Cycle Zero Wait States
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7.1.2 Write Cycle Timing basic write cycle begins with arbitration, followed address, data, assertion (transfer start). AL300A asserts (transfer acknowledge) samples data. single beat write cycle shown below Figure BDIP# signal ignored assumed de-asserted, which means burst cycles supported direct data transfer between AL300A.
CLKout
Receive grant busy negated
Assert BB#, Drive address assert
A[0:31]
RD/WR#
TSIZ[0:1]
BURST#
DATA
Data sampled
Figure
Single Beat Write Cycle Zero Wait States
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7.1.3 AL300A MPC801 Burst Cycles bridging function data transfers performed burst mechanism. When performing bridging function, AL300A acts master starts cycle asserting P_BR# (bus request). AL300A work with either MPC801 chip arbiter external arbiter. After obtaining control bus, AL300A will transfer data from memory using burst cycle. signal memory controller must tied high board, therefore memory attached AL300A must able support burst cycle. Each burst cycle consists cycles while wait state inserted slow down cycle. AL300A transfers data from system memory burst four 32-bit words 16-bytes. AL300A will relinquish control another arbitration cycle four 16-byte bursts (64-byte transfer), until data transfer completed. AL300A drives data during data phase burst write cycle. also asserts BDIP# signal intends drive data beat after current data beat.
DRAM
Multiplexer baddr[28:30] A[2:19] D[0:31] MPC801 BURST# AL300A PDIP#
Figure
Power Interface AL300A (Block Diagram)
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CLKout
A[0:31]
RD/WR#
TSIZ[0:1]
'00'
BURST#
Last beat Expects another data BDIP#
DATA
Data valid
Figure
Power Interface AL300A (Timing Diagram)
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AL300A receives data from memory during data phase burst read cycle. AL300A needs more than 32-bit word data, will assert BDIP# signal when data received before last data. AL300A de-asserts BDIP# signal memory stops driving data after receives negation BDIP# signal rising edge clock. typical read operation shown Figure
CLKout
A[0:31]
RD/WR#
TSIZ[0:1]
'00'
BURST#
Last beat Will drive another data BDIP#
DATA
Data sampled
Figure
Typical Burst Read Cycle MPC801
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7.1.4 Relinquishing After transferring 64-byte burst, P_BR# will de-asserted P_CLK cycle same time, P_BB# will high. more data needs transferred, P_BR# will asserted again next clock cycle granted right-of-way (P_BG# from arbiter), P_BB# will asserted next clock cycle. other words, P_BR# will high least P_CLK cycle P_BB# will high least P_CLK cycles between bursts.
Type Interface (P_SEL
7.2.1 Read/Write Cycle Timing with 486-type interface access management functions AL300A using single beat read/write cycle. MPC801 must assert when accessing AL300A. burst cycle related signals such BURST# BDIP# will ignored. During data transfer phase, data transferred from MPC801 AL300A write cycles from AL300A MPC801 read cycle. avoid electrical contention, MPC801 considers "one dead clock cycle" when switching between drivers. MPC801 stop driving data soon samples signal asserted rising edge CLKout signal. read cycle MPC801 accepts data contents valid rising edge CLKout signal which signal sample asserted. with 486-type interface access management function AL300A using two-cycle read/write cycles. must first assert order access AL300A. burst cycle related signals such BLAST# BRDY# will ignored. basic two-clock read/ write cycles initiated processor with assertion address status signal (ADS#) rising edge first clock, with valid cycle definition address. non-burst ready (RDY#) asserted AL300A second clock. RDY# indicates that AL300A presented valid data data pins response read request AL300A accepted data response write request. samples RDY# second clock. cycle completed RDY# asserted (LOW) when sampled, otherwise wait state inserted AL300A. Note that RDY# ignored first clock cycle. BLAST# signal ignored assumed asserted, which means burst cycles supported direct data transfer between AL300A. typical read/write operation shown Figure
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Read/ rite cycle initiated
CLKout
ADS#
A31-A2 MIO#
W/R#
RDY#
Data ready
BLAST#
DATA
Figure
Typical Read/Write Cycle Interface
7.2.2 Burst Cycle Transfer data transfers performed burst mechanism when AL300A acts master. During burst cycle, data strobed into AL300A every clock instead every other clock non-burst cycle. AL300A starts cycle asserted HOLD. After obtaining control bus, AL300A will transfer data from memory using burst cycle. burst cycle transfer starts with AL300A asserting signal (ADS#) driving address same manner non-burst cycle. AL300A indicates that cycle burst cycle holding burst last signal (BLAST#) de-asserted second clock cycle. memory controller must assert burst ready signal (BRDY#) indicating willing burst cycle. These signals addition basic signals bus. Memory attached AL300A must able support burst cycle. Wait cycles inserted slow down transfer rate. AL300A transfers data from system memory bursts four 32-bit words bytes. AL300A will relinquish control another arbitration cycle four 16-byte bursts (64-byte transfer), until data transfer completed. cases when 32-bit data transfer takes place, where BLAST# asserts second clock-cycle transfer cycle, memory controller assert RDY# instead BRDY#.
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AL300A will respond interrupt acknowledge cycles generated providing interrupt vector. This vector programmed writing Interrupt Vector Register. typical burst read/write operation shown Figure
CLKout
ADS#
A31-A4 M/IO#
A3-A2
RD/WR#
RDY#
BRDY#
BLAST#
DATA
Figure
Typical Burst Read/Write Cycle
7.2.3 Relinquishing Since does have P_BB# equivalent signal, HOLD signal serves purposes request hold. will grant AL300A asserted HLDA when both signals active high. Between bursts, AL300A will de-assert HOLD signal (pull low) least P_CLK cycle. more data needs transferred, HOLD will asserted next clock cycle.
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Signal Timing Specification
Table Timing
INPUT SIGNAL P_BURST P_BB P_TS P_TA P_INT P_BDIP BRDY P_BR P_BG MIN. SETUP 8.0ns 8.0ns 8.0ns 8.0ns 8.0ns 8.0ns 8.0ns -8.0ns 8.0ns -8.0ns MIN. HOLD 2.5ns 2.5ns 2.5ns 2.5ns 2.5ns 2.5ns 2.5ns -2.5ns 2.5ns -2.5ns MIN. DELAY 2.0ns 2.0ns 2.0ns 2.0ns 2.0ns 2.0ns 2.0ns 2.0ns 2.0ns -2.0ns -OUTPUT TYP. DELAY -6ns -MAX. DELAY 10.0ns 10.0ns 10.0ns 10.0ns 10.0ns 10.0ns 10.0ns 10.0ns 10.0ns -10.0ns
Table Ring Timing
INPUT SIGNAL RODH ROCTL ROTLH RIDH RICTL RICTLH MIN. SETUP -3.0ns 3.0ns 3.0ns 3.0ns MIN. HOLD -2.0ns 2.0ns 2.0ns 2.0ns MIN. DELAY 4.0ns 4.0ns 4.0ns 4.0ns -OUTPUT TYP. DELAY -MAX. DELAY 10.0ns 10.0ns 10.0ns 10.0ns
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Table Clock Specifications
CHARACTERISTIC ring clock frequency Clock tolerance Duty cycle Maximum frequency Duty cycle -MAX 55/45 55/45 UNIT
Note: riclk/3 <p_CLK min. MHz, riclk)
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Assignments
NAME RICTLH RICTL0 RICTL1 RICTL2 RICTL3 RICTL4 RICTL5 RICTL6 RICTL7 RIDH RID0 RID1 RID2 RID3 RID4 RID5 RID6 RID7 RID8 RID9 RICLK RID10 SIGNAL TYPE
RID11 RID12 RID13 RID14 RID15 RID16 RID17 RID18 RID19 RID20 RID21 RID22 RID23 RID24 RID25 RID26 RID27 RID28 RID29 RID30 RID31 BURST#
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INT# BDIP# BRDY P_MST# P_A2 P_A3 P_A4 P_A5 P_A6 P_A7 P_A8 P_A9 P_A10 P_A11 P_A12 P_A13 P_A14
-I/O -I/O -I/O -I/O -I/O -I/O -I/O
P_A15 P_A16 P_A17 P_A18 P_A19 P_D0 P_D1 P_D2 P_D3 P_D4 P_D5 P_D6 P_D7 P_D8 P_D9 P_D10 P_D11 P_D12 P_D13 P_D14 P_D15 P_D16 P_D17 P_D18
-I/O -I/O -I/O -I/O -I/O -I/O
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P_D19 P_D20 P_D21 P_D22 P_D23 PCLK P_D24 P_D25 P_D26 P_D27 P_D28 P_D29 P_D30 P_D31 P_SEL P_RST ROD31 ROD30 ROD29 ROD28 ROD27
-I/O -I/O -I/O
ROD26 ROD25 ROD24 ROD23 ROD22 ROD21 ROD20 ROD19 ROD18 ROD17 ROD16 ROD15 ROD14 ROD13 ROD12 ROD11 ROD10 ROD9 ROD8 ROD7 ROD6 ROD5
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ROD4 ROD3 ROD2 ROD1 ROD0 RODH ROCTL7 ROCTL6 ROCTL5 ROCTL4 ROCTL3 ROCTL2 ROCTL1 ROCTL0 ROCTLH TEST0 TEST1 TEST2 TEST3
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Electrical Specifications
Note: Operation absolute maximum ratings could cause permanent damage device.
Table Absolute Maximum Ratings
Supply Voltage Input Voltage Output Voltage Storage Temperature -0.3V 3.6V -0.3 0.3V -0.3 0.3V +150
Table Recommended Operation Conditions
Supply Voltage Operating Temperature (Ambient) 3.3V 0.3V (typical)
Table Electrical Characteristics
PARAMETER DESCRIPTION Output voltage-high, Ioh=4mA Output voltage-low, Ioh=4mA High impedance state output current Input current-high (With pull-up pull-down) Input current-low (With pull-up pull-down) Supply current -TYP. -MAX -0.4 UNIT
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AL300A Mechanical Data
208-Pin PQFP Package
25.5
0.20 0.05
0.50 0.01
28.00 0.13 30.6
3.23 0.12
3.68 max. 0.10 min. 1.30 0.20
0.50 0.20 0.10 min.
Figure
AL300A Mechanical Dimensions
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Rev. History Prelim. 1.2a Reformatted edited document. Changed from ground VCC. Prelim 1.2a Updated electrical specifications. Corrected mechanical diagram dimensions. Prelim. Rev. Fully released document. Rev. Changed reference InPReady InPDone. Corrected RD/WR# line figure Rev. Updated statistics collection description section 3.6.
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Index
Numerics Gbit/s Register Descriptions 100Mbit/s Register Descriptions 100Mbit/s Registers AL300A PQFP Package Type Interface (P_SEL Absolute Maximum Ratings Access AL1022 Port Information AL300A MPC801 Burst Cycles AL300A Functional Block Diagram AL300A Host Memory Requirements Access AL300A Overview AL300A Diagram Burst Cycle Transfer Clear AL300A Port Information Clock Specifications Configuration Register (Register Configuration Register (Register Timing Processor Interface Electrical Characteristics Frame Reception Frame Transmission Functional Description Host Register (Register Host Register (Register Host Memory Structure Host Count Hold Host Count Unhold Host Register (Register Host Register (Register Host Register (Register Indirect Access Read Indirect Access Write Interrupt Mechanism Interrupt Vector Register (Intel Mode Only)(Register Lower 32-Bit Word Address Entry Address Table Update Access Services Host Frame Transmission Reception Managed Switch Using Matrix Register (Register Matrix Register (Register Counters Mechanism Registers Statistics Collection Microprocessor Interface Services Microprocessor Interface Description MPC801 Type Interface (P_SEL Descriptions Port Related Etherstat Access Power Miscellaneous Power Interface AL300A (Block Diagram) Power Interface AL300A (Timing Diagram) Product Description Read AL300A Port Information Read/Write Cycle Timing Reading Counters Mechanism Receive Descriptor Field Receive Frame Buffer Initialization Recommended Operation Conditions Register Indirect Access Result Register Register Descriptions Register Structure AL300A Relinquishing RMON Host Group Access Description Input Interface Output Interface Ring Timing Table Convergence Base Address Shadow Register Receive Buffer Ownership (Register Signal Timing Specification Single Beat Read Cycle Zero Wait States Single Beat Write Cycle Zero Wait States Spanning Tree Support Switch Management Engine System Block Diagram System Status Configuration Test Test Register (Register Transmit Frame Initialization Transmit Frame Transfer Notification Types Interface Typical Burst Read Cycle MPC801 Typical Read/Write Cycle Interface Upper 32-Bit Word Address Entry
Reference Only Allayer Communications

Manages Fast Ethernet ports 8-Gigabit Ethernet ports Ethernet interfac

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