Supports 10/100 Mbit/s ports Capable trunking Mbit/s link Trunk fail-o

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Supports 10/100 Mbit/s ports Capable trunking Mbit/s link Trunk fail-o

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AL103 Revision PORT COST 10/100 SWITCH
Supports 10/100 Mbit/s ports Capable trunking Mbit/s link Trunk fail-over feature Full- half-duplex mode operation Speed auto-negotiation through MDIO Built-in storage addresses Design utilize low-cost SGRAM Serial EEPROM interface low-cost system configuration Automatic source address learning Secure mode traffic filtering Broadcast storm control Port monitoring support IEEE 802.3x flow control full-duplex operation Optional backpressure flow control support half-duplex operation Supports store-and-forward mode switching VLAN support AL102A compatible 3.3V operation Packaged 256-pin PQFP
Product Description AL103 eight-port 10/100 Mbit/s dual speed Ethernet switch. low-cost Fast Ethernet switch implemented using AL103 with low-cost SGRAM. AL103 also supports VLAN multiple port aggregation trunks.
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Switch Controller
Buffer Manager
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10/100 High Speed Switch Fabric
Address Control
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Address Table
10/100 EEPROM Interface
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Figure
System Block Diagram
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This document contains proprietary information which shall reproduced, transferred other documents, used other purpose without prior written consent Allayer Communications.
Disclaimer Allayer Communications reserves right make changes, without notice, product(s) described information contained herein order improve design and/or performance. Allayer Communications assumes responsibility liability these products, conveys license title under patent copyright these products, makes representations warranties that these products free from patent copyright infringement unless otherwise specified.
Life Support Applications Allayer Communications products designed life support appliances, systems, devices where malfunctions reasonably expected result personal injury.
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Table Contents
AL103 Overview Descriptions. Functional Description. Data Reception. 3.1.1 3.1.2 3.1.3 3.1.4 3.2.1 3.2.2 3.2.3 Illegal Frame Length. Long Frames False Carrier Events Frame Filtering. Broadcast Storm Control. Frame Transmission. Frame Generation.
Frame Forwarding.
Half Duplex Mode Operation Secure Mode Operation Address Learning 3.5.1 Address Aging. VLAN Support. Port Aggregation (Trunking). 3.7.1 3.7.2 3.7.3 3.7.4 3.7.5 Load Balancing Trunk Fail Over. Trunk Port Assignment Port Based Trunk Load Balancing Based Load Balancing Half Duplex Flow Control (Backpressure) Full Duplex Flow Control (802.3x)
Flow Control 3.8.1 3.8.2
3.10 3.11 3.12 3.13
Queue Management Uplink Port. Port Monitoring. Media Independent Interface (MII) Management. Management MDIO
3.13.1
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3.13.2 3.13.3 3.13.4 3.13.5 3.14 3.14.1 3.14.2 3.14.3 3.14.4 3.14.5 3.14.6 3.15
Management Master Mode Management Slave Mode. Auto-negotiation Mode Other Options. System Initialization Start Stop Write Cycle Operation Read Cycle Operation Reprogramming EEPROM Configuration. EEPROM
EEPROM Interface
SGRAM Interface
Register Description Timing Requirements. Electrical Specifications AL103 Mechanical Data. Appendix (VLAN Mapping Worksheet) Appendix (Port Trunk Port Assignment Work Sheet) Appendix (Suggested Memory Components).
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AL103 Overview
AL103 provides eight 10/100 Mbit/s Ethernet ports. Each port supports both Mbit/s data rate. operation mode auto-negotiated PHY. ports full-duplex capable. device also supports VLAN workgroup segment switching applications. AL103 also supports trunking applications. chip provides optional load-balancing schemes, explicit dynamic. With trunking, possible group four full-duplex links together form single Mbit/s link. Data received from interface stored external memory buffer. AL103 utilizes cost effective SGRAM provide 8-Mbit 16-Mbit buffer memory. During transmission, data obtained from buffer memory routed destination port's output buffer. collision occurs half-duplex operation, control will back retransmit accordance IEEE 802.3 specification. AL103 provides flow control methods. half-duplex operations, optional jamming based flow control (known backpressure) available prevent loss data. With this method flow control, switch will generate signal when receive buffer full sending station will start transmit until line clear. full-duplex mode, AL103 utilizes IEEE 802.3x flow control mechanism. ports support multiple addresses. switch chip supports addresses internally. These addresses shared among eight ports. initialization configuration switch programmed external EEPROM. Field reconfiguration achieved using parallel interface reprogram EEPROM. AL103 also supports port based VLAN. VLAN register used configure destination ports multicast broadcast frames. device also provides levels security intrusion protection. Security implemented port basis. AL103 operates only store forward mode. entire frame checked error frames with errors automatically filtered will forwarded destination port. AL103 also features port monitoring broadcast storm throttling.
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Diagram
PBANC_8 EECLK EEDIO PBCS# PBCAS# PBWE# SYSCLK PBRAS# PBA9_10 PBA0 PBA1 PBA2 PBA3 PBA4 PBA5 PBA6 PBA7 PBA8_9 PBD0 PBD1 PBD2 PBD3 PBD4 PBD5 PBD6 PBD7 PBD16 PBD17 PBD18 PBD19 PBD20 PBD21 PBD22 PBD23 PBD8 PBD9 PBD10 PBD11 PBD12 PBD13 PBD14 PBD15 PBD24 PBD25 PBD26 PBD27 PBD28 PBD29 PBD30 PBD31 PBCLKI
M0CRS M0COL M0TXD3 M0TXD2 M0TXD1 M0TXD0 M0TXEN M0TXCLK M0RXER M0RXCLK M0RXDV M0RXD0 M0RXD1 M0RXD2 M0RXD3 M1CRS M1COL M1TXD3 M1TXD2 M1TXD1 M1TXD0 M1TXEN M1TXCLK M1RXER M1RXCLK M1RXDV M1RXD0 M1RXD1 M1RXD2 M1RXD3 M2CRS M2COL M2TXD3 M2TXD2 M2TXD1 M2TXD0 M2TXEN M2TXCLK M2RXER M2RXCLK M2RXDV M2RXD0 M2RXD1
I.D.
M7RXD3 M7RXD2 M7RXD1 M7RXD0 M7RXDV M7RXCLK M7RXER M7TXCLK M7TXEN M7TXD0 M7TXD1 M7TXD2 M7TXD3 M7COL M7CRS M6RXD3 M6RXD2 M6RXD1 M6RXD0 M6RXDV M6RXCLK M6RXER M6TXCLK M6TXEN M6TXD0 M6TXD1 M6TXD2 M6TXD3 M6COL M6CRS M5RXD3 M5RXD2 M5RXD1 M5RXD0 M5RXDV M5RXCLK M5RXER M5TXCLK M5TXEN M5TXD0 VccM M5TXD1 M5TXD2 M5TXD3
M2RXD2 M2RXD3 M3CRS M3COL M3TXD3 M3TXD2 M3TXD1 M3TXD0 M3TXEN M3TXCLK M3RXER M3RXCLK M3RXDV M3RXD0 M3RXD1 M3RXD2 M3RXD3 MDIO DEVID0 DEVID1 RESET# TESTMODE EPBYPASS M4CRS M4COL M4TXD3 M4TXD2 M4TXD1 M4TXD0 M4TXEN M4TXCLK M4RXER M4RXCLK M4RXDV M4RXD0 M4RXD1 M4RXD2 M4RXD3 M5CRS M5COL
Figure
AL103 Diagram (Top View)
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Descriptions
Table Interface Port
NAME M0TXD3 M0TXD2 M0TXD1 M0TXD0 M0TXEN M0TXCLK M0RXD3 M0RXD2 M0RXD1 M0RXD0 M0RXDV M0RXCLK M0RXER M0CRS M0COL NUMBER DESCRIPTION Transmit Data data transmitted transceiver. Signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. Transmit Enable. Synchronous transmit clock. Transmit Clock Input. Mbit/s Mbit/s. Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge RX_CLK. Receive Data Valid. Receive Clock. Receive Data Error. Carrier Sense. Collision Detect.
Table Interface Port
NAME M1TXD3 M1TXD2 M1TXD1 M1TXD0 M1TXEN M1TXCLK NUMBER DESCRIPTION Transmit Data data transmitted transceiver. Signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. Transmit Enable. Synchronous transmit clock. Transmit Clock Input. Mbit/s Mbit/s.
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Table Interface Port (Continued)
M1RXD3 M1RXD2 M1RXD1 M1RXD0 M1RXDV M1RXCLK M1RXER M1CRS M1COL Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge RX_CLK. Receive Data Valid. Receive Clock. Receive Data Error. Carrier Sense. Collision Detect.
Table Interface Port
NAME M2TXD3 M2TXD2 M2TXD1 M2TXD0 M2TXEN M2TXCLK M2RXD3 M2RXD2 M2RXD1 M2RXD0 M2RXDV M2RXCLK M2RXER M2CRS M2COL NUMBER DESCRIPTION Transmit Data data transmitted transceiver. Signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. Transmit Enable. Synchronous transmit clock. Transmit Clock Input. Mbit/s Mbit/s. Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge RX_CLK. Receive Data Valid. Receive Clock. Receive Data Error. Carrier Sense. Collision Detect.
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Table Interface Port
NAME M3TXD3 M3TXD2 M3TXD1 M3TXD0 M3TXEN M3TXCLK M3RXD3 M3RXD2 M3RXD1 M3RXD0 M3RXDV M3RXCLK M3RXER M3CRS M3COL NUMBER DESCRIPTION Transmit Data data transmitted transceiver. Signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. Transmit Enable. Synchronous transmit clock. Transmit Clock Input. Mbit/s Mbit/s. Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge RX_CLK. Receive Data Valid. Receive Clock. Receive Data Error. Carrier Sense. Collision Detect.
Table Interface Port
NAME M4TXD3 M4TXD2 M4TXD1 M4TXD0 M4TXEN M4TXCLK M4RXD3 M4RXD2 M4RXD1 M4RXD0 M4RXDV NUMBER DESCRIPTION Transmit Data data transmitted transceiver. Signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. Transmit Enable. Synchronous transmit clock. Transmit Clock Input. Mbit/s Mbit/s. Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge RX_CLK. Receive Data Valid.
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Table Interface Port (Continued)
M4RXCLK M4RXER M4CRS M4COL Receive Clock. Receive Data Error. Carrier Sense. Collision Detect.
Table Interface Port
NAME M5TXD3 M5TXD2 M5TXD1 M5TXD0 M5TXEN M5TXCLK M5RXD3 M5RXD2 M5RXD1 M5RXD0 M5RXDV M5RXCLK M5RXER M5CRS M5COL NUMBER DESCRIPTION Transmit Data data transmitted transceiver. Signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. Transmit Enable. Synchronous transmit clock. Transmit Clock Input. Mbit/s Mbit/s. Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge RX_CLK. Receive Data Valid. Receive Clock. Receive Data Error. Carrier Sense. Collision Detect.
Table Interface Port
NAME M6TXD3 M6TXD2 M6TXD1 M6TXD0 M6TXEN NUMBER DESCRIPTION Transmit Data data transmitted transceiver. Signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. Transmit Enable. Synchronous transmit clock.
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Table Interface Port (Continued)
M6TXCLK M6RXD3 M6RXD2 M6RXD1 M6RXD0 M6RXDV M6RXCLK M6RXER M6CRS M6COL Transmit Clock Input. Mbit/s Mbit/s. Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge RX_CLK. Receive Data Valid. Receive Clock. Receive Data Error. Carrier Sense. Collision Detect.
Table Interface Port
NAME M7TXD3 M7TXD2 M7TXD1 M7TXD0 M7TXEN M7TXCLK M7RXD3 M7RXD2 M7RXD1 M7RXD0 M7RXDV M7RXCLK M7RXER M7CRS M7COL NUMBER DESCRIPTION Transmit Data data transmitted transceiver. Signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. Transmit Enable. Synchronous transmit clock. Transmit Clock Input. Mbit/s Mbit/s. Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge RX_CLK. Receive Data Valid. Receive Clock. Receive Data Error. Carrier Sense. Collision Detect.
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Table SGRAM Interface
NAME PBD31 PBD30 PBD29 PBD28 PBD27 PBD26 PBD25 PBD24 PBD23 PBD22 PBD21 PBD20 PBD19 PBD18 PBD17 PBD16 PBD15 PBD14 PBD13 PBD12 PBD11 PBD10 PBD9 PBD8 PBD7 PBD6 PBD5 PBD4 PBD3 PBD2 PBD1 PBD0 PBA9_10 PBA8_9 PBANC_8 NUMBER DESCRIPTION
SGRAM Data Bus.
SGRAM Address. Mbit/s SGRAM, this PBA10 Mbit/s SGRAM this SGRAM Address. Mbit/s SGRAM, this PBA9 Mbit/s SGRAM this SGRAM Address. Mbit/s SGRAM, this PBA8 Mbit/s SGRAM when this connected.
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Table SGRAM Interface (Continued)
PBA7 PBA6 PBA5 PBA4 PBA3 PBA2 PBA1 PBA0 PBCS# PBRAS# PBCAS# PBWE# PBCLKI SGRAM address line PBA0- PBA8 sampled during ACTIVE command (row address) READ/WRITE command (column address with PBA8 defining auto precharge).
Chip Select. Enables disables command decoder SGRAM. SGRAM Address Strobe. SGRAM Column Address Strobe. Write Enable. System Clock Output Drive SGRAM.
Table EEPROM Interface
NAME EEDIO EECLK NUMBER DESCRIPTION EEPROM Serial Data Input Output. EEPROM Serial Clock.
Table Management Interface
NAME MDIO NUMBER DESCRIPTION Management Clock. Management Data Input Output.
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Table Miscellaneous Pins
NAME DEVID0 DEVID1 RESET# TESTMODE EPBYPASS NUMBER DESCRIPTION Device Number. AL103, both pins should connected ground. Reset Test Mode Pin. This should grounded normal operation. This bypasses EEPROM setup. This should tied ground. System Clock. Connect.
SYSCLK
127, 128, 129, 130, 191, 192, 193, 194, 254,
Table Power Interface
NAME NUMBER 100, 102, 104, 118, 120, 122, 144, 146, 165, 167, 168, 187, 189, 205, 208, 217, 232, 108, 121, 124, 126, 147, 149, 151, 155, 169, 171, 173, 177, 190, 202, 224, 239, Ground DESCRIPTION
(3.3V)
3.3V Supply Voltage.
VccM
Supply Voltage Interface. VccM interface) VccM 3.3V (3.3V interface)
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MXTXD3 MXTXD2 MXTXD1 MXTXD0 MXTXEN MXTXCLK MXRXD3 MXRXD2 MXRXD1 MXRXD0 MXRXDV MXRXCLK MXRXER MXCRS MXCOL PBD[n] PBA[n] PBBA PBCS PBRAS PBCAS PBWE PBDSF PBDQM PBCLK
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Switch Controller
Address Control
Address Table Buffer Manager Management Management Information EEPROM Interface EEDIO EECLK MDIO
RESET
Figure
AL103 Interface Block Diagram
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Functional Description
Data Reception
port will into receive-state when RX_DV interface asserted. (Media Independent Interface) presents received data four-bit nibbles that synchronous receive clock Mbit/s Mbit/s). AL103 will then attempt detect occurrence (Start Frame Delimiter) pattern "10101011." preamble data prior discarded. Once detected from interface, frame data forwarded stored buffer switch. 3.1.1 Illegal Frame Length During receiving process, AL103 will monitor length received frame. Legal Ethernet frames should have length less than bytes more than 1536 bytes. frames with illegal frame length discarded. 3.1.2 Long Frames AL103 handle frame size 1536 bytes. frames longer than 1536 bytes will discarded. port continues receive data after 1536th byte, port's data will filtered. port half-duplex mode, port will longer able transmit receive data during long frame reception. 3.1.3 False Carrier Events (Carrier Sense) signal interface asserted receive RX_DV (Receive Data Valid) signal asserted within 16BT (Bit Period), port considered have false carrier event. 3.1.4 Frame Filtering AL103 will make filtering forwarding decisions each frame received based frame routing table, VLAN Mapping, port state, system configuration. Under following conditions, received frames filtered: AL103 will check received frames errors such symbol error, error, short event, runt, long event, etc. Frames with kind error will forwarded their destination port. frame heading source port will filtered. Frames heading disabled receiving port will filtered. input buffer port full, incoming frame will discarded. recommended that flow control used prevent loss data. flow control option enabled, this event will occur. remote station will transmit frame when input buffer becomes available. frame security violation security option enabled receiving port.
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Frame Forwarding
After frame received, both source address (SA) destination address (DA) retrieved. used update port's address table used determine frames destination port. Address Lookup Engine will attempt match destination address with addresses stored address table. there match found, link between source port destination port then established. first destination address "0," frame regarded unicast frame. destination address passed Address Lookup Engine, which returns matched destination port number identify which port frame should forwarded destination port within same VLAN receiving port, frame will forwarded. destination port does belong VLANs specified receiving ports, frame will discarded. event will recorded VLAN boundary violation. There ways that AL103 handles frames with unknown destinations. forwarding decision controlled Flood Control option (System Configuration Register 00). Flood Control disabled, frame will forwarded ports (except receiving port) within same VLANs receiving port. Flood Control option enabled, AL103 will forward frame only uplink port specified receiving port. Note: AL103 defines port either single port trunk. port monitoring function enabled, frame forwarding decision also subject port monitoring configurations. first destination address "1," frame will handled multicast broadcast frame. AL103 does differentiate multicast frames from broadcast frames except reserved bridge management group address, specified table IEEE 802.1d standard. destination ports broadcast frame ports within same VLAN except source port itself. 3.2.1 Broadcast Storm Control unique features provided AL103 Broadcast Storm Control. This option allows user limit number broadcast frames into switch. This option implemented port basis. threshold number broadcast frames programmed System Register (register 01). When Storm Control enabled number cumulated non-unicast frames over programmed threshold, broadcast frame discarded. Storm Control disabled, number non-unicast frames received over programmed threshold, AL103 will forward frame ports (except receiving port) specified within VLANs receiving port. Broadcast-Storm-drop (BConly_SC) enabled System Register (register 02), AL103 will only drop broadcast frames multicast frames.
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3.2.2 Frame Transmission AL103 transmits frames accordance IEEE 802.3 standard. AL103 will send frames with guaranteed minimum (Inter Packet/Frame Gap) 96BT even received frames have less than minimum requirement. AL103 also supports transmission frames with 64BT (optional). This option selected System Register III, Register 3.2.3 Frame Generation During transmit process frame data read from memory buffer forwarded destination port's device di-bits. Seven bytes preamble signal (10101010) will generated first before (10101011). Frame data sent after along with four-bytes end.
Half Duplex Mode Operation
half-duplex operation, logic will abort transmit-process collision detected. Re-transmission frame scheduled accordance IEEE 802.3's truncated binary exponential back-off algorithm. transmit process encountered consecutive collisions, excessive collision error reported AL103 will re-transmit frame unless retry-on-excessive-collision (REC) option System Register (register enabled. When enabled, number collisions reset zero transmission started soon time inter packet passed after last collision. collision detected after transmission, late collision error will reported frame will still retransmitted after proper back-off time. AL103 also provides option aggressive back-off System Configuration Register (SuperMAC). This option allows back-off only three slots. This will create more aggressive channel capture behavior than standard IEEE back-off algorithm.
Secure Mode Operation
AL103 provides security support port basis. Whenever secure mode enabled, port will stop learning addresses. address table each port will remain unchanged. this mode operation, address lookup table will freeze additional address will learned. AL103 provides levels security protection. most severe intrusion protection disabling port intrusion experienced. security management (SecMgmt register will disable port frame with unlearned source address (SA) received from secured port (security violation). alternative enable security local port level without security management. When AL103 configured this way, device will only discard frames that have security violations, which prevents intruders from accessing network.
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Address Learning
Table Lookup Engine provides switching information required route data frames. address lookup table set-up through auto address learning (dynamic) manual entry (static). static addresses assigned address table EEPROM. static address entries will aged updated AL103. After frame received AL103, embedded (SA) destination address (DA) retrieved. source address retrieved from received frame automatically stored buffer. AL103 will then check error security violations, perform search. there error security violation, AL103 will store source address address lookup table. been previously stored another port's table, AL103 will delete from previously stored location. Individual Address 48-bit unique address programmed learned. will masked, i.e. multicast AL103 provides on-chip Address-to-PortID/TrunkID table frame destination lookup operations. AL103 address table contains both static addresses input EEPROM dynamically learned address. learns individual addresses from frame received with errors from local ports. received frames that contain source address learned another port's address table, that hasn't been aged out, perform following based switches; security option selected port, AL103 considers this security violation; port non-protected port, AL103 will delete from previous port's address table update current port's address table. However, static address entry, address will updated. 3.5.1 Address Aging port's address register cleared power-up, hardware reset. aging option enabled, dynamically learned will cleared refreshed within programmed time.
VLAN Support
Each port AL103 assigned multiple VLANs. Frames from source port will only forwarded destination ports within same VLAN domain. broadcast/multicast frame will forwarded ports within VLAN(s) except source port itself. unicast frame will forwarded destination port only destination port same VLAN source port. Otherwise, frame will treated frame with unknown destination port belongs another VLAN, frame will discarded event will recorded VLAN boundary violation. Each port assigned with dedicated uplink port. Unicast frames with unknown destination addresses will forwarded uplink port source port. uplink port either single port trunk. AL103 provides VLAN register ports (register mapping 8-ports (8bits). Each register contains 8-bit indicate VLAN group port.
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VLAN registers hold broadcast destination mask each source port. value will indicate broadcast frames will routed from source port specified port. Note that source port must within source port VLAN, because broadcast frames routed source port. setting VLAN trunking, please following section trunking detail. VLAN Example VLAN worksheet provided Appendix complete VLAN easily simply marking ports wish send broadcast frame example, let's assume want VLAN groups 8-port switch: Group consists Group consists completed VLAN maps shown Table
Table VLAN Port Switch
PORT 6/REG. PORT 7/REG. PORT 0/REG. PORT 1/REG. PORT 2/REG. PORT 3/REG. PORT 4/REG. PORT 5/REG.
PORT
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Port Aggregation (Trunking)
AL103 supports trunking/port aggregation. Port aggregation trunking essentially method treat multiple physical links single logical link. benefit trunking ability group multiple lower speed links into higher speed link. example, four full-duplex Mbps links used single 800-Mbps link. This very useful switch switch, switch server, switch router applications. AL103 considers trunk single port entity regardless trunk composition. four ports grouped together single trunk link. grouping ports trunk must from four ports bottom four ports device, i.e. port port multiple link trunk, links within trunk should have balanced amount traffic order achieve maximum efficiency. requirements transmission that frames being transmitted must order. Therefore, some sort load balancing among links trunk must deployed. AL103 offers methods load balancing which selected System Configuration Register (register 00). 3.7.1 Load Balancing load-balancing methods that AL103 uses support trunking port based address based. Port based load balancing method explicit port assignment scheme. requires each individual port assigned specific link (trunk port) trunk. port assigned, frame might routed trunk randomly which cause frames order. port based load balancing trunk assigned 4-port trunk. During transmission frame, will routed from source port assigned trunk port. When frame received from trunk ports, will routed destination port within VLAN. essence, AL103 treats trunk single port within same VLAN. ports traffic evenly distributed among trunk ports, load balancing achieved aggregate bandwidth trunk high Mbit/s (full-duplex). alternative address based load balancing. When AL103 receives frame with trunk destination, will automatically forward frame port trunk based source, destination, combination source destination address. address load balancing decision based proprietary algorithm. address based load-balancing trunk also assigned 4-port trunk. 3.7.2 Trunk Fail Over link lost trunk ports, frame loss will occur. trunk fail-over feature AL103 prevent frame loss caused link failure trunk port. When trunk fail-over option enabled register (L2Fail), AL103 will automatically shift load from port with lost link next available port. This option available address based loading trunk only. Once port with lost link recovers links AL103 will return original trunk setting.
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3.7.3 Trunk Port Assignment maximum number trunks AL103 two. Port Configuration registers provide ability designate port member trunk. trunk consist four trunk ports. trunk group must consist either four ports bottom four ports, example trunk consist port through port port through port Each trunk port's number sequence corresponding order port devices. example, port (See Figure
AL103
Ports
Trunk Port
Trunk Port
Figure
Trunk Port Numbering
3.7.4 Port Based Trunk Load Balancing port-based load balancing, trunk port must assigned each port defined trunks. port assignment done programming Port Trunk Port Registers 35). port assignment worksheet provided back data sheet. recommended that ports evenly distributed among trunk ports prevent overloading single trunk port. Port Based Load Balancing Example Note: Register bits reference X.Y, where register number number. Appendix provide worksheet port trunk port VLAN assignment. example designing 8-port switch with 3-port based loading trunk. desired trunk ports want assign port trunk port port trunk port port trunk port Port Configuration register bits 15.9, 16.9, 17.9 This assigns ports trunk port. Assign port trunk port port trunk port port trunk port Therefore, port trunk port register bits. 2E.2= 2E.3 2F.2= 2F.3 30.2= 30.3 31.2= 31.3 32.2= 32.3
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Trunk ports should assigned with their port number port trunk Port register. port trunk-port bits follows: 33.2= 33.3 34.2= 34.3 35.2= 35.3 remaining bits zeros port trunk port registers. Assigning VLAN. VLAN should assigned shown. bits while bits 1E.6 1E.7 because port assigned port other ports similarly. Bits through reserved should VLAN mapping registers.
Table VLAN Mapping Port Based Load Balancing Trunk
PORT 6/REG. PORT 7/REG. PORT 0/REG. PORT 1/REG. PORT 2/REG. PORT 3/REG. PORT 4/REG. PORT 5/REG.
PORT
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3.7.5 Based Load Balancing address based load balancing, there need assign port trunk port. AL103 dynamically assigns addresses trunk port. address based trunks consist two, three, four trunk ports. bits chosen their randomness. statistically random bits will ensure good load balancing among trunk-ports. following procedure based load trunk. Select address load trunking setting 00.3 "1." Select trunk ports using Port Configuration Register Assign ports trunk port same VLAN using register When number trunk ports four, following steps required. number trunk ports three, register 2D.8 (L2MAP) "1." TrunkMap1 TrunkMap0 register bits through These bits indicate mapping trunk ports. example, ports used trunk ports, then bits 2D.0 2D.1 "1." ports used trunk ports, bits 2D.5 2D.7. trunk port mapping trunk member bits Port Configuration register must match. Finally, select algorithm based loading. register 2D.10 source address only, combination source destination addresses. port VLAN grouping should include trunk ports. Since AL103 will assign port addresses, frames from single port routed trunk ports. Based Load Balancing Example desired trunk port Therefore, port configuration register bits 15.9, 17.9, 19.9, 1B.9 "1." Select address loading setting 00.3 "1."
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Table VLAN Mapping Based Loading Trunk
PORT 0/REG. PORT 7/REG. PORT 1/REG. PORT 2/REG. PORT 3/REG. PORT 4/REG. PORT 5/REG. PORT 6/REG.
PORT
Note: bits except ports themselves.
Flow Control
AL103 operate different modes, half- full-duplex. Each port operate either full- half-duplex configured have flow control enabled flow control independently port basis. 3.8.1 Half Duplex Flow Control (Backpressure) half-duplex flow control option elected, backpressure will used flow control. Whenever receive frame buffer port full, port will start sending signal through port. remote station after sensing signal will defer transmission. Backpressure flow control applied ensure that there dropped frame. AL103 supports types backpressure, collision based carrier based. Carrier based backpressure generated AL103, when switch port's frame buffer full. AL103 will cease line when port buffer space available frame reception. jamming signal selected from 48BT, 56BT, 65BT, 72BT, 96BT. This selected register bits BpIPGSelEn must select backpressure less than 96BT. Collision based backpressure generated AL103, only when switch port receives frame. AL103 will cease line, when line idle. carrier based backpressure several advantages over collision based backpressure such
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Collision based backpressure cause late collision. After consecutive collisions, could drop frames. AL103 option drop frame after collisions. However, terminal still drop frames.
Therefore, recommend carrier based backpressure preferred method halfduplex flow control. this mode operation, also recommend that signal should less than 96BT. This because terminal might still able transmit frame cause collision. excessive collision could cause frames dropped. AL103 also supports collision-based backpressure customers that prefer collision-based backpressure. 3.8.2 Full Duplex Flow Control (802.3x) full-duplex mode, AL103 will transmit receive frame accordance 802.3x. Note that transmission channel receiving channel operate independently. incoming direction, whenever receive frame buffer port full, port will send PAUSE frame with delay value maximum. PAUSE frame will deter incoming frame from flowing into port. After receive frame buffer reduced below backpressure watermark level (register 11:10), port will then send PAUSE frame with delay value zero resume receiving incoming frame flow. outgoing direction, whenever incoming PAUSE frame with non-zero delay value received through port, port will stop next frame transmission after ongoing frame transmission finished. will start pause timer resume frame transmission either after pause timer expired when PAUSE frame with zero delay value received. When 802.3x flow control option elected, device will program appropriate auto-negotiation capability field. When AL103 used full-duplex mode, recommended that flow control should turned which prevents buffer from overflow loss frames. connected device 802.3x capability, then recommended link setting half-duplex.
Queue Management
AL103 ports have advanced queue management algorithm optimal switching performance. frames received AL103 stored into shared memory. frame unicast type, location frame buffer then passed destination output queue manager. Destination Output Queue Manger extract frame from buffer transmit. output queue manager receives more frames than send out, simply stores locations frames transmits them after transmitting current frame. There ways manage output queues. method that eight output queues will share frame buffer shared memory limit, without limit each individual queue. When this method chosen setting 00.15 "0," shared buffer memory allocated incoming frame from port long free buffer available. When extreme cases congestion experienced, such traffic merging into single port speed mismatch long period time, single output queue occupy entire shared buffer causing other ports drop frames.
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this case, flow control option recommended when frame buffer full, incoming frames will backpressured. prevent buffer starvation, half memory reserved allocated each port while other half shared. other option limit number frames that each output queue store. This option selected setting 00.15 "1." output queue watermark System Configuration Register (Register Bits 7:6) keep balance between utilization fairness buffer sharing. This method prevents other ports from suffering performance reduction single port experiencing extreme congestion. severe congestion experienced single port, only that port will suffer from frame loss because buffer limited dedicated portion. Other ports will experience frame loss congestion problem other ports since other ports retain their allocated buffer space. When output queue multicast queue experiences buffer full condition, AL103 will backpressure incoming frames flow control enabled. watermark buffer full condition selected register
3.10 Uplink Port
uplink port provides means connect switch with repeater hub, workgroup switch, router, type interconnecting device compliance with IEEE 802.3 standards. flood control enabled, AL103 will send frames with unmatched multicast/ broadcast frames uplink port. very important that each port assigned uplink port Port Configuration Register to1C), data frames might lost. uplink port should configured within same VLAN source port. uplink port member VLANs, broadcast multicast frames will forwarded designated uplink port. Multiple VLANs share same uplink port. AL103 will direct following frames uplink port: Frames with unicast destination address that doesn't match with address stored switch. Frames with broadcast/multicast destination address uplink port same VLAN.
Note: When configuring uplink port, uplink port should designate itself uplink port.
3.11 Port Monitoring
AL103 supports port monitoring. This feature provides complete network monitoring capability Mbit/s. copy egress (TX) data ingress (RX) data monitored port sent their respective snooping ports. monitored port selected register AL103 allows transmit receive data monitored different snooping ports. snooping ports also selected register
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3.12 Media Independent Interface (MII)
each port AL103 connected through standard interface. receiving frames, received data (RXD[3:0]) sampled rising edge receive clock (RX_CLK). Assertion receive data valid (RX_DV) signal will cause look start SFD. transmission, transmit data enable (TX_EN) signal asserted when first preamble nibble sent transmit data (TXD[3:0]) lines. transmit data clocked rising edge transmit clock (TX_CLK). Prior transaction, AL103 will output 32-bits preamble signal then after preamble, "01" signal used indicate start frame.
3.13 Management
AL103 supports transceiver management through serial MDIO signal lines. device provides modes management, master slave mode. master mode operation, AL103 controls operation modes link slave mode controls operating mode. 3.13.1 Management MDIO write operation, device will send "01" signal write operation. Following "01" write signal their will 5-bit address device 5-bit register address. "10" turn around signal then used avoid contention during read transaction. After turn around, 16-bit data will written into register then after completion write transaction, line will high impedance state. read operation, AL103 will output a"0" indicate read operation after start frame indicator. Following "10" read signal will 5-bit address device 5-bit register address. Then, AL103 will cease driving MDIO line, wait time. During this time, MDIO should high impedance state. device will then synchronize with next driven device, continue read 16-bit data from register. detail timing requirements management signals described section "Timing Requirement." 3.13.2 Management Master Mode master mode, AL103 will continuously poll status devices through serial management interface. device will also configure capability fields ensure proper operation link. configuration link automatic. link capability programmed AL103 through port configuration register. AL103 reads from standard IEEE registers determine auto-negotiated operating speed mode. there need manually operation mode because flow control cabling issues AL103 port operation mode through MDIO interface (see EEPROM section programming AL103). 3.13.3 Management Slave Mode slave mode, controls programming operating mode. AL103 will continuously poll status devices through serial management interface determine operation mode link.
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This mode management very useful unmanaged switches. operating mode link changed programming mode through jumper. AL103 also supports 100Base-TX transceivers without MDIO interface interface. When MDIO disabled, AL103 will operate operation mode specified port configuration register (register 1C). 3.13.4 Auto-negotiation Mode AL103 also turn auto-negotiation capability PHY. When auto-negotiation turned off, AL103 slave mode transceiver will determine link's operating mode. 3.13.5 Other Options Some Legacy Fast Ethernet devices other cost devices have auto-negotiation capability. those cases when transceiver will able perform auto-negotiation, switch transceiver will typically parallel detection update information transceiver's register. Unfortunately, such register addresses vendor specific. AL103 provides register (register specify register address AL103 read. AL103 will read from that register configure port operation accordingly. Register also provides some additional flexibility's some PHYs market. general, system designer should devices port port port Certain PHYs utilize address 00000 broadcast address. register allows AL103 start with address 01000. This provision allows engineers work around PHY's that have problems handling address 00000. Quad PHYs have 2-port ordering chip pinout, both clockwise counter clockwise. Register programs AL103 port order either direction. This provision enables engineers easily implement designs with PHY. There also slow MDIO clock KHz) available that capable handling high speed MDIO clock. some reason, transceiver connected device that device fails auto-negotiate, AL103 will default data rate duplex mode default setting port configuration register.
3.14 EEPROM Interface
AL103 provides three functions with EEPROM interface: system initialization, obtaining system status, reconfiguring system real time. AL103 uses 24C02 serial EEPROM device (2048 bits organized bits 3.14.1 System Initialization EEPROM interface provided that manufacturer provide pre-configured system their customers which allows customers change reconfigure their system retain their preferences. EEPROM contains configuration initialization information, which will accessed power reset.
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reset held low, AL103's EEPROM interface will into high impedance state. This feature very useful reprogramming EEPROM during installation reconfiguration. EEPROM reprogrammed external parallel port. reprogramming using parallel port, signal used hold RESET low. EEPROM interface will then high-impedance state. external device then program EEPROM through EEDIO EECLK pins. EEPROM address should 000. 3.14.2 Start Stop write cycle started start ended stop bit. start transition from high EEDIO when high. operation terminates when EEDIO goes from high when high. Following start condition, writing device must output address EEPROM. most significant four EEPROM address device type identifier which address 1010. EEPROM device address should 000.
EECLK
EEDIO
Data Address Valid
START
Data Change
STOP
Figure
EEPROM Start Stop
3.14.3 Write Cycle Operation EECLK output from AL103 while EEDIO bi-directional signal. When accessing EEPROM, reset held initialization AL103 must finished before writing operation begin. typical write operation shown Figure
Device Address
Start
Stop
8-Bit Word Address
8-Bit Data
Acknowledge
Acknowledge
Acknowledge
Figure
EEPROM Write Cycle
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3.14.4 Read Cycle Operation Read operations initiated same manner write operations, with exception that EEPROM address "1."
Device Address Device Address
Start
Start
Stop
8-Bit Word Address
8-Bit Data
EEDIO Acknowledge Acknowledge Acknowledge Acknowledge
Figure
EEPROM Read Cycle
3.14.5 Reprogramming EEPROM Configuration There ways that system reconfigured. Figure shows application using parallel interface reprogram EEPROM. this application, parallel port holds reset pins low, which forces EEDIO pins into high impedance. Once pins high impedance, EEPROM programmed parallel port. Once parallel port releases reset pins, devices will start download EEPROM data reconfigure devices. alternate reconfiguring system directly change register settings AL103. After initialization, EEPROM interface virtual EEPROM. order this method work, EEPROM's device address must 000, while AL103's address will 100. customer program AL103 EEPROM. read write timing same EEPROM. Because read well write AL103, registers status read from AL103. This will serve very useful tool diagnostic unmanaged switch.
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Reset
AL103
EECLK EEDIO
Parallel Port EEPROM
Figure
EEPROM Parallel Port
3.14.6 EEPROM Table shows EEPROM address cross-referenced register/bit AL103. Addresses through configuring device. They downloaded AL103 after reset power Since AL103 registers 16-bit wide, takes EEPROM addresses each AL103 register. Even numbered EEPROM addresses corresponds upper byte AL103 registers while numbered EEPROM addresses corresponds lower byte AL103 registers. Address should programmed 0000 0001 0001 0100. address indicates last address entry. static address used switch, address should programmed. Addresses used programming static address entry. following format example Static Entry Address 70-7F.
Table Static Address Entry Format EEPROM
EEPROM ADDRESS
Reserved (Must zero) Reserved Port 000XXX Trunk 100YYY
Address [47:40] Address [39:32] Address[31:24] Address[23:16] Address[15:8] Address[7:0]
Note: represents port represents Trunk
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Table AL103 EEPROM Mapping
EEPROM PHYSICAL ADDRESS 00-01 02-03 04-05 06-07 08-09 0A-0B 0C-0D 0E-0F 10-11 12-13 14-15 16-17 18-19 1A-1B 1C-1D 1E-1F 20-21 22-23 24-25 26-27 28-29 2A-2B 2C-2D 2E-2F 30-31 32-33 34-35 36-37 System Configuration System Configuration System Configuration Reserved (Value must 0000 0001 0100) Reserved Vendor Specific Port Monitoring Configuration Reserved Reserved Reserved Reserved Reserved Reserved Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration DESCRIPTION
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Table AL103 EEPROM Mapping (Continued)
38-39 3A-3B 3C-3D 3E-3F 40-41 42-43 44-45 46-47 48-49 4A-4B 4C-4D 4E-4F 50-51 52-53 54-55 56-57 58-59 5A-5B 5C-5D 5E-5F 60-61 62-63 64-65 66-67 68-69 6A-6B 6C-6D 70-77 Port Configuration Reserved (Must zero) Port VLAN Reserved (Must zero) Port VLAN Reserved (Must zero) Port VLAN Reserved (Must zero) Port VLAN Reserved (Must zero) Port VLAN Reserved (Must zero) Port VLAN Reserved (Must zero) Port VLAN Reserved (Must zero) Port VLAN Miscellaneous Register Checksum Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Reserved Last Static Entry EEPROM Address (Value must Static Entry) Static Entry
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Table AL103 EEPROM Mapping (Continued)
78-7F 80-87 88-8F 90-97 98-9F A0-A7 A8-AF B0-B7 B8-BF C0-C7 C8-CF D0-D7 D8-DF E0-E7 E8-EF F0-F7 F8-FF Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry
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3.15 SGRAM Interface
ports AL103 work Store-And-Forward mode that ports support both Mbps Mbps data speed. AL103 utilizes central memory buffer pool, which shared ports within same device. After frame received, passed across SGRAM interface stored buffer. During transmit, frame retrieved from buffer pool forwarded destination port. AL103 designed Mbit SGRAM Mbit SGRAM achieve cost high performance. SGRAM accessed Page Burst Access Mode very high-speed access. This burst mode repeatedly sent same column. burst mode reaches column address, then wraps around first column address (=0) continues count until interrupted read/write, pre-charge, burst stop command. AL103 will initialize SGRAM automatically pre-charges banks inserts eight auto-refresh commands. will also program mode registers AL103's read write operations. SGRAM essentially SDRAM. Dynamic memories must refreshed periodically prevent data loss. SGRAM uses refresh address counters refresh automatically. SGRAM autorefresh command generates pre-charge command internally SGRAM. AL103 will insert auto-refresh command once every microseconds.
Register Description
Table Register Tables Summary
REGISTER 06-0C REGISTER DESCRIPTION System Configuration System Configuration System Configuration Reserved Testing Register Vendor Specific Status Reserved Port Configuration Port Configuration Port Configuration Port Configuration REVERSE EEPROM ADDRESS 00,01 02,03 04,05 06,07 08,09 0A,0B 0C-19 1A,1B 1C,1D 1E,1F 20,21
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Table Register Tables Summary (Continued)
Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Reserved Port VLAN Reserved Port VLAN Reserved Port VLAN Reserved Port VLAN Reserved Port VLAN Reserved Port VLAN Reserved Port VLAN Reserved Port VLAN Miscellaneous Register Port Trunk Port Assignment 22,23 24,25 26,27 28,29 2A,2B 2C,2D 2E,2F 30,31 32,33 34,35 36,37 38,39 3A,3B 3C,3D 3E,3F 40,41 42,43 44,45 46,47 48,49 4A,4B 4C,4D 4E,4F 50,51 52,53 54,55 56,57 58,59 5A,5B 5C,5D
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Table Register Tables Summary (Continued)
36-38 Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Reserved System Status Register Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Indirect Resource Access Command Indirect Resource Access Data Indirect Resource Access Data Indirect Resource Access Data Indirect Resource Access Data Check 5E,5F 60,61 62,63 64,65 66,67 68,69 6A,6B 6C-71 72,73 74,75 76,77 78,79 7A,7B 7C,7D 7E,7F 80,81 82,83 84,85 86,87 88,89 8A,8B 8C,8D 8E,8F
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System Configuration Register (Register System Configuration Registers global system configuration registers. options selected these registers affects overall system operation.
Table System Configuration Register (Register
NAME OutQMgmt DESCRIPTION Output Queue Management Method. Output queue limited until frame buffer full. Output queue limited output queue watermark specified register bits [7:6]. Flood Control. Control forwarding unicast frames with unknown destination received from non-uplink ports. Enable. Frames received with unknown unicast destination address will forwarded ports (excluding receiving port) within VLANs specified receiving port. Disable. Frames received with unknown unicast destination address will forwarded uplink port specified receiving port. Security Enforcement. Auto security off. security violation secured port will change port state. Auto security security violation secured port will cause port into DISABLE state. Switch Table Entry Aging Control. Disable. table aging process will stopped. Enable. table aging process will running every dynamically learned table entry. Reserved (Must 0000). Port Incoming Frame Flow Monitoring Enable Control. Disable Enable Port Outgoing Frame Flow Monitoring Enable Control. Disable Enable Output Queue Watermark. Watermark selection output queues multicast queue full conditions. Mbit/s SGRAM 00:128; 01:512; 10:768; 11:Test Mode. Mbit/s SGRAM 00:64; 01:256; 10:384; 11:Test Mode. value
FloodCtl
SecMgmt
AgeEn
11~10
Reserved PInMon
POutMon
OutQWM
Reserved
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Table System Configuration Register (Register (Continued)
L2Trunk Layer Trunk Loading Method. Port based loading. Trunking decisions will based Trunk Port Assignment Registers. address based loading. Trunking decisions will based source port addresses. Frame Time Enable. Device will timeout frames based MaxDelay. Device will timeout frames. Reserved (Must 00).
TimeoutEN
Reserved
Table System Configuration Register (Register
15~8 NAME MaxAge MaxDelay DESCRIPTION Maximum Dynamically Learned Entries. 0000 0000: sec. 1111 1111: sec. Maximum Frame Transition Delay Through Switch. second. seconds. seconds. seconds. Maximum Number Broadcast Frames That Accumulated Each Input Frame Buffer. frames. frames. frames. frames. Disable. Device will perform IEEE standard exponential back-off algorithm when collision occurs. Enable. When collisions occur, AL103 will back slots. Retry Excessive Collision. Normal collision handling. Retry transmission after consecutive collisions. Select Bits Position Address Trunk Assignment. Source address [1:0]. Source address [3:2]. Source address [5:4]. Source address [7:6].
MaxStorm
SuperMAC
L2TbitSel
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Table System Configuration Register (Register
NAME Reserved DISPHYReset Reserved (Must Reset Option. Reset link down. Don't reset link down. Enable skip register read during auto-negotiation Seeq PHY. Don't skip. Skip Reserved (Must Resolution. Normal aging. Slow down aging. Backpressure Select Enable. Backpressure 96BT. According BpIPGSel value. Control. 96BT 64BT Reserved SGRAM Select. Mbit SGRAM Mbit SGRAM Backpressure Control. Carrier based. Collision based. Backpressure Select. 48BT; 56BT; 65BT; 72BT. Reserved Flow control multicast. Flow control multicast/broadcast. DESCRIPTION
Skip_Reg6
12~11
Reserved AgeRes
BpIPGSelEn
IPG64
Reserved SG16M
BPCOL
BpIPGSel Reserved BCdrop_SC
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Reserved Register (Register This register reserved Allayers use. bits should 0000 0001 0001 0100. Testing Register (Register Most bits this register reserved factory testing except WmarkSel bits. These bits level buffer trigger backpressure eliminate buffer overflow.
Table Testing Register (Register
15~12 11~10 NAME Reserved WmarkSel Reserved Backpressure Watermark Select. Backpressure available block count Backpressure available block count Backpressure available block count Backpressure available block count Mbit/s SGRAM). Backpressure available block count Mbit/s SGRAM). Each block byte. Reserved DESCRIPTION
Reserved
Vendor Specific Register (Register This register used program vendor-specific options. also used programming Vendor Specific register location location operation status.
Table Vendor Specific Register (Register
12~8 NAME PHYAD MclkSpd PortOrder PHYOpReg PHYSpBit PHYDxMode DESCRIPTION Setting this will program MDIO address Setting this will reduce MDIO clock speed KHz. Setting this will reverse ID/port number switch. PHY's Operation Status Register Number. PHY's Data Rate Status Register Number. PHY's Operating Duplex Mode Status Register Number.
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Table Port Monitoring Configuration (Register
14~10 NAME Reserved MdPID MgIPID MgOPID Reserved Monitored Port Snooping Port Incoming Frame Flow. Snooping Port Outgoing Frame Flow. DESCRIPTION
Reserved Registers (Registers These registers reserved must zero. Port Configuration Registers (Registers Registers local port configuration. There port configurations port. Port port configuration uses register Port register etc.
Table Port Configuration Register
15~10 NAME UpLinkID DESCRIPTION Uplink Associated with Port. 0XXYYY: Port with device port 100XXN: Trunk with device trunk Others: Reserved Trunk Member Port. Individual port. Member trunk port. Reserved (Set Broadcast Storm Control Enable. Storm control disable. broadcast frame will throttled. Storm control enable. accumulated number broadcast frames input buffer port over threshold specified system configuration register, incoming broadcast frames will discarded until number been reduced below threshold. Intrusion Protection. Security control frames received from nonuplink ports. Security off. forwarding decision made about frames received from port will involve source address checking. Security frames received from port with unknown source address with source address learned previously from another port will discarded. Reserved (Set
Tmember
Reserved StormCTL
Security
Reserved
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Table Port Configuration Register (Continued)
LrnDis Learning Disable. Source address from this port will learned. Source address from this port will learned. Must Reserved (Set
Reserved Reserved
Table Port Configuration Register
15~14 NAME Reserved Reserved SkipANDone FlowCtrlFdEn FlowCtrlHdEn MDIOCfg[3:0] Reserved Reserved (Set Ignore Auto-Negotiation Complete Wait Link Flow Control Full-duplex Enable. Flow Control Half-duplex Enable. MDIO Configuration. 0001: Master mode management. 0010: Slave mode management. 0111: Force mode. MDIO Disable. MDIO enabled. MIDO disabled. This relevant when MDIO enabled. When MDIO disabled, this forces port into link link down state. Force Full-duplex Mode. Force Half-duplex Mode. Force Full-duplex Mode. Force Half-duplex Mode. DESCRIPTION
MDIODis
LinkUp PrtMode100F PrtMode100H PrtMode10F PrtMode10H
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Port VLAN Registers (Registers These registers provide VLAN each port. Registers reserved. values these reserved registers should zero. VLAN worksheet provided Appendix
Table Port VLAN Registers (Registers
15~8 NAME Reserved Port7VLAN Should Port VLAN Corresponding Port Non-member port. Member port. Port VLAN Corresponding Port Non-member port. Member port. Port VLAN Corresponding Port Non-member port. Member port. Port VLAN Corresponding Port Non-member port. Member port. Port VLAN Corresponding Port Non-member port. Member port. Port VLAN Corresponding Port Non-member port. Member port. Port VLAN Corresponding Port Non-member port. Member port. Port VLAN Corresponding Port Non-member port. Member port. DESCRIPTION
Port6VLAN
Port5VLAN
Port4VLAN
Port3VLAN
Port2VLAN
Port1VLAN
Port0VLAN
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Table Miscellaneous Register (Register
15~11 NAME Reserved L2DASA value Select Algorithm Based Loading. only. Trunk Link Fail Over. Don't fail-over when trunk port fails. Allow link fail-over trunking. Enable Port Based Trunking Option. Disable Enable Based Trunk Port Mapping Trunk Non-trunk port. Trunk port. Based Trunk Port Mapping Trunk Non-trunk port. Trunk port. DESCRIPTION
L2Fail
L2MAP
TrunkMap1
TrunkMap0
Port Trunk Port Assignment Registers (Registers Port Trunk Port assignment register assigns port trunk port-based load balancing trunking. Please example trunking section. port trunk port work sheet provided Appendix
Table Port Trunk Port Assignment Registers (Registers
15~4 NAME Reserved Trunk1 Should Trunk Port Trunk Port Port Port Port Trunk Port Trunk Port Port Port Port DESCRIPTION
Trunk0
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Table System Status Register (Register
NAME EPTimeOut DESCRIPTION EEPROM Time Out. EEPROM initialized device. EEPROM found. Default configuration. SGRAM Initialization Done. SGRAM initialization done. SGRAM initialization done. SRAM Initialization Done. SRAM initialization done. SRAM initialization done. Register Initialization Done. AL103 register initialization done. AL103 register initialization done. Traffic Counter. 0000: Minimum traffic. 1111: Maximum traffic. Reserved 0101: AL103
Sgraminitdone
Sraminitdone
Reginitdone
11~8
TrafCnt
Reserved Version
Port Operation Status Registers (Register Registers status indication port basis. These read only register. Port port status register Port register 3B.and port register
Table Port Operation Status Registers (Register
NAME LinkFail Port Link Status. Normal Fail Port Status. Normal Error Port Security Violation. Normal Violation DESCRIPTION
PHYError
Sviolation
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Table Port Operation Status Registers (Register (Continued)
FlowCtrl Flow Control. port mode ([1:0]) 2'b01 2'b11: Pause disable. Pause enable. port mode ([1:0]) 2'b00 2'b10: Backpressure based CRS. Backpressure based collision. Port Broadcast Storm Status. Normal Stormed Port Input Buffer Full Status. Normal Input buffer full experienced. Table Entry Unavailability Learning. Normal. Unavailability experienced. Port Jabber Status. Normal Jabber experienced. Port Late Collision Status. Normal Late collision experienced. Port Transmit Pause Status. transmit pause experienced. Transmit pause experienced. Port Carrier Sense Loss During Transmission Status. carrier sense loss experienced. Carrier sense loss experienced. False Carrier Status. Transmit Queue Underflow Status. Normal Underflow experienced. Frame Time Out. Normal Frame time experienced. Port Operating Mode. half-duplex. full-duplex. half-duplex. full-duplex.
Stormed
InBFull
TblUNAVL
Jabbered
LateCOL
TxPaused
CRSLoss
FalseCRS Underflow
TimeOut
PortMode
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Indirect Resource Access Command Register (Register Indirect resource access command allows management (Reverse EEPROM Method) access other resources other than AL103 register values. registers, both internal external address tables, SGRAM contents accessed using this command.
Table Indirect Resource Access Command Register (Register
NAME CmdDone DESCRIPTION Command Done. Execute command. Command done. Clear this execute command. When finished with command, AL103 will back "1." Read/Write Operation Command. Read operation. Write operation. Type Accessed Resource. 000: registers. 001: EEPROM 010: SGRAM 011: address table Read: table address read. Write: address learn. 100: address table Read: address search. Write: address delete. 101-111: Reserved External Address Table Read. ResType Operation On-chip address table read. Off-chip address table read. Address Entry Within Accessed Resource.
Operation
13~11
ResType
ExtRD
10~0
ResAddr
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Indirect Resource Access Data Registers Indirect Resource Access Data through used with indirect resource access command.
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data
Table Check (Register
15~8 NAME CheckSum Reserved DESCRIPTION Check Value AL103 Register Contents.
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Timing Requirements
Table Transmit Timing
SYMBOL ttdv ttxev DESCRIPTION TXCLK valid time. TXCLK TXEN valid time. UNIT
TXCLK
ttxev ttxev
TXEN
ttdv
DATA
DATA
DATA
DATA
DATA
DATA
Figure
Transmit Timing
Table Receive Timing
SYMBOL trxds trxdh DESCRIPTION RX_DV, RXD, RX_ER, setup time. RX_DV, RXD, RX_ER hold time. UNIT
RXCLK
trxdh
RXEN
trxds trxdh
DATA
DATA
DATA
DATA
DATA
DATA
Figure
Receive Timing
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Table Management (MDIO) Read Timing
SYMBOL DESCRIPTION high time. time. period. MDIO setup time. MDIO hold time. UNIT
MDIO
Figure
Management Read Timing
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Table Management (MDIO) Write Timing
SYMBOL DESCRIPTION high time. time. period. MDIO output delay. UNIT
MDIO
Figure
Management Write Timing
Table SGRAM Refresh Timing
SYMBOL tCHI tCKH tCKS DESCRIPTION Access hold time. Access setup time. PBCS#, PBRAS#, PBWE# hold time. Clock high level width. System clock cycle time. hold time. setup time. Clock level width. PBCS#, PBRAS#, PBWE# setup time. Precharge command period. Auto-refresh auto-refresh period. UNIT
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PBCLK tCKS tCKH
tCHI
Command
Precharge
Auto Refresh
Auto Refresh
Active
BANK
BANK
Address
Don't Care
Figure
SGRAM Refresh Timing
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Table SGRAM Read Timing
SYMBOL tCHI tCKH tCKS tRAS tRCD DESCRIPTION Access time. Access hold time. Access setup time. PBCS#, PBRAS#, PBWE# hold time. Clock high level width. System clock cycle time. hold time. setup time. Clock level width. PBCS#, PBRAS#, PBWE# setup time. Data high impedance time. Data impedance time. Data hold time. Active precharge command period. Active read delay. UNIT
Note: This timing requirement SGRAM running Latency Typically speed grade SGRAM needs used.
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tCHI
PBCLK
tCKS
tCKH
BURST TERM.
Command
Active
READ
A0-A7
column
PBBA
BANK BANK
tRCD (Bank Latency
Dout
Dout
Dout
Dout
Dout
Dout
location within same
tRAS (Bank
Figure
SGRAM Read Timing
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Table SGRAM Write Timing
SYMBOL tCHI tCKH tCKS tRAS tRCD DESCRIPTION Access hold time. Access setup time. PBCS#, PBRAS#, PBWE# hold time. Clock high level width. System clock cycle time. hold time. setup time. Clock level width. PBCS#, PBRAS#, PBWE# setup time. Data hold time. Data setup time. Active precharge command period. Active read delay. 100,000 UNIT
Note: This timing requirement SGRAM running Latency Typically speed grade SGRAM needs used.
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tCHI
PBCLK
tCKS
tCKH
Command Active write BURST TERM.
A0-A7
column
BANK
PBBA
BANK
tRCD (Bank tRAS (Bank
Don't Care location within same Undefined
Figure
SGRAM Write Timing
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Electrical Specifications
Note: Operation absolute maximum ratings extended period time could cause permanent damage device.
Table Maximum Ratings
Supply Voltage (Vcc) Input Voltage Output Voltage Supply Voltage Input Voltage Output Voltage Storage Temperature -0.3V 3.6V -0.3 0.3V -0.3 0.3V -0.6V 6.0V -0.6 Vcc5 0.3V -0.6 Vcc5 0.3V +150
Table Recommended Operation Conditions
Supply Voltage Operating Temperature Power Dissipation 3.3V 0.3V (typical)
Table Electrical Characteristics
PARAMETER DESCRIPTION Output voltage-high, Ioh=4mA Output voltage-low, Ioh=4mA High impedance state output current Input current-high (With pull-up pull-down) Input current-low (With pull-up pull-down) Input high voltage Input voltage Supply current 0.7*Vcc 0.3*Vcc UNIT
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AL103 Revision
AL103 Mechanical Data
PQFP Package
25.2
0.18 0.04
0.40
28.00 0.10 30.6 0.15
3.23 0.07
4.07 max. 0.60 0.10 0.25 1.30 0.10
0.35 0.10 0.25 min.
Figure
AL103 Mechanical Dimensions
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AL103 Revision
Appendix (VLAN Mapping Worksheet)
PORT 6/REG.
PORT
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PORT 7/REG.
PORT 0/REG.
PORT 1/REG.
PORT 2/REG.
PORT 3/REG.
PORT 4/REG.
PORT 5/REG.
AL103 Revision
Appendix (Port Trunk Port Assignment Work Sheet)
PORT 0/REG.
PORT 1/REG.
PORT 2/REG.
PORT 3/REG.
PORT 4/REG.
PORT 5/REG.
PORT 6/REG.
TRUNK PORT
BIT/ VALUE
TRUNK BITS TRUNK BITS
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PORT 7/REG.
AL103 Revision
Appendix (Suggested Memory Components)
Note: This only partial list memory components that used Allure devices. AL103 uses Frame Buffer SGRAM chips that require 32-bit wide SGRAM SDRAM, that faster with latency following lists some memory that used AL103.
DEVICE
FREQ.
Mbit SGRAM
Mbit SGRAM
AL103
MoSys MG802C256Q-10 Etron EM635327Q-8
MoSys MG802C512L-8 Etron EM636327Q-8 Winbond W971632AF-7 MS82V16520-7
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AL103 Revision
Rev. History (Prelim. 1.1a) Reformatted edited document. Added AL103 overview. Added memory information appendix III. Added management timing diagrams. Added RMII timing diagrams. Rev. History (Prelim. 1.1a 1.2) Changed bits 11~15 reserved Miscellaneous Register, Table Revised Queue Management (3.9) section. Prelim. Rev. Fully released document.
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Index
Address Aging Address Learning AL103 Interface Block Diagram AL103 Overview AL103 Diagram (Top View) Appendix (VLAN Mapping Worksheet) Appendix (Port Trunk Port Assignment Work Sheet) Appendix (Suggested Memory Components) Broadcast Storm Control Check (Register Data Reception Electrical Characteristics EEPROM Interface EEPROM EEPROM Read Cycle EEPROM Start Stop EEPROM Write Cycle False Carrier Events Flow Control Frame Filtering Frame Forwarding Frame Generation Frame Transmission Full Duplex Flow Control (802.3X) Functional Description Half Duplex Flow Control (Backpressure) Half Duplex Mode Operation Illegal Frame Length Indirect Resource Access Command Register (Register Indirect Resource Access Data Register (Register Indirect Resource Access Data Register (Register Indirect Resource Access Data Register (Register Indirect Resource Access Data Register (Register Load Balancing Long Frames Based Load Balancing Maximum Ratings Media Independent Interface (MII) Interface Port Interface Port Interface Port Interface Port Interface Port Interface Port Interface Port Interface Port Management Interface Receive Timing Transmit Timing Miscellaneous Pins Miscellaneous Register (Register Auto-negotiation Mode Other Options Management Management (MDIO) Read Timing Management (MDIO) Write Timing Management Master Mode Management MDIO Management Slave Mode Descriptions Port Aggregation Port Based Trunk Load Balancing Port Configuration Register Port Configuration Registers (Registers Port Monitoring Port Monitoring Configuration (Register Port Operation Status Registers (Register Port Trunk Port Assignment Registers (Registers Port VLAN Registers (Registers Power Interface Product Description Queue Management Recommended Operation Conditions Register Tables Summary Reprogramming EEPROM Configuration Reserved Register (Register Reserved Registers (Registers Secure Mode Operation SGRAM Interface SGRAM Read Timing SGRAM Refresh Timing SGRAM Write Timing Static Address Entry Format EEPROM System Block Diagram System Configuration Register (Register System Configuration Register (Register System Configuration Register (Register System Initialization
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AL103 Revision
System Status Register (Register Testing Register (Register Trunk Fail Over Trunk Port Assignment Trunk Port Numbering Uplink Port Vendor Specific register (Register VLAN Port Switch VLAN Mapping Port Based Load Balancing Trunk VLAN Support
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Supports 10/100 Mbit/s ports Capable trunking Mbit/s link Trunk fail-o

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