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Supports eight 10/100 Mbit/s Ethernet ports with interface Capable tru


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AL102A Revision PORT COST 10/100 SWITCH
Supports eight 10/100 Mbit/s Ethernet ports with interface Capable trunking Mbit/s link Full- half-duplex mode operation Speed auto-negotiation through MDIO Built-in storage addresses Designed utilize low-cost SGRAM Serial EEPROM interface low-cost system configuration Automatic source address learning Secure mode traffic filtering Broadcast storm control Port monitoring support IEEE 802.3x flow control full duplex operation Optional backpressure flow control support half-duplex operation Supports store-and-forward mode switching VLAN support 3.3V operation Packaged 256-pin PQFP
Product Description AL102A eight-port 10/100 Mbit/s dual speed Ethernet switch. low-cost Fast Ethernet switch implemented using AL102A with low-cost SGRAM. AL102A also supports VLAN multiple port aggregation trunks.
10/100
Switch Controller
Buffer Manager
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10/100 High Speed Switch Fabric
Address Control
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10/100
Address Table
10/100 EEPROM Interface
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Figure
System Block Diagram
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AL102A Revision
This document contains proprietary information which shall reproduced, transferred other documents, used other purpose without prior written consent Allayer Communications.
Disclaimer Allayer Communications reserves right make changes, without notice, product(s) described information contained herein order improve design and/or performance. Allayer Communications assumes responsibility liability these products, conveys license title under patent copyright these products, makes representations warranties that these products free from patent copyright infringement unless otherwise specified.
Life Support Applications Allayer Communications products designed life support appliances, systems, devices where malfunctions reasonably expected result personal injury.
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Table Contents
AL102A Overview. Descriptions. Functional Description. Data Reception. 3.1.1 3.1.2 3.1.3 3.1.4 3.2.1 3.2.2 3.2.3 Illegal Frame Length Long Frames False Carrier Events Frame Filtering. Broadcast Storm Control. Frame Transmission Frame Generation.
Frame Forwarding.
Half Duplex Mode Operation Secure Mode Operation Address Learning 3.5.1 Address Aging. VLAN Support. Trunking (Port Aggregation). 3.7.1 3.7.2 3.7.3 Load Balancing Trunk Port Assignment Port Based Trunk Load Balancing Half Duplex Flow Control (Backpressure) Full Duplex Flow Control (802.3x)
Flow Control 3.8.1 3.8.2
3.10 3.11 3.12 3.13
Queue Management Uplink Port. Port Monitoring. Media Independent Interface (MII) Management. Management MDIO Management Master Mode Management Slave Mode.
3.13.1 3.13.2 3.13.3
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AL102A Revision
3.13.4 3.13.5 3.14 3.14.1 3.14.2 3.14.3 3.14.4 3.14.5 3.14.6 3.15
Auto-negotiation Mode Other Options. System Initialization Start Stop Write Cycle Timing. Read Cycle Timing Reprogramming EEPROM Configuration EEPROM
EEPROM Interface
SGRAM Interface
Register Descriptions. Timing Requirements. Electrical Specifications AL102A Mechanical Data Appendix (VLAN Mapping Work Sheet) Appendix (Port Trunk Port Assignment Work Sheet) Appendix (Suggested Memory Components).
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AL102A Overview
AL102A provides eight 10/100 Mbit/s Ethernet ports. Each port supports both Mbit/s data rate. operation mode auto-negotiated PHY. ports full-duplex capable. device also supports VLAN workgroup segment switching applications. AL102A also supports trunking applications. chip provides optional load balancing schemes, explicit dynamic. With trunking, group four full-duplex links together form single Mbit/s link. Data received from interface stored external memory buffer. AL102A utilizes cost effective SGRAM provide 8-Mbit 16-Mbit buffer memory. During transmission, data obtained from buffer memory routed destination port. half-duplex operations, event collision, control will back retransmit accordance IEEE 802.3 specification. AL102A provides flow control methods. half-duplex operations, optional jamming based flow control (also known backpressure) available prevent loss data. With this method flow control, switch will generate signal when receive-buffer full. sending station will transmit until line clear. full-duplex mode, AL102A utilizes IEEE 802.3x flow control mechanism. ports support multiple addresses. switch chip supports addresses internally. These addresses shared among eight ports. initialization configuration switch programmed external EEPROM. unmanaged switch design, required. Field reconfiguration achieved using parallel interface reprogram EEPROM. AL102A supports port based VLAN. VLAN register used configure destination ports multicast broadcast frames. device also provides levels security intrusion protection. Security implemented port basis. AL102A operates only store forward mode. entire frame checked error. Frames with errors automatically filtered will forwarded destination port. Other features include port monitoring broadcast storm throttling.
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Diagram
PBANC_8 CLKin EECLK EEDIO PBCS# PBCAS# PBWE# SYSCLK PBRAS# PBA9_10 PBA0 PBA1 PBA2 PBA3 PBA4 PBA5 PBA6 PBA7 PBA8_9 PBD0 PBD1 PBD2 PBD3 PBD4 PBD5 PBD6 PBD7 PBD16 PBD17 PBD18 PBD19 PBD20 PBD21 PBD22 PBD23 PBD8 PBD9 PBD10 PBD11 PBD12 PBD13 PBD14 PBD15 PBD24 PBD25 PBD26 PBD27 PBD28 PBD29 PBD30 PBD31 PBCLKI
Figure
AL102A Diagram (Top View)
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M2RXD2 M2RXD3 M3CRS M3COL M3TXD3 M3TXD2 M3TXD1 M3TXD0 M3TXEN M3TXCLK M3RXER M3RXCLK M3RXDV M3RXD0 M3RXD1 M3RXD2 M3RXD3 MDIO DEVID1 DEVID0 RESET# TESTMODE EPBYPASS M4CRS M4COL M4TXD3 M4TXD2 M4TXD1 M4TXD0 M4TXEN M4TXCLK M4RXER M4RXCLK M4RXDV M4RXD0 M4RXD1 M4RXD2 M4RXD3 M5CRS M5COL
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MOCRS M0COL M0TXD3 M0TXD2 M0TXD1 M0TXD0 MOTXEN M0TXCLK M0RXER M0RXCLK M0RXDV M0RXD0 M0RXD1 M0RXD2 M0RXD3 M1CRS M1COL M1TXD3 M1TXD2 M1TXD1 M1TXD0 M1TXEN M1TXCLK M1RXER M1RXCLK M1RXDV M1RXD0 M1RXD1 M1RXD2 M1RXD3 M2CRS M2COL M2TXD3 M2TXD2 M2TXD1 M2TXD0 M2TXEN M2TXCLK M2RXER M2RXCLK M2RXDV M2RXD0 M2RXD1
M7RXD3 M7RXD2 M7RXD1 M7RXD0 M7RXDV M7RXCLK M7RXER M7TXCLK M7TXEN M7TXD0 M7TXD1 M7TXD2 M7TXD3 M7COL M7CRS M6RXD3 M6RXD2 M6RXD1 M6RXD0 M6RXDV M6RXCLK M6RXER M6TXCLK M6TXEN M6TXD0 M6TXD1 M6TXD2 M6TXD3 M6COL M6CRS M5RXD3 M5RXD2 M5RXD1 M5RXD0 M5RXDV M5RXCLK M5RXER M5TXCLK M5TXEN M5TXD0 VccM M5TXD1 M5TXD2 M5TXD3
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Descriptions
Table Interface Port
NAME M0TXD3 M0TXD2 M0TXD1 M0TXD0 M0TXEN M0TXCLK M0RXD3 M0RXD2 M0RXD1 M0RXD0 M0RXDV M0RXCLK M0RXER M0CRS M0COL NUMBER DESCRIPTION Transmit Data data transmitted transceiver. Signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. Transmit Enable. Synchronous transmit clock. Transmit Clock Input. Mbit/s Mbit/s. Receive Data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge RX_CLK. Receive Data Valid. Receive Clock. Receive Data Error. Carrier Sense. Collision Detect.
Table Interface Port
NAME M1TXD3 M1TXD2 M1TXD1 M1TXD0 M1TXEN M1TXCLK M1RXD3 M1RXD2 M1RXD1 M1RXD0 M1RXDV NUMBER DESCRIPTION Transmit Data data transmitted transceiver. Signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. Transmit Enable. Synchronous transmit clock. Transmit Clock Input. Mbit/s Mbit/s. Receive Data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge RX_CLK. Receive Data Valid.
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Table Interface Port (Continued)
M1RXCLK M1RXER M1CRS M1COL Receive Clock. Receive Data Error. Carrier Sense. Collision Detect.
Table Interface Port
NAME M2TXD3 M2TXD2 M2TXD1 M2TXD0 M2TXEN M2TXCLK M2RXD3 M2RXD2 M2RXD1 M2RXD0 M2RXDV M2RXCLK M2RXER M2CRS M2COL NUMBER DESCRIPTION Transmit Data data transmitted transceiver. Signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. Transmit Enable. Synchronous transmit clock. Transmit Clock Input. Mbit/s Mbit/s. Receive Data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge RX_CLK. Receive Data Valid. Receive Clock. Receive Data Error. Carrier Sense. Collision Detect.
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Table Interface Port
NAME M3TXD3 M3TXD2 M3TXD1 M3TXD0 M3TXEN M3TXCLK M3RXD3 M3RXD2 M3RXD1 M3RXD0 M3RXDV M3RXCLK M3RXER M3CRS M3COL NUMBER DESCRIPTION Transmit Data data transmitted transceiver. Signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. Transmit Enable. Synchronous transmit clock. Transmit Clock Input. Mbit/s Mbit/s. Receive Data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge RX_CLK. Receive Data Valid. Receive Clock. Receive Data Error. Carrier Sense. Collision Detect.
Table Interface Port
NAME M4TXD3 M4TXD2 M4TXD1 M4TXD0 M4TXEN M4TXCLK M4RXD3 M4RXD2 M4RXD1 M4RXD0 M4RXDV M4RXCLK NUMBER DESCRIPTION Transmit Data data transmitted transceiver. Signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. Transmit Enable. Synchronous transmit clock. Transmit Clock Input. Mbit/s Mbit/s. Receive Data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge RX_CLK. Receive Data Valid. Receive Clock.
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Table Interface Port (Continued)
M4RXER M4CRS M4COL Receive Data Error. Carrier Sense. Collision Detect.
Table Interface Port
NAME M5TXD3 M5TXD2 M5TXD1 M5TXD0 M5TXEN M5TXCLK M5RXD3 M5RXD2 M5RXD1 M5RXD0 M5RXDV M5RXCLK M5RXER M5CRS M5COL NUMBER DESCRIPTION Transmit Data data transmitted transceiver. Signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. Transmit Enable. Synchronous transmit clock. Transmit Clock Input. Mbit/s Mbit/s. Receive Data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge RX_CLK. Receive Data Valid. Receive Clock. Receive Data Error. Carrier Sense. Collision Detect.
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Table Interface Port
NAME M6TXD3 M6TXD2 M6TXD1 M6TXD0 M6TXEN M6TXCLK M6RXD3 M6RXD2 M6RXD1 M6RXD0 M6RXDV M6RXCLK M6RXER M6CRS M6COL NUMBER DESCRIPTION Transmit Data data transmitted transceiver. Signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. Transmit Enable. Synchronous transmit clock. Transmit Clock Input. Mbit/s Mbit/s. Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge RX_CLK. Receive Data Valid. Receive Clock. Receive Data Error. Carrier Sense. Collision Detect.
Table Interface Port
NAME M7TXD3 M7TXD2 M7TXD1 M7TXD0 M7TXEN M7TXCLK M7RXD3 M7RXD2 M7RXD1 M7RXD0 M7RXDV M7RXCLK NUMBER DESCRIPTION Transmit Data data transmitted transceiver. Signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. Transmit Enable. Synchronous transmit clock. Transmit Clock Input. Mbit/s Mbit/s. Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge RX_CLK. Receive Data Valid. Receive Clock.
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Table Interface Port (Continued)
M7RXER M7CRS M7COL Receive Data Error. Carrier Sense. Collision Detect.
Table EEPROM Interface
NAME EEDIO EECLK NUMBER DESCRIPTION EEPROM Serial Data Input Output. EEPROM Serial Clock.
Table Management Interface
NAME MDIO NUMBER DESCRIPTION Management Clock. Management Data Input Output.
Table Power Interface
NAME NUMBER 100, 102, 104, 118, 120, 122, 144, 146, 165, 167, 168, 187, 189, 205, 208, 217, 232, 108, 121, 124, 126, 147, 149, 151, 155, 169, 171, 173, 177, 190, 202, 224, 239, Ground DESCRIPTION
(3.3V)
3.3V Supply Voltage.
VccM
Supply Voltage Interface. VccM interface) VccM 3.3V (3.3V interface)
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Table SGRAM Interface
NAME PBD31 PBD30 PBD29 PBD28 PBD27 PBD26 PBD25 PBD24 PBD23 PBD22 PBD21 PBD20 PBD19 PBD18 PBD17 PBD16 PBD15 PBD14 PBD13 PBD12 PBD11 PBD10 PBD9 PBD8 PBD7 PBD6 PBD5 PBD4 PBD3 PBD2 PBD1 PBD0 PBA9_10 PBA8_9 PBANC_8 NUMBER DESCRIPTION
SGRAM Data Bus.
SGRAM Address. Mbit/s SGRAM, this PBA10 Mbit/s SGRAM this SGRAM Address. Mbit/s SGRAM, this PBA9 Mbit/s SGRAM this SGRAM Address. Mbit/s SGRAM, this PBA8 unconnected when connected Mbit/s SGRAM.
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Table SGRAM Interface (Continued)
PBA7 PBA6 PBA5 PBA4 PBA3 PBA2 PBA1 PBA0 PBCS# PBRAS# PBCAS# PBWE# PBCLKI SGRAM Address line PBA0-PBA8 sampled during ACTIVE command (row address) read/write command (column address with PBA8 defining auto precharge).
Chip Select. Enables disables command decoder SGRAM. SGRAM Address Strobe. SGRAM Column Address Strobe. Write Enable. System Clock Output drive SGRAM.
Table Miscellaneous Pins
NAME DEVID0 DEVID1 RESET# TESTMODE EPBYPASS NUMBER DESCRIPTION Device Number. AL102A, both pins should connected ground. Reset Test Mode Pin. This should grounded normal operation. This bypasses EEPROM setup. This should tied ground. This should tied ground. System Clock. Connect.
CLKIN SYSCLK
127, 128, 129, 130, 191, 192, 193, 194,
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AL102A Interface Block Diagram
MXTXD3 MXTXD2 MXTXD1 MXTXD0 MXTXEN MXTXCLK MXRXD3 MXRXD2 MXRXD1 MXRXD0 MXRXDV MXRXCLK MXRXER MXCRS MXCOL PBD[n] PBA[n] PBBA PBCS PBRAS PBCAS PBWE PBDSF PBDQM PBCLK
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Switch Controller
Address Control
Address Table Buffer Manager Management Management Information EEPROM Interface EEDIO EECLK MDIO
RESET DEVID1 DEVID0
Figure
Interface Block Diagram
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Functional Description
Data Reception
port will into receive-state when RX_DV interface asserted. (Media Independent Interface) presents received data four-bit nibbles that synchronous receive clock Mbit/s Mbit/s). AL102A will then attempt detect occurrence (Start Frame Delimiter) pattern "10101011." preamble data prior discarded. Once detected from interface, frame data forwarded stored buffer switch. 3.1.1 Illegal Frame Length During receiving process, AL102A will monitor length received frame. Legal Ethernet frames should have length less than bytes more than 1536 bytes. frames with illegal frame length discarded. 3.1.2 Long Frames AL102A handle frame size 1536 bytes. frames longer than 1536 bytes will discarded. port continues receive data after 1536th byte, port's data will filtered. port half-duplex mode, port will longer able transmit receive data during long frame reception. 3.1.3 False Carrier Events (Carrier Sense) signal interface asserted receive RX_DV (Receive Data Valid) signal asserted within 16BT (Bit Period), port considered have false carrier event. false carrier event recorded counter. 3.1.4 Frame Filtering AL102A will make filtering forwarding decisions each frame received based frame routing table, VLAN Mapping, port state, system configuration. Under following conditions, received frames filtered: AL102A will check received frames errors such symbol error, error, short event, runt, long event, etc. Frames with kind error will forwarded their destination port. frame heading source port will filtered. Frames heading disabled receiving port will filtered. input buffer port full, incoming frame will discarded. recommended that flow control used prevent loss data. flow control option enabled, this event will occur. remote station will transmit frame when input buffer becomes available. frame security violation security option enabled receiving port.
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Frame Forwarding
After frame received, both source address (SA) destination address (DA) retrieved. used update port's address table used determine frames destination port. Address Lookup Engine will attempt match destination address with addresses stored address table. there match found, link between source port destination port then established. first destination address "0," frame regarded unicast frame. destination address passed Address Lookup Engine, which returns matched destination port number identify which port frame should forwarded destination port within same VLAN receiving port, frame will forwarded. destination port does belong VLANs specified receiving ports, frame will discarded. event will recorded VLAN boundary violation. There ways that AL102A handles frames with unknown destinations. forwarding decision controlled Flood Control option (System Configuration Register 00). Flood Control disabled, frame will forwarded ports (except receiving port) within same VLANs receiving port. Flood Control option enabled, AL102A will forward frame only uplink port specified receiving port. Note: AL102A defines port either single port trunk. port monitoring function enabled, frame forwarding decision also subject port monitoring configurations. first destination address "1," frame will handled multicast broadcast frame. AL102A does differentiate multicast frames from broadcast frames except reserved bridge management group address, specified table IEEE 802.1d standard. destination ports broadcast frame ports within same VLAN except source port itself. 3.2.1 Broadcast Storm Control unique features provided AL102A Broadcast Storm Control. This option allows user limit number broadcast frames into switch. This option implemented port basis. threshold number broadcast frames programmed System Register (register 01). When Storm Control enabled number cumulated non-unicast frames over programmed threshold, broadcast frame discarded. Storm Control disabled, number non-unicast frames received over programmed threshold, AL102A will forward frame ports (except receiving port) specified within VLANs receiving port. Broadcast-Storm-drop (BConly_SC) enabled System Register (register 02), AL102A will only drop broadcast frames multicast frames.
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3.2.2 Frame Transmission AL102A transmits frames accordance IEEE 802.3 standards. AL102A will send frames with guaranteed minimum (Inter Packet/Frame Gap) 96BT even received frames have less than minimum requirement. AL102A also supports transmission frames with 64BT (optional). This option selected System Register III, (Bit Register 02). 3.2.3 Frame Generation During transmit process frame data read from memory buffer forwarded destination port's device di-bits. Seven bytes preamble signal (10101010) will generated first before (10101011). Frame data sent after along with four-bytes end.
Half Duplex Mode Operation
half-duplex operation, logic will abort transmit-process collision detected through assertion collision (Col) signal MII. Re-transmission frame scheduled accordance IEEE 802.3's truncated binary exponential back algorithm. transmit process encountered consecutive collisions, excessive collision error reported AL102A will re-transmit frame unless retry-on-excessive-collision (REC) option enabled. When enabled, number collisions reset zero transmission started soon bit-time inter-packet passed after last collision. collision detected after 512BT transmission, late collision error will reported frame will still re-transmitted after proper back time. AL102A also provides option aggressive back Port Configuration Register 01.3 (SuperMAC). This option allows back only three slots. This will create more aggressive channel capture behavior than standard IEEE back algorithm.
Secure Mode Operation
AL102A provides security support port basis. Whenever secure mode enabled, port will stop learning addresses. address table each port will remain unchanged. this mode operation, address lookup table will freeze additional address will learned. AL102A provides levels security protection. most severe intrusion protection disabling port intrusion experienced. security management (SecMgmt register will disable port frame with unlearned source address (SA) received from secured port (security violation). Once port disabled, only enabled network management. Security management global option. alternative enable security local port level without security management. When AL102A configured this way, device will only discard frames that have security violations, which prevents intruders from accessing network.
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Address Learning
Table Lookup Engine provides switching information required route data frames. address look table set-up through auto address learning (dynamic) manual entry (static). static addresses assigned address table EEPROM. static address entries will aged updated AL102A. After frame received AL102A, embedded (SA) destination address (DA) retrieved. source address retrieved from received frame automatically stored buffer. AL102A will then check error security violations, perform search. there error security violation, AL102A will store source address address lookup table. been previously stored another port's table, AL102A will delete from previously stored location. Individual Address 48-bit unique address programmed learned. will masked, i.e. multicast AL102A provides on-chip Address-to-PortID/TrunkID table frame destination look-up operations. AL102A address table contains both static addresses input EEPROM dynamically learned address. learns individual addresses from frame received with errors from local ports. received frames that contain source address learned another port's address table, that hasn't been aged out, perform following based switches; security option selected port, AL102A considers this security violation; port non-protected port, AL102A will delete from previous port's address table update current port's address table. However, static address entry, address will updated. 3.5.1 Address Aging port's address register cleared power-up, hardware reset. aging option enabled, dynamically learned will cleared refreshed within programmed time.
VLAN Support
Each port AL102A assigned multiple VLANs. Frames from source port will only forwarded destination ports within same VLAN domain. broadcast/multicast frame will forwarded ports within VLAN(s) except source port itself. unicast frame will forwarded destination port only destination port same VLAN source port. Otherwise, frame will treated frame with unknown destination port belongs another VLAN, frame will discarded event will recorded VLAN boundary violation. Each port assigned with dedicated uplink port. Unicast frames with unknown destination addresses will forwarded uplink port source port. uplink port either single port trunk. AL102A provides VLAN register ports (register mapping eight-ports (eight-bits). Each register contains eight-bit indicate VLAN group port.
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VLAN registers hold broadcast destination mask each source port. value will indicate broadcast frames will routed from source port specified port. Note that source port must within source port VLAN, because broadcast frames routed source port. setting VLAN trunking, please following section trunking detail. VLAN Setup Example VLAN setup worksheet provided Appendix Simply marking ports wish send broadcast frame complete VLAN easily. example, let's assume want VLAN groups 8-port switch: Group consists Group consists completed VLAN maps shown below. other bits (15~8) shown register, should "0."
Table VLAN 8-Port Switch
PORT 5/REG. PORT 6/REG. PORT 7/REG. PORT 0/REG. PORT 1/REG. PORT 2/REG. PORT 3/REG. PORT 4/REG.
PORT
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Trunking (Port Aggregation)
AL102A supports trunking/port aggregation. Port aggregation trunking essentially method treat multiple physical links single logical link. benefit trunking ability group multiple lower speed links into higher speed link. example, four full-duplex Mbit/s links used single 800-Mbps link. This very useful switch switch, switch server, switch router applications. AL102A considers trunk single port entity regardless trunk composition. four ports grouped together single trunk link. grouping ports trunk must from four ports bottom four ports device, i.e. port total eight trunks supported chip sets. multiple link trunk, links within trunk should have balanced amount traffic order achieve maximum efficiency. requirements transmission that frames being transmitted must order. Therefore, some sort load balancing among links trunk must deployed. AL102A offers methods load balancing which selected System Configuration Register (register 00). 3.7.1 Load Balancing load-balancing methods that AL102A uses support trunking port based address based. Port based load balancing method explicit port assignment scheme. requires each individual port assigned specific link (trunk port) trunk. port assigned, frame might routed trunk randomly which cause frames order. port based load balancing trunk assigned 4-port trunk. During transmission frame, will routed from source port assigned trunk port. When frame received from trunk ports, will routed destination port within VLAN. essence, AL102A treats trunk single port within same VLAN. ports traffic evenly distributed among trunk ports, load balancing achieved aggregate bandwidth trunk high Mbit/s (full-duplex). alternative address based load balancing. When AL102A receives frame with trunk destination, will automatically forward frame port trunk based source address. address load balancing decision based proprietary algorithm. algorithm assumes trunk four port trunk. Therefore, address based load balancing used, trunk must consist four ports. based load balancing three port trunks could result loss frames.
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3.7.2 Trunk Port Assignment maximum number trunks Allayer's architecture eight. Port Configuration Registers provides ability designate port member trunk. trunk consist four trunk ports. trunk group must consist either four ports bottom four ports. example, trunk consist either port port Each trunk port's number sequence corresponding order port devices. example, port (See Figure
AL102A
Ports
Trunk Port
Trunk Port
Figure
Trunk Port Numbering
3.7.3 Port Based Trunk Load Balancing port-based load balancing, trunk port must assigned each port defined trunks. port assignment done programming Port Trunk Port registers 34). port assignment worksheet provided back data sheet. recommended that ports evenly distributed among trunk ports prevent overloading single trunk port. Port Based Trunk Load Balancing Example example ports two-port trunk. desired trunk ports Therefore, port configuration register bits 15.9, 16.9, 17.9 want assign port trunk port port trunk port port trunk port Therefore, port trunk port register bits follows. 08.2= 08.3 09.2= 09.3 10.2= 10.3 11.2= 11.3 12.2= 12.3 trunk ports, trunk ports should assigned with their port number port trunk port register. port trunk port bits.
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13.2= 13.3 14.2= 14.3 15.2= 15.3 Assigning VLAN. VLAN assigned shown. bits bits 21.1 21.0 because port assigned port other ports similarly.
Table VLAN Mapping Port Based Load Balancing Trunk
PORT 0/REG. PORT 7/REG. PORT 1/REG. PORT 2/REG. PORT 3/REG. PORT 4/REG. PORT 5/REG. PORT 6/REG.
PORT
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Flow Control
AL102A operate different modes, half- full-duplex. Each port operate either full- half-duplex configured have flow control enabled flow control independently port basis. 3.8.1 Half Duplex Flow Control (Backpressure) half-duplex flow control option elected, backpressure will used flow control. Whenever occupancy receiving frame buffer port full, port will start sending signal through port. remote station after sensing signal will defer transmission. Backpressure flow control applied ensure that there dropped frame. AL102A supports types backpressure, collision based carrier based. Carrier based backpressure generated AL102A, when switch port's frame buffer full. AL102A will cease line, when port buffer space available frame reception. jamming signal programmed either 64BT 96BT. Collision Based backpressure generated AL102A, only when switch port receives frame. AL102A will cease line, when line idle. carrier based backpressure several advantages over collision based backpressure. Collision based backpressure cause late collisions. After consecutive collisions, could drop frames. AL102A option drop frame after collisions. However, terminal still drop frames. Therefore, recommend carrier based back pressure preferred method halfduplex flow control. this mode operation, also recommend that signal should 64BT. This because 96BT, terminal might still able transmit frame cause collision. excessive collision could cause frames dropped. AL102A also supports collision-based backpressure customers that prefer collision based backpressure. 3.8.2 Full Duplex Flow Control (802.3x) full-duplex mode, AL102A will transmit receive frame accordance 802.3x standards. transmission channel receiving channel operate independently. incoming direction, whenever occupancy receiving frame buffer port full, port will send PAUSE frame with delay value maximum. PAUSE frame will deter incoming frame from flowing into port. After occupancy receiving frame buffer reduced below FlowControlOff threshold, port will then send PAUSE frame with delay value zero, resume receiving incoming frame flow. outgoing direction, whenever incoming PAUSE frame with non-zero delay value received through port, port will stop next frame transmission after ongoing frame transmission finished, start pause timer. will resume frame transmission either after pause timer expired when PAUSE frame with zero delay value received.
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When 802.3x flow control option elected, device will program appropriate autonegotiation capability field. When AL102A used full-duplex mode, recommended that flow control should turned This prevent buffer from overflow loss frames. connected device 802.3x capability, then link recommended half-duplex.
Queue Management
Each port AL102A individual transmission receive queues. frames come into AL102A stored into shared memory buffer, lined transmission queues corresponding destination port. Each port AL102A input frame queue, dedicated queue buffer locally generated management event messages. Each output port maintains output frame queue for, dedicated multicast queue outgoing multicast frame parking. transmit frame from sources, local from another device ring. output queue, source selected multicast queue, device will channel copy frame head multicast queue output queue transmission. output queue, source selected local input queue, device will channel from local DRAM buffer output queue upon requested DRAM bandwidth available. output queue, source selected from another device ring, device will send message, that device, trying channel through ring from source input queue that device local output queue. multicast queue, source selected local input queue, device will channel from local DRAM buffer multicast queue upon requested DRAM bandwidth available. multicast queue, source selected from another device ring, device will send message that device, trying channel through ring from source input queue that device local multicast queue.
3.10 Uplink Port
uplink port provides means connect switch with repeater hub, workgroup switch, router, type interconnecting device compliance with IEEE 802.3 standards. flood control enabled, AL102A will send frames with unmatched multicast/ broadcast frames uplink port. very important that each port assigned uplink port Port Configuration Register to1C), data frames might lost. uplink port should configured within same VLAN source port. uplink port member VLANs, broadcast multicast frames will forwarded designated uplink port. Multiple VLANs share same uplink port. AL102A will direct following frames uplink port: Frames with unicast destination address that doesn't match with address stored switch;
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Frames with broadcast/multicast destination address uplink port same VLAN.
Note: When configuring uplink port, uplink port should designate itself uplink port. some applications, might desirable configure port port without address learning capability. When port configured such, that port becomes "dumping" port frames with unknown uplink port individual port trunk. recommended that uplink port learning disabled state (Port Configuration Register conserve address table space.
3.11 Port Monitoring
AL102A supports port monitoring. This feature provides complete network monitoring capability Mbit/s. copy egress (TX) data ingress (RX) data monitored port sent their respective snooping ports. monitored port selected register AL102A allows transmit receive data monitored different snooping ports. snooping ports also selected register Summary Programmable Register Port Monitoring Register (register this register selects target monitored port snooping port. five-bit Port_ID designates port. format Port_ID [00].[Port_ID]. [00] device number [Port_ID] port number.
3.12 Media Independent Interface (MII)
each port AL102A connected through standard interface. receiving frames, received data (RXD[3:0]) sampled rising edge receive clock (RX_CLK). Assertion receive data valid (RX_DV) signal will cause look start SFD. transmission, transmit data enable (TX_EN) signal asserted when first preamble nibble sent transmit data (TXD[3:0]) lines. transmit data clocked rising edge transmit clock (TX_CLK). Prior transaction, AL102A will output 32-bits preamble signal then after preamble, "01" signal used indicate start frame.
3.13 Management
AL102A supports transceiver management through serial MDIO signal lines. device provides modes management, master slave mode. master mode operation, AL102A controls operation modes link, slave mode controls operating mode.
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3.13.1 Management MDIO write operation, device will send "01" signal write operation. Following "01" write signal will five-bit address device five-bit register address. "10" turn around signal then used avoid contention during read transaction. After turn around, 16-bit data will written into register. After completion write transaction, line will high impedance state. read operation, AL102A will output "10" indicate read operation after start frame indicator. Following "10" read signal will five-bit address device five-bit register address. Then, AL102A will cease driving MDIO line, wait time. During this time, MDIO should high impedance state. device will then synchronize with next driven device, continue read data from register. detail timing requirement management signals described section "Timing Requirement." MDIO port disabled through port configuration register. This allows engineers 100Base-TX transceiver without auto-negotiation capability interconnect. this mode operation, communication with AL102A. Therefore, AL102A will assert link status soon initialization completed assumes connected operating specified operating duplex mode speed. 3.13.2 Management Master Mode master mode, AL102A will continuously poll status devices through serial management interface. device will also configure capability fields ensure proper operation link. configuration link automatic. link capability programmed AL102A through port configuration register. AL102A reads from standard IEEE registers determine auto-negotiated operating speed mode. there need manually operation mode because flow control cabling issues AL102A port operation mode through MDIO interface (see EEPROM section programming AL102A). 3.13.3 Management Slave Mode slave mode, controls programming operating mode. AL102A will continuously poll status devices through serial management interface determine operation mode link. This mode management very useful unmanaged switch. operating mode link changed programming mode through jumper. AL102A also supports 100Base-TX transceivers without MDIO interface interface. When MDIO disabled, AL102A will operate operation mode specified Port Configuration Register (register 1C). 3.13.4 Auto-negotiation Mode AL102A also turn auto-negotiation capability PHY. When auto-negotiation turned off, AL102A slave mode transceiver will determine link's operating mode.
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3.13.5 Other Options Some Legacy Fast Ethernet devices other cost devices have auto-negotiation capability. those cases when transceiver will able perform auto-negotiation, switch transceiver will typically parallel detection update information transceiver's register. Unfortunately, such register addresses vendor specific. AL102A provides register (register specify register address AL102A read. AL102A will read from that register configure port operation accordingly. Register also provides some additional flexibility's some PHYs market. general, system designer should devices port port port etc. Certain PHYs utilize address 00000 broadcast address. register allows AL102A start with address 10000. This provision allows engineers work around PHY's that have problems handling address 00000. Quad PHYs have two-port ordering chip pinout, both clockwise counter clockwise. Register programs AL102A port order either direction. This provision enables engineers easily implement designs with PHY. There also slow MDIO clock KHz) available that capable handling high speed MDIO clock. some reason, transceiver connected device that device fails auto-negotiate, AL102A will default data rate duplex mode default setting port configuration register.
3.14 EEPROM Interface
AL102A provides three functions with EEPROM interface: system initialization, obtaining system status, reconfiguring system real time. AL102A uses 24C02 serial EEPROM device (2048 bits organized bits 3.14.1 System Initialization EEPROM interface provided that manufacturer provide pre-configured system their customers which allows customers change reconfigure their system retain their preferences. EEPROM contains configuration initialization information, which will accessed power reset.
Device Type Identifier Device Address
reset held low, AL102A's EEPROM interface will into high impedance state. This feature very useful reprogramming EEPROM during installation reconfiguration. EEPROM reprogrammed external parallel port. reprogramming using parallel port, signal used hold RESET low. EEPROM interface will then
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high-impedance state. external device then program EEPROM through EEDIO EECLK pins. EEPROM address should 000. 3.14.2 Start Stop write cycle started start ended stop bit. start transition from high EEDIO when high. Figure operation terminates when EEDIO goes from high when high. Following start condition, writing device must output address EEPROM. most significant four EEPROM address device type identifier which address 1010. EEPROM address should same Device with (EEPROM) grounded. example, EEPROM device address device address 001.
EECLK
EEDIO
Data Address Valid
START
Data Change
STOP
Figure
EEPROM Start Stop
3.14.3 Write Cycle Timing EECLK output from AL102A while EEDIO bi-directional signal. When accessing EEPROM, reset held initialization AL102A must finished before writing operation begin. typical write operation shown Figure
Device Address
Start
Stop
EEDIO
Word Address
Data
Acknowledge
Acknowledge
Acknowledge
Figure
EEPROM Random Write Cycle
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3.14.4 Read Cycle Timing Read operations initiated same manner write operations, with exception that EEPROM address "1."
Start Device Address Start Device Address
EEDIO
Word Address
Data
Acknowledge
Acknowledge
Acknowledge
Figure
EEPROM Random Read Cycle
3.14.5 Reprogramming EEPROM Configuration There ways that system reconfigured. Figure shows application using parallel interface reprogram EEPROM. this application, parallel port holds reset pins low, which forces EEDIO pins high impedance. Once pins high impedance, EEPROM programmed parallel port. Once parallel port releases reset pins, devices will start download EEPROM data reconfigure devices. alternate reconfiguring system directly change register settings AL102A. After initialization, EEPROM interface virtual EEPROM. order this method work, EEPROM's device address must 000, while AL102A's address will 100. customer program AL102A EEPROM. read write timing same EEPROM. Because read well write AL102A, registers status read from AL102A. This will serve very useful tool diagnostic unmanaged switch.
Reset
AL102A
EECLK EEDIO
Parallel Port EEPROM
Figure
EEPROM Parallel Port
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3.14.6 EEPROM Table shows EEPROM address cross-referenced register/bit AL102A. Addresses through configuring device. They downloaded AL102A after reset power Since AL102A registers 16-bit wide, takes EEPROM addresses each AL102A register. Even numbered EEPROM addresses corresponds upper byte AL102A registers while numbered EEPROM addresses corresponds lower byte AL102A registers. Note: specific bits register reference "X.Y" notation, where register number number. Address should programmed 0000 0001 0001 0100. address indicates last address entry. static address used switch, address should programmed. Addresses used programming static address entry. following format example Static Entry Address 70-77.
Table Static Address Entry Format EEPROM
EEPROM ADDRESS
Reserved (Must zero) Reserved Port YXXXXX Trunk YXXYYY
Address [47:40] Address [39:32] Address [31:24] Address [23:16] Address [15:8] Address [7:0]
represents: then [port_ID] represents five-bit individual port number then [port_ID] represents trunk number (0-1) then this represents port [port_ID] don't care.
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Table AL102A EEPROM Mapping
EEPROM PHYSICAL ADDRESS 02-03 04-05 06-07 08-09 0A-0B 0C-0D 0E-0F 10-11 12-13 14-15 16-17 18-19 1A-1B 1C-1D 1E-1F 20-21 22-23 24-25 26-27 28-29 2A-2B 2C-2D 2E-2F 30-31 32-33 DESCRIPTION System Configuration [15:8] System Configuration [7:0] System Configuration System Configuration 0000 0001 0001 0100 Reserved Vendor Specific Snooping Port Configuration Monitored Host [47:32] Monitored Host [31:16] Monitored Host [15:0] Monitored Host [47:32] Monitored Host [31:16] Monitored Host [15:0] Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration AL102A REGISTER/BIT 00.15 00.8 00.7 00.0 01.15 01.0 02.15 02.0 03.15 03.0 04.15 04.0 05.15 05.0 06.15 06.0 07.15 07.0 08.15 08.0 09.15 09.0 0A.15 0A.0 0B.15 0B.0 0C.15 0C.0 0D.15 0D.0 0E.15 0E.0 0F.15 0F.0 10.15 10.0 11.15 11.0 12.15 12.0 13.15 13.0 14.15 14.0 15.15 15.0 16.15 16.0 17.15 17.0 18.15 18.0 19.15 19.0
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Table AL102A EEPROM Mapping (Continued)
34-35 36-37 38-39 3A-3B 3C-3D 3E-3F 40-41 42-43 44-45 46-47 48-49 4A-4B 4C-4D 4E-4F 50-51 52-53 54-55 56-57 58-59 5A-5B 5C-5D 5E-5F 60-61 62-63 64-65 66-67 68-69 6A-6B 6C-6D Port Configuration Port Configuration Port Configuration Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Reserved Checksum Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Reserved 2D.15 2D.0 2E.15 2E.0 2F.15 2F.0 30.15 30.0 31.15 31.0 32.15 32.0 33.15 33.0 34.15 34.0 1A.15 1A.0 1B.15 1B.0 1C.15 1C.0 1D.15 1D.0 1E.15 1E.0 1F.15 1F.0 20.15 20.0 21.15 21.0 22.15 22.0 23.15 23.0 24.15 24.0 25.15 25.0 26.15 26.0 27.15 27.0 28.15 28.0 29.15 29.0 2A.15 2A.0 2B.15 2B.0 2C.15 2C.0
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Table AL102A EEPROM Mapping (Continued)
70-71 72-73 74-75 76-77 78-7f 80-87 88-8f 90-97 98-9f A0-A7 A8-AF B0-B7 B8-BF C0-C7 C8-CF D0-D7 D8-DF E0-E7 E8-EF F0-F7 F8-FF Last Entry Address Static Entry (Port Number) Static Entry (MAC [47:32]) Static Entry (MAC [31:16]) Static Entry (MAC [15:0]) Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry
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3.15 SGRAM Interface
ports AL102A work Store-And-Forward mode that ports support both Mbit/s Mbit/s data speed. AL102A utilizes central memory buffers pool, which shared ports within same device. After frame received, passed across SGRAM interface stored buffer. During transmit, frame retrieved from buffer pool forwarded destination port. AL102A designed 8-Mbit SGRAM 16-Mbit SGRAM cost performance. SGRAM accessed page burst access mode very high speed access. This burst mode repeatedly access same column. burst mode reaches column address, then wraps around first column address (=0) continues count until interrupted news read/write, pre-charge, burst stop command. AL102A will initialize SGRAM automatically. pre-charges banks inserts auto- refresh commands. will also program mode registers AL102A read write operations. SGRAM essentially SDRAM. Dynamic memories must refreshed periodically prevent data loss. SGRAM uses refresh address counters refresh automatically. SGRAM Autorefresh command generates pre-charge command internally SGRAM. AL102A will insert auto-refresh command once every During transmit, frame retrieved from buffer pool forwarded destination port.
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Register Descriptions
Table Register Table Summary
REGISTER REGISTER DESCRIPTION System Configuration System Configuration System Configuration Reserved Reserved Vendor Specific Status Port Monitoring Configuration Monitored Source Host [47:32] Monitored Source Host [31:16] Monitored Source Host [15:0] Monitored Destination Host [47:32] Monitored Destination Host [31:16] Monitored Destination Host [15:0] Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration
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Table Register Table Summary (Continued)
Port Configuration Port Configuration Port VLAN Reserved Port VLAN Reserved Port VLAN Reserved Port VLAN Reserved Port VLAN Reserved Port VLAN Reserved Port VLAN Reserved Port VLAN Reserved Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Reserved Reserved Reserved Reserved
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Table Register Table Summary (Continued)
42~47 System Status Register Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Reserved
System Configuration Register (Register registers global system configuration registers. option selected this register affect overall system operation.
Table System Configuration Register (Register
NAME Reserved FloodCtl zero. Flooding Control. Control forwarding unicast frames with unknown destinations received from non-uplink ports. Disable. Frames received with unknown unicast destination address will forwarded ports (excluding receiving port) within VLANs specified receiving port. Enable. Frames received with unknown unicast destination address will forwarded uplink port specified receiving port. Security Enforcement. Security Off. security violation secured port will change port state. Security security violation secured port will change port into DISABLE state. Switch Table Entry Aging Control. Disable. table aging process will stopped. Enable. table aging process will running every dynamically learned table entries. Table Convergence Control. zero. DESCRIPTION
SecMgmt
AgeEn
TCNVG
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Table System Configuration Register (Register (Continued)
Reserved PInMon zero. Port Incoming Frame Flow Monitoring Enable Cable. Disable Enable Port Outgoing Frame Flow Monitoring Enable Cable. Disable Enable zero. Layer Trunk Loading Method. Port based loading. Trunking decisions will based trunk port assignment registers. address based loading. Trunking decisions will based source port addresses. Frame Time Enable. Device will timeout frames based MaxDelay. Device will timeout frames. Reserved factory use. Bits should
POutMon
Reserved L2Trunk
TimeoutEN
Reserved
Table System Configuration Register (Register
15~8 NAME MaxAge MaxDelay DESCRIPTION Maximum dynamically learned entries. 0000 0000: sec. 1111 1111: sec. Maximum frame transition delay through switch. second seconds seconds seconds Maximum number broadcast frames that accumulated each input frame buffer. frames frames frames frames Disable. Device will perform IEEE standard exponential back algorithm when collision occurs. Enable. When collisions occur, AL102A will back slots. Retry Excessive Collision. Normal collision handling. Retry transmission after consecutive collisions.
MaxStorm
SuperMAC
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Table System Configuration Register (Register
L2TbitSel Select bits position address trunk assignment. Source Address [1:0] Source Address [3:2] Source Address [5:4] Source Address [7:6]
Table System Configuration Register (Register
15~12 NAME Reserved RegPg SlowAge BpIPG84 Reserved (Must First page. Second page. Normal aging. Slow down aging. Backpressure Select Enable. 96BT. 64BT. Control. 96BT. 64BT. Reserved (Must SGRAM Select. Mbit SGRAM. Mbit SGRAM. Back Pressure Control. Carrier based. Collision based. Reserved (Must Flow control multicast. Flow control broadcast. DESCRIPTION
IPG64
Reserved SG16M
BPCOL
Reserved FlowCtrlBC
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Reserved Register (Register This register reserved Allayer's use. bits should 0000 0001 0001 0100. Reserved Register (Register This register reserved Allayer's use. bits should 0000 0000 0000 1000. Vendor Specific Register (Register This register used program vendor specific options. also used programming Vendor Specific register location location operation status.
Table Vendor Specific Register (Register
12~8 NAME PHYAD MCIkSpd PortOrder PHYOpReg PHYSpBit PHYDxModeBit DESCRIPTION Setting this will program MDIO address addresses Setting this will reduce MDIO clock speed HKz. Setting this will reverse ID/port number switch. PHY's Operation Status Register Number. PHY's Data Rate Status Register Number. PHY's Operating Duplex Mode Status Register Number.
Port Monitoring Configuration Register (Register This register configures port monitoring. sets monitored port snooping ports.
Table Port Monitoring Configuration Register (Register
14~10 NAME Reserved MdPID MgIPID MgOPID should Monitored Port Snooping Port Incoming Frame Flow. Snooping Port Outgoing Frame Flow. DESCRIPTION
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RMON Source Destination Registers (Registers These registers used RMON manager frame counting. RMON manager counts frames (destination) from (source) these addresses stored register. 48-bit address programmed three separate registers. Source address stored registers destination address register
Table RMON Source Destination Registers (Registers
REGISTER 15~0 15~0 15~0 NAME SRCMAC [47:32] SRCMAC [31:16] SRCMAC [15:0] DESCRIPTION Monitored Source Host Address Monitored Source Host Address Monitored Source Host Address
Table RMON Source Destination Registers (Registers
REGISTER 15~0 15~0 15~0 NAME DSTMAC [47:32] DSTMAC [31:16] DSTMAC [15:0] DESCRIPTION Monitored Destination Host Address Monitored Destination Host Address Monitored Destination Host Address
Port Configuration Registers (Registers Registers local port configuration. There port configurations port. port configuration Port uses register Port register etc. Port Configuration Register Uplink this six-bit link assign uplink port local port. uplink port three types; single port, trunk, port. uplink single port, format port [0][Dev_ID][Port_ID]. uplink trunk, then bits should read [100][trunk number]. trunk number numbered [Dev_ID][Trunk_ID]. local port uplink port, uplink should port frame with unlearned will then filtered.
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Table Port Configuration Register
15~10 NAME UpLinkID DESCRIPTION Uplink associated with port. 0XXYYY: Port with device port 100XXN: Trunk with device trunk 111XXX: port. Others: Reserved. Trunk Member Port. Individual port. Member trunk port. should zero. Broadcast Storm Control Enable. Storm control disable. broadcast frame will throttled. Storm control enable. accumulated number broadcast frames input buffer port over threshold specified system configuration register, incoming broadcast frames will discarded until number been reduced below threshold. Intrusion Protection. Provides security control frames received from non-uplink ports. Security Off. forwarding decision made about frames received from port will involve source address checking. Security frames received from port with unknown source address with source address learned previously from another port will discarded. Port VLAN Membership. zero. Learning Disable. Source address from this port will learned. Source address from this port will learned. Port State Control. Disable. incoming frames from will discarded; outgoing frames will masked from path PHY. Blocking-N-Listening. incoming frames except incoming BPDUs from will discarded; outgoing frames except outgoing BPDUs will masked from path PHY. Learning. incoming frames from will learned about their source information; incoming frames except incoming BPDUs from will discarded after being learned; outgoing frames except outgoing BPDUs will masked from path PHY. Forwarding. incoming frames from will learned from their source information; incoming frames will forwarded based switch routing decision; outgoing frames will transmitted PHY. Reserved (Must
Tmember
Reserved StormCTL
Security
CPUOn LrnDis
PortST
Reserved
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Table Port Configuration Register
15~12 NAME Reserved FlowCtrlFdEn FlowCtrlHdEn MDIOCfg [3:0] Reserved Flow Control Full Duplex Enable. Flow Control Half Duplex Enable. MDIO Configuration. 0001: Master mode management. 0010: Slave mode management. 0111: Force mode. MDIO Disable. MDIO enabled. MIDO disabled. This relevant when MDIO enabled. When MDIO disabled, this forces port into link link down state. Link Down. Link Full Duplex Mode. Half Duplex Mode. Full Duplex Mode. Half Duplex Mode. DESCRIPTION
MDIODis
LinkUp
PrtMode100F PrtMode100H PrtMode PrtMode
Port VLAN Registers (Registers These registers provide VLAN each port. VLAN worksheet provided Appendix
Table Port VLAN Registers (Registers
REGISTER Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 NAME Dev0Map DESCRIPTION Port VLAN corresponding port7~port0 device with Dev_ID Non-member port. Member port.
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Port Trunk Port Assignment Registers (Registers Port Trunk Port assignment register assigns port trunk port-based load balancing trunking. Please example trunking section. port trunk port work sheet provided Appendix
Table Port Trunk Port Assignment Registers (Registers
15~4 NAME Reserved Trunk DESCRIPTION Reserved (Must Trunk Port Trunk Port Port Port Port Trunk Port Trunk Port Port Port Port
Trunk
Table System Status Register (Register
10~7 NAME Reserved CheckSumEr SGRAMinit SRAMinit REGinit Traffic Counter Reserved Chip 0000: AL102A DESCRIPTION Reserved (Must EEPROM Checksum Error. SGRAM Initialization Done. SRAM Initialization Done. Register Initialization Done. Traffic Counter.
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Port Operation Status Registers (Register Registers status indication port basis. These read only register. Port port status register Port 1~3E, Port 2~3F, Port3~40, Port 4~41.
Table Port Operation Status Registers (Register
NAME LinkFail Port Link Status. Normal Fail Port Status. Normal Error Port Security Violation. Normal Violation Flow Control. port mode ([1:0]) 2'b01 2'b11: Pause disable. Pause enable. port mode ([1:0]) 2'b00 2'b10: Back pressure based CRS. Back pressure based collision. Port Broadcast Storm Status. Normal Stormed Port Input Buffer Full Status. Normal Input buffer full experienced. Table Entry Unavailability Learning. Normal Unavailability experienced. Port Jabber Status. Normal Jabber experienced. Port Late Collision Status. Normal Late collision experienced. Port Transmit Pause Status. transmit pause experienced. Transmit pause experienced. DESCRIPTION
PHYError
Sviolation
FlowCtrl
Stormed
InBFull
TblUNAVL
Jabbered
LateCOL
TxPaused
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Table Port Operation Status Registers (Register (Continued)
CRSLoss Port Carrier Sense Loss During Transmission Status. carrier sense loss experienced. Carrier sense loss experienced. False Carrier Status. Transmit Queue Underflow Status. Normal Underflow experienced. Frame Time Out. Normal Frame time experienced. Port Operating Mode. half-duplex. full-duplex. half-duplex. full-duplex.
FalseCRS Underflow
TimeOut
PortMode
Indirect Resource Access Command Register (Register indirect resource access command allows management (Reverse EEPROM Method) access other resources other than AL102A register values. registers, both internal external address tables, SGRAM contents accessed using this command.
Table Indirect Resource Access Command Register (Register
NAME CmdDone DESCRIPTION Command Done. Execute command. Command done. Clear this execute command. When finished with command, AL102A will back "1". Read/Write Operation Command. Read operation. Write operation. Accessed Resource Type. 000: registers. 001: EEPROM. 010: SGRAM. 011: address table Read: table address read. Write: address learn. 100: address table Read: address search. Write: address delete. 101-111: Reserved
Operation
13~11
ResType
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Table Indirect Resource Access Command Register (Register
ExtRD External Address Table Read. ResType Operation On-chip address table read. Off-chip address table read. address entry within accessed resource.
ResAddr
Indirect Resource Access Data Register (Register Indirect Resource Access Data through used with indirect resource access command.
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data
Table Check (Register
15~8 NAME CheckSum Reserved DESCRIPTION Checksum value AL102A register contents.
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Timing Requirements
Table Transmit Timing
SYMBOL ttdv ttxev DESCRIPTION TXCLK valid time. TXCLK TXEN valid time. UNIT
TXCLK
ttxev ttxev
TXEN
ttdv
Figure Transmit Timing
DATA
DATA
DATA
DATA
DATA
DATA
Table Receive Timing
SYMBOL trxds trxdh DESCRIPTION RX_DV, RXD, RX_ER, setup time. RX_DV, RXD, RX_ER hold time. UNIT
RXCLK
trxdh
RXEN
trxds trxdh
Figure Receive Timing
DATA
DATA
DATA
DATA
DATA
DATA
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Table Management (MDIO) Read Timing
SYMBOL DESCRIPTION high time. time. period. MDIO setup time. MDIO hold time. UNIT
MDIO
Figure
Management Read Timing
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Table Management (MDIO) Write Timing
SYMBOL DESCRIPTION high time. time. period. MDIO output delay. UNIT
MDIO
Figure
Management Write Timing
Table SGRAM Refresh Timing
SYMBOL tCHI tCKH tCKS DESCRIPTION Access hold time. Access setup time. PBCS#, PBRAS#, PBWE# hold time. Clock high level width. System clock cycle time. hold time. setup time. Clock level width. PBCS#, PBRAS#, PBWE# setup time. Precharge command period. Auto-refresh auto-refresh period. UNIT
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PBCLK tCKS tCKH
tCHI
Command
Precharge
Auto Refresh
Auto Refresh
Active
BANK
BANK
Address
Don't Care
Figure
SGRAM Refresh Timing
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Table SGRAM Read Timing
SYMBOL tCHI tCKH tCKS tRAS tRCD DESCRIPTION Access time. Access hold time. Access setup time. PBCS#, PBRAS#, PBWE# hold time. Clock high level width. System clock cycle time. hold time. setup time. Clock level width. PBCS#, PBRAS#, PBWE# setup time. Data high impedance time. Data impedance time. Data hold time. Active precharge command period. Active read delay. UNIT
Note: This timing requirement SGRAM running Latency Typically speed grade SGRAM needs used.
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tCHI
PBCLK
tCKS
tCKH
BURST TERM.
Command
Active
READ
A0-A7
column
PBBA
BANK BANK
tRCD (Bank Latency
Dout
Dout
Dout
Dout
Dout
Dout
location within same
tRAS (Bank
Figure
SGRAM Read Timing
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Table SGRAM Write Timing
SYMBOL tCHI tCKH tCKS tRAS tRCD DESCRIPTION Access hold time. Access setup time. PBCS#, PBRAS#, PBWE# hold time. Clock high level width. System clock cycle time. hold time. setup time. Clock level width. PBCS#, PBRAS#, PBWE# setup time. Data hold time. Data setup time. Active precharge command period. Active read delay. 100,000 UNIT
Note: This timing requirement SGRAM running Latency Typically speed grade SGRAM needs used.
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tCHI
PBCLK
tCKS
tCKH
Command Active write BURST TERM.
A0-A7
column
BANK
PBBA
BANK
tRCD (Bank tRAS (Bank
Don't Care location within same Undefined
Figure
SGRAM Write Timing
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Electrical Specifications
Note: Operation absolute maximum ratings could cause permanent damage device.
Table Maximum Ratings
Supply Voltage (Vcc) Input Voltage Output Voltage Supply Voltage Input Voltage Output Voltage Storage Temperature -0.3V 3.6V -0.3 0.3V -0.3 0.3V -0.6V 6.0V -0.6 Vcc5 0.3V -0.6 Vcc5 0.3V +150
Table Recommended Operation Conditions
Supply Voltage Operating Temperature Power Dissipation 3.3V 0.3V (typical)
Table Electrical Characteristics
PARAMETER DESCRIPTION Output voltage-high, Ioh=4mA Output voltage-low, Ioh=4mA High impedance state output current Input current-high (With pull-up pull-down) Input current-low (With pull-up pull-down) Input high voltage Input voltage Supply current 0.7*Vcc 0.3*Vcc UNIT
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Reference Only Allayer Communications
AL102A Revision
AL102A Mechanical Data
PQFP Package
25.2
0.18 0.04
0.40
28.00 0.10 30.6 0.15
3.23 0.07
4.07 max. 0.60 0.10 0.25 1.30 0.10
0.25 min.
Figure
AL102A Mechanical Dimensions
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Reference Only Allayer Communications
AL102A Revision
Appendix (VLAN Mapping Work Sheet)
PORT 6/REG.
PORT
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Reference Only Allayer Communications
PORT 7/REG.
PORT 0/REG.
PORT 1/REG.
PORT 2/REG.
PORT 3/REG.
PORT 4/REG.
PORT 5/REG.
AL102A Revision
Appendix (Port Trunk Port Assignment Work Sheet)
PORT 0/REG.
PORT 1/REG.
PORT 2/REG.
PORT 3/REG.
PORT 4/REG.
PORT 5/REG.
PORT 6/REG.
TRUNK PORT
BIT/ VALUE
TRUNK BITS TRUNK BITS
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Reference Only Allayer Communications
PORT 7/REG.
AL102A Revision
Appendix (Suggested Memory Components)
Note: This only partial list memory components that used Allayer devices. AL102A uses Frame Buffer SGRAM chips that require 32-bit wide SGRAM SDRAM, that faster with latency
DEVICE
FREQ.
Mbit SGRAM
Mbit SGRAM
AL102A
MoSys MG802C256Q-10 Etron EM635327Q-8
MoSys MG802C512L-8 Etron EM636227Q-8 Winbond W971632AF-8 Hitachi HM5216326FP-8
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Reference Only Allayer Communications
AL102A Revision
Rev. History (Prelim. 1.2) Reformatted edited document. Added memory information appendix III. Rev. History (Prelim 1.3) Added management timing diagrams. Added RMII timing diagrams. Prelim Rev. Fully released document.
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Reference Only Allayer Communications
Index
Address Aging Address Learning AL102A Diagram Appendix (VLAN Mapping Work Sheet) Appendix (Port Trunk Port Assignment Work Sheet) Appendix (Suggested Memory Components) Broadcast Storm Control Data Reception Electrical Characteristics EEPROM Interface EEPROM EEPROM Random Read Cycle EEPROM Random Write Cycle EEPROM Start Stop False Carrier Events Flow Control Frame Filtering Frame Forwarding Frame Generation Frame Transmission Functional Description Half Duplex Flow Control (Backpressure) Half Duplex Mode Operation Illegal Frame Length Indirect Resource Access Command Register (Register Indirect Resource Access Data Register (Register Load Balancing Long Frames Maximum Ratings Media Independent Interface (MII) Interface Port Interface Port Interface Port Interface Port Management Interface Receive Timing Transmit Timing Miscellaneous Pins Auto-negotiation Mode Other Options Management Management (MDIO) Read Timing Management (MDIO) Write Timing Management Master Mode Management MDIO Management Slave Mode Descriptions Port Based Trunk Load Balancing Port Configuration Register Port Configuration Register Port Configuration Registers (Registers Port Monitoring Port Monitoring Configuration Register (Register Port Operation Status Registers (Register Port Trunk Port Assignment Registers (Registers Port VLAN Registers (Registers Power Interface Queue Management Read Cycle Timing Recommended Operation Conditions Reprogramming EEPROM Configuration Reserved Register (Register Reserved Register (Register RMON Source Destination Registers (Registers Secure Mode Operation SGRAM Interface SGRAM Refresh Timing SGRAM Write Timing Static Address Entry Format EEPROM System Block Diagram System Configuration Register (Register System Configuration Register (Register System Configuration Register (Register System Initialization Trunk Port Assignment Trunk Port Numbering Trunking (Port Aggregation) Uplink Port Vendor Specific Register (Register VLAN Port Switch VLAN Mapping Port Based Load Balancing Trunk VLAN Support
Reference Only Allayer Communications
AL102A Revision
Write Cycle Timing
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Reference Only Allayer Communications

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