Supports eight 10/100 Mbit/s Ethernet ports with interface Capable tru
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AL100A Revision PORT COST 10/100 SWITCH
Supports eight 10/100 Mbit/s Ethernet ports with interface Capable trunking Mbit/s link with link fail over Full- half-duplex mode operation Supports addresses Designed utilize low-cost SGRAM Scalable design stackable switch implementation expansion link supports Gbit/s throughput Gigabit Ethernet ready Speed auto-negotiation through MDIO Automatic source address learning Product Description AL100A eight-port 10/100 Mbit/s dual speed Ethernet switch. low-cost scalable solution achieved through low-cost buffer memory Allayer's proprietary RoXarchitecture. AL100A also supports VLAN multiple port aggregation trunks.
10/100 Switch Controller Buffer Manager
Secure mode traffic filtering Broadcast storm control Port monitoring support IEEE 802.3x flow control full-duplex operation RMON SNMP support with external management (MIB) device Optional backpressure flow control support half duplex operation Supports store-and-forward mode switching VLAN support 3.3V operation Packaged 388-pin
10/100 Expansion Interface 10/100 High Speed Switch Fabric Address Control
10/100
10/100
Address Table
10/100 EEPROM Interface Management Information 10/100
10/100
Figure
System Block Diagram
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This document contains proprietary information which shall reproduced, transferred other documents, used other purpose without prior written consent Allayer Communications.
Disclaimer Allayer Communications reserves right make changes, without notice, product(s) described information contained herein order improve design and/or performance. Allayer Communications assumes responsibility liability these products, conveys license title under patent copyright these products, makes representations warranties that these products free from patent copyright infringement unless otherwise specified.
Life Support Applications Allayer Communications products designed life support appliances, systems, devices where malfunctions reasonably expected result personal injury.
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Table Contents
AL100A Overview. Descriptions. Functional Description. Interface. Data Reception. 3.2.1 3.2.2 3.2.3 3.2.4 3.3.1 3.3.2 3.3.3 Illegal Frame Length Long Frames False Carrier Events Frame Filtering. Broadcast Storm Control. Frame Transmission Frame Generation.
Frame Forwarding.
Half Duplex Mode Operation Secure Mode Operation Address Learning 3.6.1 Address Aging. VLAN Support. Trunking (Port Aggregation). 3.8.1 3.8.2 3.8.3 3.8.4 Load Balancing Trunk Port Assignment Port Based Trunk Load Balancing Based Load Balancing
3.10
Spanning Tree Support. Flow Control Half Duplex Flow Control (Backpressure) Full Duplex Flow Control (802.3x)
3.10.1 3.10.2 3.11 3.12 3.13 3.14 3.15
Queue Management Port Monitoring. Uplink Port. Media Independent Interface (MII) Management.
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3.15.1 3.15.2 3.15.3 3.15.4 3.15.5 3.16 3.17
Management MDIO Management Master Mode Management Slave Mode. Non-Auto-negotiation Mode. Other Options.
SGRAM Interface EEPROM Interface System Initialization Start Stop Read Cycle Timing Reprogramming EEPROM Configuration EEPROM
3.17.1 3.17.2 3.17.3 3.17.4 3.17.5
Register Descriptions. Timing Requirements. Electrical Specifications AL100A Mechanical Data Appendix (VLAN Mapping Work Sheet) Appendix (Port Trunk Port Assignment Work Sheet) Appendix (Suggested Memory Components).
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AL100A Overview
interface Gbit/s interface (4.8 Gbit/s full-duplex). interface support four switch chips. Various combinations used different configurations. maximum port configuration will either 32-port Mbps ports 24-port Mbps plus Gigabit Ethernet ports. AL100A provides eight 10/100 Mbps Ethernet ports that supports both Mbps data rates. operation mode auto-negotiated PHY. ports full-duplex capable. interface also supports external management device. external management device supports SNMP RMON. AL100A supports port based VLAN. VLAN register used configure destination ports multicast broadcast frames. device also supports VLAN workgroup segment switching applications. AL100A supports trunking applications. chip provides optional load balancing schemes, explicit dynamic. With trunking, possible group four full-duplex links together form single Mbps link. AL100A utilizes cost effective SGRAM provide 8-Mbps 16-Mbps buffer memory. During transmission, data obtained from buffer memory routed destination port. event collision during half-duplex operation, control will back retransmit accordance IEEE 802.3 specifications. Data received from interface stored external memory buffer. AL100A provides flow control methods. half-duplex operation, optional jamming based flow control (also known backpressure) available prevent loss data. With this method flow control, switch will generate signal when receive-buffer full. sending station will transmit until line clear. full-duplex mode, AL100A utilizes IEEE 802.3x flow control mechanism. ports support multiple addresses. switch chip supports addresses internally. These addresses shared among eight ports. Additional SRAM added provide addresses support. initialization configuration switch programmed external EEPROM. unmanaged switch design, there need CPU. Field reconfigurations achieved using parallel interface reprogram EEPROM. managed switch applications, AL100A supports network management through network management option. When management option enabled, network statistics each port gathered sent across bus. management information base chip will collect store data network management agent. Access statistic counters provided interface device. AL100A operates only store forward mode. entire frame checked errors. Frames with errors automatically filtered forwarded destination port. device also provides levels security intrusion protection. Security implemented port basis. Other features include port monitoring broadcast storm throttling.
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Diagram
Figure
AL100A Diagram (Top View)
Note: balls center should connected ground. These pins rows column
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Descriptions
Table Interface Port
NAME M0TXD3 M0TXD2 M0TXD1 M0TXD0 M0TXEN M0TXCLK M0RXD3 M0RXD2 M0RXD1 M0RXD0 NUMBER DESCRIPTION Transmit Data data transmitted transceiver. mode signal, TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. RMII mode M0TXD1 M0TXD0 clocked RMII reference clock M0RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M0TXEN sychronous M0RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge M0RXCLK. RMII mode, M0RXD3 M0RXD2 used. M0RXD1and M0RXD0 sampled rising edge RMII reference clock M0RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). RMII clock port Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M0RXDV M0RXCLK M0RXER M0CRS M0COL
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Table Interface Port
NAME M1TXD3 M1TXD2 M1TXD1 M1TXD0 M1TXEN M1TXCLK M1RXD3 M1RXD2 M1RXD1 M1RXD0 NUMBER DESCRIPTION Transmit Data data transmitted transceiver. mode, signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. RMII mode, M1TXD1 M1TXD0 clocked RMII reference clock M3RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M1TXEN synchronous M3RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge M3RXCLK. RMII mode, M1RXD3 M1RXD2 used. M1RXD1and M1RXD0 sampled rising edge RMII reference clock M3RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). RMII clock port Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M1RXDV M1RXCLK M1RXER M1CRS M1COL
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Table Interface Port
NAME M2TXD3 M2TXD2 M2TXD1 M2TXD0 M2TXEN M2TXCLK M2RXD3 M2RXD2 M2RXD1 M2RXD0 NUMBER DESCRIPTION Transmit Data data transmitted transceiver. mode, signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. RMII mode, M2TXD1 M2TXD0 clocked RMII reference clock M3RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M2TXEN synchronous M3RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge M3RXCLK. RMII mode, M2RXD3 M2RXD2 used. M2RXD1and M2RXD0 sampled rising edge RMII reference clock M3RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). RMII clock port Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M2RXDV M2RXCLK M2RXER M2CRS M2COL
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Table Interface Port
NAME M3TXD3 M3TXD2 M3TXD1 M3TXD0 M3TXEN M3TXCLK M3RXD3 M3RXD2 M3RXD1 M3RXD0 NUMBER AD10 AE10 AF10 AF12 AD12 AC12 AF11 DESCRIPTION Transmit Data data transmitted transceiver. mode, signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. RMII mode, M3TXD1 M3TXD0 clocked RMII reference clock M3RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M3TXEN synchronous M3RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge M3RXCLK. RMII mode, M3RXD3 M3RXD2 used. M3RXD1and M3RXD0 sampled rising edge RMII reference clock M3RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). RMII clock port Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M3RXDV M3RXCLK M3RXER M3CRS M3COL
AE11 AD11 AC11
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Table Interface Port
NAME M4TXD3 M4TXD2 M4TXD1 M4TXD0 M4TXEN M4TXCLK M4RXD3 M4RXD2 M4RXD1 M4RXD0 NUMBER AD16 AE16 AF16 AD17 AE17 AF17 AF19 AD19 AC19 AF18 DESCRIPTION Transmit Data data transmitted transceiver. mode, signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. RMII mode, M4TXD1 M4TXD0 clocked RMII reference clock M3RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M4TXEN synchronous M3RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge M3RXCLK. RMII mode, M4RXD3 M4RXD2 used. M4RXD1and M4RXD0 sampled rising edge RMII reference clock M3RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). RMII clock port Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M4RXDV M4RXCLK M4RXER M4CRS M4COL
AE18 AD18 AC18 AD15 AF15
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Table Interface Port
NAME M5TXD3 M5TXD2 M5TXD1 M5TXD0 M5TXEN M5TXCLK M5RXD3 M5RXD2 M5RXD1 M5RXD0 NUMBER AF26 AE26 AD25 AC24 AC25 AC26 AA26 AA24 AA23 AB26 DESCRIPTION Transmit Data data transmitted transceiver. mode, signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. RMII mode, M5TXD1 M5TXD0 clocked RMII reference clock M3RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M5TXEN synchronous M3RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge M3RXCLK. RMII mode, M5RXD3 M5RXD2 used. M5RXD1and M5RXD0 sampled rising edge RMII reference clock M3RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). RMII clock port Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M5RXDV M5RXCLK M5RXER M5CRS M5COL
AB25 AB24 AB23 AE24 AE25
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Table Interface Port
NAME M6TXD3 M6TXD2 M6TXD1 M6TXD0 M6TXEN M6TXCLK M6RXD3 M6RXD2 M6RXD1 M6RXD0 NUMBER DESCRIPTION Transmit Data data transmitted transceiver. mode, signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. RMII mode, M6TXD1 M6TXD0 clocked RMII reference clock M3RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M6TXEN synchronous M3RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge M3RXCLK. RMII mode, M6RXD3 M6RXD2 used. M6RXD1and M6RXD0 sampled rising edge RMII reference clock M3RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). RMII clock port Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M6RXDV M6RXCLK M6RXER M6CRS M6COL
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Table Interface Port
NAME M7TXD3 M7TXD2 M7TXD1 M7TXD0 M7TXEN M7TXCLK M7RXD3 M7RXD2 M7RXD1 M7RXD0 NUMBER DESCRIPTION Transmit Data data transmitted transceiver. mode, signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. RMII mode, M7TXD1 M7TXD0 clocked RMII reference clock M3RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M7TXEN synchronous M3RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge M3RXCLK. RMII mode, M7RXD3 M7RXD2 used. M7RXD1and M7RXD0 sampled rising edge RMII reference clock M3RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). RMII clock port Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M7RXDV M7RXCLK M7RXER M7CRS M7COL
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Table Input Interface
NAME RID31 RID30 RID29 RID28 RID27 RID26 RID25 RID24 RID23 RID22 RID21 RID20 RID19 RID18 RID17 RID16 RID15 RID14 RID13 RID12 RID11 RID10 RID9 RID8 RID7 RID6 RID5 RID4 RID3 RID2 RID1 RID0 RIDH RICTL7 RICTL6 RICTL5 RICTL4 RICTL3 RICTL2 RICTL1 RICTL0 RICTLH RICLK DESCRIPTION
Ring Input Device.
Ring Control Signal.
Ring Clock.
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Table Output Interface
NAME ROD31 ROD30 ROD29 ROD28 ROD27 ROD26 ROD25 ROD24 ROD23 ROD22 ROD21 ROD20 ROD19 ROD18 ROD17 ROD16 ROD15 ROD14 ROD13 ROD12 ROD11 ROD10 ROD9 ROD8 ROD7 ROD6 ROD5 ROD4 ROD3 ROD2 ROD1 ROD0 RODH ROCTL7 ROCTL6 ROCTL5 ROCTL4 ROCTL3 ROCTL2 ROCTL1 ROCTL0 ROCTLH AF23 AE23 AD23 AC23 AF22 AE22 AD22 AF21 AE21 AD21 AC21 AF20 AE20 AD20 DESCRIPTION
Ring Output Device.
Ring Output Data Header.
Ring Control Data.
Ring Output Control Header.
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Table SGRAM Interface
NAME PBD31 PBD30 PBD29 PBD28 PBD27 PBD26 PBD25 PBD24 PBD23 PBD22 PBD21 PBD20 PBD19 PBD18 PBD17 PBD16 PBD15 PBD14 PBD13 PBD12 PBD11 PBD10 PBD9 PBD8 PBD7 PBD6 PBD5 PBD4 PBD3 PBD2 PBD1 PBD0 PBA9_10 PBA8_9 PBANC_8 NUMBER DESCRIPTION
SGRAM Data Bus.
SGRAM Address. Mbps SGRAM, this PBA10 Mbps SGRAM this SGRAM Address. Mbps SGRAM, this PBA9 Mbps SGRAM this This connected address when connected Mbps SGRAM unconnected when connected Mbps SGRAM.
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Table SGRAM Interface (Continued)
PBA7 PBA6 PBA5 PBA4 PBA3 PBA2 PBA1 PBA0 PBCS# PBRAS# PBCAS# PBWE# PBCLKI SGRAM address line PBA0- PBA8 sampled during ACTIVE command (row address) READ/WRITE command (column address with PBA8 defining auto precharge).
Chip Select. Enables disables command decoder SGRAM. SGRAM Address Strobe. SGRAM Column Address Strobe. Write Enable. System Clock Output drive SGRAM.
Table EEPROM Interface
NAME EEDIO EECLK NUMBER DESCRIPTION EEPROM Serial Data Input Output. EEPROM Serial Clock.
Table MDIO Interface
NAME MDIO NUMBER AD13 AE13 DESCRIPTION Management Clock. Management Data Input Output.
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Table Miscellaneous Pins
NAME DEVID0 DEVID1 RESET# TESTMODE EPBYPASS SYSCLK TRST TCLK NUMBER AC14 AF13 AD14 AE14 AF14 DESCRIPTION Device number. Reset Test Mode Pin. This should grounded normal operation. This bypasses EEPROM setup. This should tied ground. system clock. Reserved JTAG scan. Testing output. Leave unconnected. Reserved JTAG scan. Testing output. Leave unconnected. Reserved JTAG scan. Testing output. Leave unconnected. Reserved JTAG scan. Testing output. Leave unconnected. Reserved JTAG scan. Testing output. Leave unconnected.
Table Power Interface
NAME NUMBER A18, A19, A23, A24, A26, B12, B15, B23, C10, C12, C15, D10, D17, D18, D23, E25, K23, L23, M23, N25, U23, Y23, AA2, AA25, AB4, AC8, AC9, AC10, AC15, AC16, AC20, AD24, AE8, AE15, AE19, AF2, AF3, A20, B13, C13, C24, D19, G23, H23, J23, J25, R23, T23, U25, W23, AC4, AC5, AC7, AC13, AC17, AC22, AE12, AF24, AF25, AD26 Ground DESCRIPTION
(3.3V)
3.3V supply voltage.
VccM
Supply voltage interface. VccM interface) VccM 3.3V (3.3V interface)
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MXTXD3 MXTXD2 MXTXD1 MXTXD0 MXTXEN MXTXCLK MXRXD3 MXRXD2 MXRXD1 MXRXD0 MXRXDV MXRXCLK MXRXER MXCRS MXCOL PBD[n] PBA[n] PBBA PBCS PBRAS PBCAS PBWE PBDSF PBDQM PBCLK
10/100 10/100 10/100 10/100 10/100 10/100 10/100 10/100 High Speed Switch Fabric
Switch Controller Expansion Interface Address Control
ROD[n] ROCTL[n] RODH ROCTLH RID[n] RICTL[n] RIDH RICTLH RICLK
Address Table Buffer Manager Management Management Information EEPROM Interface EEDIO EECLK MDIO
DEVID0 DEVID1 RESET
Figure
AL100A Interface Block Diagram
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Functional Description
Interface
switch system shown Figure 24-port 10/100 Mbps switch with Gigabit Ethernet ports. This system utilizes Allayer's proprietary architecture. architecture ring structure that serves system backplane.
AL300A
AL100A
AL100A
AL100A
AL1000
Figure
Port Mbps Port Gbps Managed Switch with
ring composed data ring control ring. data ring used transfer frame data, events, well system configuration status report messages. control ring used communicate ring protocol messages among devices switch backbone resources data transfer data ring. Each device ring input interface receiving data frames ring protocol messages from upstream device, output interface transmitting data frames ring protocol messages downstream device. management device (MIB) resides ring. provides network management function devices ring. device collects network statistics switch system well provides system configurations devices. interface provided device. This supporting chip, AL300A, provides full statistical counters support both SNMP RMON network management.
Data Reception
port will into receive-state when RX_DV interface asserted. (Media Independent Interface) presents received data four-bit nibbles that synchronous receive clock Mbps Mbps). AL100A will then attempt detect occurrence (Start Frame Delimiter) pattern "10101011." preamble data prior discarded. Once detected from interface, frame data forwarded stored buffer switch.
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3.2.1 Illegal Frame Length During receiving process, AL100A will monitor length received frame. Legal Ethernet frames should have length less than bytes more than 1536 bytes. frames that illegal frame length discarded. 3.2.2 Long Frames AL100A handle frame sizes 1536 bytes. frames longer than 1536 bytes will discarded. port continues receive data after 1536th byte, port's data will filtered. port half duplex mode, port will longer able transmit receive data during long frame reception. 3.2.3 False Carrier Events (Carrier Sense) signal interface asserted receive RX_DV (Receive Data Valid) signal asserted within 16BT (Bit Period), port considered have false carrier event. 3.2.4 Frame Filtering AL100A will make filtering forwarding decisions each frame received based frame routing table, VLAN Mapping, port state, system configuration. Under following conditions, received frames filtered: AL100A will check received frames errors such symbol error, error, short event, runt, long event, etc. Frames with kind error will forwarded their destination port. frame heading source port will filtered. Frames heading disabled receiving port will filtered. input buffer port full, incoming frame will discarded. recommended that flow control used prevent loss data. flow control option enabled, this event will occur. remote station will transmit frame when input buffer becomes available. frame security violation security option enabled receiving port.
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Frame Forwarding
After frame received, both source address (SA) destination address (DA) retrieved. used update port's address table used determine frames destination port. Address Lookup Engine will attempt match destination address with addresses stored address table. there match found, link between source port destination port then established. first destination address "0," frame regarded unicast frame. destination address passed Address Lookup Engine, which returns matched destination port number identify which port frame should forwarded destination port within same VLAN receiving port, frame will forwarded. destination port does belong VLANs specified receiving ports, frame will discarded will recorded VLAN boundary violation. There ways that AL100A handles frames with unknown destinations. forwarding decision controlled Flood Control option (System Configuration register 00). Flood Control disabled, frame will forwarded ports (except receiving port) within same VLANs receiving port. Flood Control option enabled, AL100A will forward frame only uplink port specified receiving port. Note: AL100A defines port either single port trunk. port monitoring function enabled, frame forwarding decision also subject port monitoring configurations. first destination address "1," frame will handled multicast broadcast frame. AL100A does differentiate multicast frames from broadcast frames except reserved bridge management group address, specified Table IEEE 802.1d Standard. destination ports broadcast frame ports within same VLAN except source port itself. 3.3.1 Broadcast Storm Control unique features provided AL100A Broadcast Storm Control. This option allows user limit number broadcast frames into switch. This option implemented port basis. threshold number broadcast frames programmed System Register (register 01). When Storm Control enabled number cumulated non-unicast frames over programmed threshold, broadcast frame discarded. Storm Control disabled, number non-unicast frames received over programmed threshold, AL100A will forward frame ports (except receiving port) specified within VLANs receiving port. Broadcast-Storm-drop (BConly_SC) enabled System Register (register 02), AL100A will only drop broadcast frames multicast frames.
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3.3.2 Frame Transmission AL100A transmits frames accordance IEEE 802.3 Standards. AL100A will send frames with guaranteed minimum (Inter Packet Gap) 96BT even received frames have less than minimum requirement. AL100A also supports transmission frames with 64BT (optional). This option selected System Register III, (register 02). 3.3.3 Frame Generation During transmit process frame data read from memory buffer forwarded destination port's device di-bits. Seven bytes preamble signal (10101010) will generated first before (10101011). Frame data sent after along with four bytes end. Summary Programmable Control Transmit Receive control transmit receive port basis. options programmable port configuration register (registers 1C). Data Rate Duplex Mode this option port option. Typically, speed auto-negotiated. manual override, appropriate port configuration register programmed. Flow Control flow control implemented independently port basis. AL100A uses backpressure half-duplex flow control IEEE802.3x full duplex flow control. Flood Control AL100A provides modes unmatched address forwarding. flood-to-all option elected, AL100A will forward unmatched frames ports. Secure Mode security option implemented port basis. When port configured secured mode, security violation will disable port. security violation defined frame without matched secured port's address table.
Half Duplex Mode Operation
half duplex operations, logic will abort transmit-process collision detected. Re-transmission frame scheduled accordance IEEE 802.3's truncated binary exponential back algorithm. transmit process encountered consecutive collisions, excessive collision error reported AL100A will re-transmit frame unless retry-on-excessive-collision (REC) option System Register (register enabled. When enabled, number collisions reset zero transmission started soon 96BT inter-frame passed after last collision. collision detected after 512BT transmission, late collision error will reported frame will still retransmitted after proper back time. AL100A also provides option aggressive back System Configuration Register (SuperMAC). This option allows back only three slots. This will create more aggressive channel capture behavior than standard IEEE back algorithm.
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Secure Mode Operation
AL100A provides security support port basis. Whenever secure mode enabled, port will stop learning addresses. address table each port will remain unchanged. this mode operation, address lookup table will freeze additional addresses will learned. AL100A provides levels security protection. most severe intrusion protection disabling port intrusion experienced. security management (SecMgmt register will disable port frame with unlearned source address (SA) received from secured port (security violation). alternative enable security local port level without security management. When AL100A configured this way, device will only discard frames that have security violations, which prevents intruders from accessing network. Summary Programmable Registers SecMgmt (register this sets global security management option. AL100A will partition port that experiences security violations. Security (register this port configuration option. When this option enabled, port secured. When port receives security violation frame, will discard frame security management disable port security management
Address Learning
Table Lookup Engine provides switching information required route data frames. address look table set-up through auto address learning (dynamic) manual entry (static). static addresses assigned address table EEPROM. static address entries will aged updated AL100A. After frame received AL100A, embedded (SA) destination address (DA) retrieved. source address retrieved from received frame automatically stored buffer. AL100A will then check errors security violations, perform search. there errors security violations, AL100A will store source address address lookup table. been previously stored another port's table, AL100A will delete from previously stored location. Individual Address 48-bit unique address programmed learned. will masked, i.e. multicast AL100A provides on-chip Address-to-PortID/TrunkID table frame destination look-up operations. AL100A address table contains both static addresses input EEPROM dynamically learned address. learns individual addresses from frames received with errors from local ports. received frames that contain source address learned another port's address table that hasn't been aged out, perform following based switches; security option selected port, AL100A considers this security violation; port non-protected port, AL100A will delete from previous port's address table update current port's address table. However, static address entry, address will updated.
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3.6.1 Address Aging port's address register cleared power-up, hardware reset. aging option enabled, dynamically learned will cleared refreshed within programmed time. Summary Programmable Options Address Learning Address Aging Time address aging aging time programmed System Configuration (register 01). resolution aging time normally 1-second increments. AgeRes (register programmed resolution will 2-second increments. Static Programmed Addresses twenty static addresses programmed EEPROM address EEPROM section programming more detail.
VLAN Support
Each port AL100A assigned multiple VLANs. Frames from source port will only forwarded destination ports within same VLAN domain. broadcast/multicast frame will forwarded ports within VLAN(s) except source port itself. unicast frame will forwarded destination port only destination port same VLAN source port. Otherwise, frame will treated frame with unknown destination port belongs another VLAN, frame will discarded event will recorded VLAN boundary violation. Each port assigned with dedicated uplink port. Unicast frames with unknown destination addresses will forwarded uplink port source port. uplink port either single port trunk. AL100A provides VLAN register ports (register mapping 8-ports (8bits). Each register contains 8-bit indicate VLAN group port. VLAN registers hold broadcast destination mask each source port. value will indicate broadcast frames will routed from source port specified port. Note that source port must within source port VLAN, because broadcast frames routed source port. VLAN Example VLAN worksheet provided Appendix complete VLAN easily simply marking ports wish send broadcast frame example, let's assume want VLAN groups 8-port switch: Group consists Group consists completed VLAN maps shown Table
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Table VLAN Port Switch
PORT 6/REG. PORT 7/REG. PORT 0/REG. PORT 1/REG. PORT 2/REG. PORT 3/REG. PORT 4/REG. PORT 5/REG.
PORT
Trunking (Port Aggregation)
AL100A supports trunking/port aggregation. Port aggregation trunking essentially method treat multiple physical links single logical link. benefit trunking ability group multiple lower speed links into higher speed link. example, four full duplex Mbps links used single 800-Mbps link. This very useful switch switch, switch server, switch router applications. AL100A considers trunk single port entity regardless trunk composition. four ports grouped together single trunk link. grouping ports trunk must from four ports bottom four ports device, i.e. port port multiple link trunk, links within trunk should have balanced amount traffic order achieve maximum efficiency. requirements transmission that frames being transmitted must order. Therefore, some sort load balancing among links trunk must deployed. AL100A offers methods load balancing which selected System Configuration Register (register 00). 3.8.1 Load Balancing load-balancing methods that AL100A uses support trunking port based address based. Port based load balancing method explicit port assignment scheme. requires each individual port assigned specific link (trunk port) trunk. port assigned, frame might routed trunk randomly which cause frames order. port based load balancing trunk assigned 4-port trunk.
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During transmission frame, will routed from source port assigned trunk port. When frame received from trunk ports, will routed destination port within VLAN. essence, AL100A treats trunk single port within same VLAN. ports traffic evenly distributed among trunk ports, load balancing achieved aggregate bandwidth trunk high Mbps (full duplex). alternative address based load balancing. When AL100A receives frame with trunk destination, will automatically forward frame port trunk based source address. address load balancing decision based proprietary algorithm. address based load-balancing scheme must four ports trunk. 3.8.2 Trunk Port Assignment maximum number trunks AL100A two. Port Configuration Register provides ability designate port member trunk. trunk consist four trunk ports. trunk group must consist either four ports bottom four ports, example trunk consist port through port port through port Each trunk port's number sequence corresponding order port devices. example, port (See Figure
AL100A
Ports
Trunk Port
Trunk Port
Figure
Trunk Port Numbering
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3.8.3 Port Based Trunk Load Balancing port-based load balancing, trunk port must assigned each port defined trunks. port assignment done programming Port Trunk Port registers 34). recommended that ports evenly distributed among trunk ports prevent overloading single trunk port. Port Based Load Balancing Example Note: Register bits referenced where register number number. Appendix provide worksheet port trunk port VLAN assignments. example designing 8-port switch with 3-port based loading trunk. desired trunk ports want assign port trunk port Port trunk port port trunk port Port Configuration register bits 15.9, 16.9, 17.9 This assigns ports trunk port. Assign port trunk port port trunk port port trunk port Therefore, port trunk port register bits. 2D.2 2D.3 2E.2 2E.3 2F.2 2F.3 30.2 30.3 31.2 31.3 Trunk ports should assigned with their port number port trunk Port register. port trunk-port bits follows: 32.2 32.3 33.2 33.3 34.2 34.3 remaining bits zeros port trunk port registers. Assigning VLAN. VLAN should assigned shown. bits while bits 1E.6 1E.7 because port assigned port other ports similarly. Bits through reserved should VLAN mapping registers.
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Table VLAN Mapping Port Based Load Balancing Trunk
PORT 6/REG. PORT 7/REG. PORT 0/REG. PORT 1/REG. PORT 2/REG. PORT 3/REG. PORT 4/REG. PORT 5/REG.
PORT
3.8.4 Based Load Balancing address based load balancing, there need assign port trunk port. AL100A dynamically assigns addresses trunk port. address based trunks must consist four trunk ports. bits chosen their randomness. statistically random bits will ensure good load balancing among four trunk-ports. following procedure based load trunk. Select address loading setting 00.3 Select trunk ports using Port Configuration Register Assign ports trunk port same VLAN using register port VLAN grouping should include trunk ports. Since AL100A will assign port addresses, frames from single port routed trunk ports. Based Load Balancing Example simplicity, example eight-port switch with four-port trunk. desired trunk port Therefore, port configuration register bits 15.9, 17.9, 19.9, 1B.9 Assigning VLAN. VLAN assigned shown. bits except ports themselves.
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Table VLAN Mapping Based Loading Trunk
PORT 6/REG. PORT 7/REG. PORT 0/REG. PORT 1/REG. PORT 2/REG. PORT 3/REG. PORT 4/REG. PORT 5/REG.
PORT
Summary Programmable Registers System Configuration (register 00.3 sets trunk address loading. System Configuration (register 01.0 01.1 bits address loading algorithm. Trunk Port Designation (registers port configuration register designates port trunk port. Port Trunk Port Loading Assignment (registers these registers assign loading trunk. Port VLAN (register these registers assign port VLAN.
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Spanning Tree Support
AL100A capability support implementation Spanning Tree Protocol. ports programmed port state required spanning tree protocol. Spanning Tree Protocol option enabled, AL100A will forward frame below. port Block-N-Listen State Learning State, frame forwarded BPDU frame; otherwise frame discarded. outgoing frames except outgoing BPDU's will masked from path PHY. port Forwarding State, frame forwarded BPDU frame. source addresses incoming frames from will learned then forwarded based switch routing decision. outgoing frames will transmitted PHY.
port learning, source addresses incoming frames from will learned. incoming frames except incoming BPDU's from will discarded after being learned; outgoing frames except outgoing BPDU's will masked from path PHY.
3.10 Flow Control
AL100A operate different modes, half full duplex. Each port operate either full half duplex configured have flow control enabled flow control independently port basis. 3.10.1 Half Duplex Flow Control (Backpressure) half-duplex flow control option elected, back-pressure will used flow control. Whenever occupancy receiving frame buffer port full, port will start sending signal through port. After sensing signal remote station will defer transmission. Backpressure flow control applied ensure that there dropped frame. AL100A supports types backpressure, collision based carrier based. Carrier based backpressure generated AL100A, when switch port's frame buffer full. AL100A will cease line when port buffer space available frame reception. jamming signal selected from 48BT, 56BT, 65BT, 72BT, 96BT. This selected register bits BpIPGSelEn must select backpressure less than 96BT. Collision based backpressure generated AL100A, only when switch port receives frame. AL100A will cease line, when line idle. carrier based backpressure several advantages over collision based backpressure such Collision based backpressure cause late collision. After consecutive collisions, could drop frames. AL100A option drop frames after collisions. However, terminal still drop frames.
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Therefore, recommend carrier based backpressure preferred method halfduplex flow control. this mode operation, also recommend that signal should less than 96BT. This because 96BT, terminal might still able transmit frame cause collision. excessive collision could cause frames dropped. AL100A also supports collision-based backpressure customers that prefer collision-based backpressure. 3.10.2 Full Duplex Flow Control (802.3x) full duplex mode, AL100A will transmit receive frame accordance with 802.3x. Note that transmission channel receiving channel operate independently. incoming direction, whenever occupancy receiving frame buffer port full, port will send PAUSE frame with delay value maximum. PAUSE frame will deter incoming frame from flowing into port. After occupancy receiving frame buffer reduced below backpressure watermark level (register 10), port will then send PAUSE frame with delay value zero resume receiving incoming frame flow. outgoing direction, whenever incoming PAUSE frame with non-zero delay value received through port, port will stop next frame transmission after ongoing frame transmission finished. will start pause timer resume frame transmission either after pause timer expired when PAUSE frame with zero delay value received. When 802.3x flow control option elected, device will program appropriate auto-negotiation capability field. When AL100A used full duplex mode, recommended that flow control turned which prevents buffer from overflow loss frames. connected device 802.3x capability, then recommended link setting halfduplex.
3.11 Queue Management
AL100A ports have advanced queue management algorithm optimal switching performance. frames received AL100A stored into shared memory. frame unicast type, location frame buffer then passed destination output queue manager. Destination Output Queue Manger extract frame from buffer transmit. output queue manager receives more frames than send out, simply stores locations frames transmits them after transmitting current frame. There ways manage output queues. method that eight output queues will share entire frame buffer. When this method chosen, there limitation many frames allocated output queue. frames stored buffer until buffer full. When extreme cases congestion experienced, such traffic merging into single port speed mismatch long period time, single output queue occupy entire buffer causing other ports drop frames. this case, flow control option recommended when frame buffer full, incoming frames will backpressured. other option limit number frames that each output queue store. output queue watermark System Configuration Register (register bits [7:6]) prevent buffer starvation heavy congestion. This method prevents other ports from suffering performance reduction single
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port experiencing extreme congestion. severe congestion experienced single port, only that port will suffer from frame loss because buffer limited dedicated portion. Other ports will experience frame loss congestion problems other ports since other ports retain their allocated buffer space. AL100A separate multicast output queues, Mbps Mbps, optimize multicast performance speed mismatch present. When Mbps port broadcasting multicasting, Mbps ports will finish transmitting before Mbps ports. Because Mbps multicast queue separate from Mbps multicast queue, Mbps ports will experience performance reduction. continuous stream multicast frames experienced, eventually Mbps multicast queue will become filled cause frame loss. Losing frames cause multiple retransmissions network application resulting inefficient utilization network resources. AL100A offers option drop frames only Mbps multicast queue Miscellaneous Register (register 11). With this option enabled, Mbps ports will drop frames when Mbps multicast queue full Mbps ports will continue operate full speed regardless Mbps multicast queue condition. This feature very useful applications such multimedia where dropping frames acceptable slower connections. When output queue multicast queue experiences buffer full condition, AL100A will backpressure incoming frames flow control enabled. watermark buffer full condition selected register
3.12 Port Monitoring
AL100A supports port monitoring. This feature provides complete network monitoring capability Mbps. copy egress (TX) data ingress (RX) data monitored port sent their respective snooping ports. monitored port selected register AL100A allows transmit receive data monitored different snooping ports. snooping ports also selected register
3.13 Uplink Port
uplink port provides means connect switch with repeater hub, workgroup switch, router, type interconnecting device compliance with IEEE 802.3 standards. flood control enabled, AL100A will send frames with unmatched multicast/ broadcast frames uplink port. very important that each port assigned uplink port Port Configuration Register to1C), data frames might lost. uplink port should configured within same VLAN source port. uplink port member VLANs, broadcast multicast frames will forwarded designated uplink port. Multiple VLANs share same uplink port. AL100A will direct following frames uplink port: Frames with unicast destination address that doesn't match with address stored switch. Frames with broadcast/multicast destination address uplink port same VLAN.
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Note: When configuring uplink port, uplink port should designate itself uplink port.
3.14 Media Independent Interface (MII)
each port AL100A connected through standard interface. reception, received data (RXD) sampled rising edge receive clock (RX_CLK). Assertion receive data valid (RX_DV) signal will cause look start SFD. transmission, transmit data enable (TX_EN) signal asserted when first preamble nibble sent transmit data (TXD) lines. transmit data clocked rising edge transmit clock (TX_CLK). Prior transaction, AL100A will output thirty-two bits preamble signal. After preamble, "01" signal used indicate start frame. write operation, device will send "01" signal write operation. Following "01" write signal will 5-bit address device 5-bit register address. "10" turn around signal then used avoid contention during read transaction. After turn around, 16-bit data will written into register. After completion write transaction, line will high impedance state. read operation, AL100A will output "10" indicate read operation after start frame indicator. Following "10" read signal will 5-bit address device 5-bit register address. Then, AL100A will cease driving MDIO line, wait time. During this time, MDIO should high impedance state. device will then synchronize with next driven device, continue read bits data from register. detail timing requirements management signals described section "Timing Requirements." MDIO port disabled through port configuration register. This allows engineers 100Base-TX transceiver without auto-negotiation capability interconnect. this mode operation, communication with AL100A. Therefore, AL100A will assert link status soon initialization completed assumes connected operating specified operating duplex mode speed.
3.15 Management
AL100A supports transceiver management through serial MDIO signal lines. device provides modes management, master slave mode. master mode operation, AL100A controls operation modes link slave mode controls operating mode. 3.15.1 Management MDIO write operation, device will send "01" signal write operation. Following "01" write signal their will 5-bit address device 5-bit register address. "10" turn around signal then used avoid contention during read transaction. After turn around, 16-bit data will written into register then after completion write transaction, line will high impedance state.
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read operation, AL100A will output indicate read operation after start frame indicator. Following "10" read signal will 5-bit address device 5-bit register address. Then, AL100A will cease driving MDIO line, wait time. During this time, MDIO should high impedance state. device will then synchronize with next driven device, continue read 16-bit data from register. detail timing requirement management signals described section "Timing Requirement." 3.15.2 Management Master Mode master mode, AL100A will continuously poll status devices through serial management interface. device will also configure capability fields ensure proper operation link. configuration link automatic. link capability programmed AL100A through port configuration register. AL100A reads from standard IEEE registers determine auto-negotiated operating speed mode. there need manually operation mode because flow control cabling issues AL100A port operation mode through MDIO interface (see EEPROM section programming AL100A). 3.15.3 Management Slave Mode slave mode, controls programming operating mode. AL100A will continuously poll status devices through serial management interface determine operation mode link. This mode management very useful unmanaged switch. operating mode link changed programming mode through jumper. AL100A also supports 100Base-TX transceivers without MDIO interface interface. When MDIO disabled, AL100A will operate operation mode specified port configuration register (register 1C). 3.15.4 Non-Auto-negotiation Mode AL100A also turn auto-negotiation capability PHY. When auto-negotiation turned off, AL100A slave mode transceiver will determine link's operating mode. 3.15.5 Other Options Some Legacy Fast Ethernet devices other cost devices have auto-negotiation capability. those cases when transceiver will able perform auto-negotiation, switch transceiver will typically parallel detection update information transceiver's register. Unfortunately, such register addresses vendor specific. AL100A provides register (register specify register address AL100A read. AL100A will read from that register configure port operation accordingly. Register also provides some additional flexibility's some PHYs market. general, system designer should devices port port port Certain PHYs utilize address 00000 broadcast address. register
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allows AL100A start with address 01000. This provision allows engineers work around PHY's that have problems handling address 00000. Quad PHYs have 2-port ordering chip pinout, both clockwise counter clockwise. Register programs AL100A port order either direction. This provision enables engineers easily implement designs with PHY. There also slow MDIO clock KHz) available that capable handling high speed MDIO clock. some reason, transceiver connected device that device fails auto-negotiate, AL100A will default data rate duplex mode default setting port configuration register.
3.16 SGRAM Interface
ports AL100A work Store-And-Forward mode that ports support both Mbps Mbps data speed. AL100A utilizes central memory buffers pool, which shared ports within same device. After frame received, passed across SGRAM interface stored buffer. During transmit, frame retrieved from buffer pool forwarded destination port. AL100A designed Mbps SGRAM Mbps SGRAM cost performance. SGRAM accessed page burst access mode very high speed access. This burst mode repeatedly accessed same column. burst mode reaches column address, then wraps around first column address (=0) continues count until interrupted news read/write, pre-charge, burst stop command. AL100A will initialize SGRAM automatically. pre-charges banks inserts eight auto-refresh commands. will also program mode registers AL100A read write operations. SGRAM essentially SDRAM. Dynamic memories must refreshed periodically prevent data loss. SGRAM auto-refresh which also uses refresh address counters. SGRAM Auto-refresh command generates pre-charge command internally SGRAM. AL100A will insert auto-refresh command once every
3.17 EEPROM Interface
AL100A provides three functions with EEPROM interface: system initialization, obtaining system status, reconfiguring system real time. AL100A uses 24C02 serial EEPROM device (2048 bits organized bits 3.17.1 System Initialization EEPROM interface provided that manufacturer provide pre-configured system their customers which allows customers change reconfigure their system retain their preferences. EEPROM contains configuration initialization information, which will accessed power reset. reset held low, AL100A's EEPROM interface will into high impedance state. This feature very useful reprogramming EEPROM during installation reconfiguration.
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EEPROM reprogrammed external parallel port. reprogramming using parallel port, signal used hold RESET low. EEPROM interface will then high-impedance state. external device then program EEPROM through EEDIO EECLK pins. EEPROM address should 000. 3.17.2 Start Stop write cycle started start ended stop bit. start transition from high EEDIO when high. operation terminates when EEDIO goes from high when high (Figure Following start condition, writing device must output address EEPROM. most significant four EEPROM address device type identifier which address 1010. EEPROM device address should 000.
EECLK
EEDIO
START
Data Address Valid
Data Change
STOP
Figure
EEPROM Start Stop
EECLK output from AL100A while EEDIO bi-directional signal. When accessing EEPROM, reset held initialization AL100A must finished before writing operation begin. typical write operation shown Figure
Start
Device Address
Stop
8-Bit Word Address
8-Bit Data
Acknowledge
Acknowledge
Acknowledge
Figure
EEPROM Write Cycle
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3.17.3 Read Cycle Timing Read operations initiated same manner write operations, with exception that EEPROM address "1."
Device Address Device Address
Start
Start
Stop
8-Bit Word Address
8-Bit Data
EEDIO Acknowledge Acknowledge Acknowledge Acknowledge
Figure
EEPROM Random Read Cycle
3.17.4 Reprogramming EEPROM Configuration There ways that system reconfigured. Figure shows application using parallel interface reprogram EEPROM. this application, parallel port holds reset pins low, which forces EEDIO pins into high impedance. Once pins high impedance, EEPROM programmed parallel port. Once parallel port releases reset pins, devices will start download EEPROM data reconfigure devices. alternate reconfiguring system directly change register settings AL100A. After initialization, EEPROM interface virtual EEPROM. order this method work, EEPROM's device address must 000, while AL100A's address will 100. customer program AL100A EEPROM. read write timing same EEPROM. Because read well write AL100A, registers status read from AL100A. This will serve very useful tool diagnostic unmanaged switch.
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Reset AL100A
EECLK EEDIO EEPROM Parallel Port
AL100A
Reset EECLK EEDIO EEPROM
Reset AL100A
EECLK EEDIO EEPROM
Reset AL100A EECLK EEDIO EEPROM
Figure
Programming EEPROM with Parallel Port
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3.17.5 EEPROM Note: specific bits register referenced "X.Y" notation, where register number number. following table shows EEPROM address cross-referenced register/bit AL100A. Addresses through configuring device. They downloaded AL100A during reset power Address should programmed 0000 0001 0001 0100. address indicates last address entry. static address used switch, address should programmed. Addresses used programming static address entry. format address shown follows when YXXXXX represents: then XXXXX 5-bit individual port number; Y=1, then XXXXX either trunk port represented followed digit [trunk number, port represented 11ZZZ where don't care.
Address 00YXXXXX Address 72-73 Address [42:32] Address 74-75 Address [31:16] Address 76-77 Address [15:0]
Address Reserved
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Table AL100A EEPROM Mapping
EEPROM PHYSICAL ADDRESS 02-03 04-05 06-07 08-09 0A-0B 0C-0D 0E-0F 10-11 12-13 14-15 16-17 18-19 1A-1B 1C-1D 1E-1F 20-21 22-23 24-25 26-27 28-29 2A-2B 2C-2D 2E-2F 30-31 32-33 DESCRIPTION System Configuration [15:8] System Configuration [7:0] System Configuration System Configuration 0000 0001 0001 0100 Reserved Vendor Specific Snooping Port Configuration Monitored Host [47:32] Monitored Host [31:16] Monitored Host [15:0] Monitored Host [47:32] Monitored Host [31:16] Monitored Host [15:0] Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration AL100A REGISTER/BIT 00.15 00.8 00.7 00.0 01.15 01.0 02.15 02.0 03.15 03.0 04.15 04.0 05.15 05.0 06.15 06.0 07.15 07.0 08.15 08.0 09.15 09.0 0A.15 0A.0 0B.15 0B.0 0C.15 0C.0 0D.15 0D.0 0E.15 0E.0 0F.15 0F.0 10.15 10.0 11.15 11.0 12.15 12.0 13.15 13.0 14.15 14.0 15.15 15.0 16.15 16.0 17.15 17.0 18.15 18.0 19.15 19.0
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Table AL100A EEPROM Mapping (Continued)
34-35 36-37 38-39 3A-3B 3C-3D 3E-3F 40-41 42-43 44-45 46-47 48-49 4A-4B 4C-4D 4E-4F 50-51 52-53 54-55 56-57 58-59 5A-5B 5C-5D 5E-5F 60-61 62-63 64-65 66-67 68-69 6A-6B 6C-6D Port Configuration Port Configuration Port Configuration Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Reserved Checksum Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Reserved 2D.15 2D.0 2E.15 2E.0 2F.15 2F.0 30.15 30.0 31.15 31.0 32.15 32.0 33.15 33.0 34.15 34.0 1A.15 1A.0 1B.15 1B.0 1C.15 1C.0 1D.15 1D.0 1E.15 1E.0 1F.15 1F.0 20.15 20.0 21.15 21.0 22.15 22.0 23.15 23.0 24.15 24.0 25.15 25.0 26.15 26.0 27.15 27.0 28.15 28.0 29.15 29.0 2A.15 2A.0 2B.15 2B.0 2C.15 2C.0
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Table AL100A EEPROM Mapping (Continued)
70-71 72-73 74-75 76-77 78-7f 80-87 88-8f 90-97 98-9f A0-A7 A8-AF B0-B7 B8-BF C0-C7 C8-CF D0-D7 D8-DF E0-E7 E8-EF F0-F7 F8-FF Last Entry Address Static Entry (Port Number) Static Entry (MAC [47:32]) Static Entry (MAC [31:16]) Static Entry (MAC [15:0]) Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry
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Register Descriptions
Table Register Table Summary
REGISTER REGISTER DESCRIPTION System Configuration System Configuration System Configuration Reserved Testing Register Vendor Specific Status Port Monitoring Configuration Monitored Source Host [47:32] Monitored Source Host [31:16] Monitored Source Host [15:0] Monitored Destination Host [47:32] Monitored Destination Host [31:16] Monitored Destination Host [15:0] Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration
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Table Register Table Summary
Port Configuration Port Configuration Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Reserved Reserved Reserved Reserved
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Table Register Table Summary
System Status Register Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Indirect Resource Access Command Indirect Resource Access Data Indirect Resource Access Data Indirect Resource Access Data Indirect Resource Access Data Check
System Configuration Register (Register registers global system configuration registers. option selected this register affect overall system operation.
Table System Configuration Register (Register
NAME CPUprst FloodCtl DESCRIPTION This AL100A when detects EEPROM absent. device will assume present. Flooding control forwarding unicast frames with unknown destinations received from non-uplink ports. Disable. Frames received with unknown unicast destination address will forwarded ports (excluding receiving port) within VLANs specified receiving port. Enable. Frames received with unknown unicast destination address will forwarded uplink port specified receiving port. Security Enforcement. Security Off. security violation secured port will change port state. Security security violation secured port will change port into DISABLE state.
SecMgmt
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Table System Configuration Register (Register (Continued)
AgeEn Switch Table Entry Aging Control. Disable. table aging process will stopped. Enable. table aging process will running every dynamically learned table entries. Table Convergence Control. Disable. device will communicate with other devices about locally learned table entries. Enable. device will slow background process periodically transfer locally learned table entries other devices learn. Spanning Tree Protocol Enable Control. Disable. BPDU frames received from network ports will treated regular broadcast frames. Enable. BPDU frames received from network ports will forwarded only port. Port Incoming Frame Flow Monitoring Enable Cable. Disable. Enable. Port Outgoing Frame Flow Monitoring Enable Cable. Disable. Enable. This used AL100A when AL100A initialized CPU. indicates register file initialization completed CPU. Network Management Enable Control. Disable. device will generate events. Enable. device will generate events propagate onto ring. System Initialization Complete. This when initialization completed under initialization mode. unmanaged switch, this relevant. Interface. RMII Interface. Layer Trunk Loading Method. Port based loading. Trunking decisions will based trunk port assignment registers. address based loading. Trunking decisions will based source port addresses. Frame Time Enable. Device will timeout frames based MaxDelay. Device will timeout frames. Reserved factory use. Bits should
TCNVG
STPEN
PInMon
POutMon
CPUcfgrdy NetMgmt
InitDone
RMII L2Trunk
TimeoutEN
Reserved
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Table System Configuration Register (Register
15~8 NAME MaxAge MaxDelay DESCRIPTION Maximum dynamically learned entries. 0000 0000: sec. 1111 1111: sec. Maximum frame transition delay through switch. second seconds seconds seconds Maximum number broadcast frames that accumulated each input frame buffer. frames frames frames frames Disable. Device will perform IEEE standard exponential back algorithm when collision occurs. Enable. When collisions occur, AL100A will back slots. Retry Excessive Collision. Normal collision handling. Retry transmission after consecutive collisions. Select bits position address trunk assignment. Source Address [1:0] Source Address [3:2] Source Address [5:4] Source Address [7:6]
MaxStorm
SuperMAC
L2TbitSel
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Table System Configuration Register (Register
15~12 NAME Reserved RegPg SlowAge BpIPG84 Reserved (Must First Page. Second Page. Normal aging. Slow down aging. Backpressure Select Enable. 96BT. 64BT. Control. 96BT. 64BT. Back Pressure Port Rate (collision based). SGRAM Select. Mbps SGRAM. Mbps SGRAM. Back Pressure Control. Carrier based. Collision based. External Table Enable. Disable. Enable. Table Size Selection. Multicast/Broadcast Frame forward only. Flow control multicast. Flow control broadcast. DESCRIPTION
IPG64
PRate SG16M
BPCOL
ETEnb
ET16K
MCTrap FlowCtrlBC
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Reserved Register (Register This register reserved Allayer's use. bits should 0000 0001 0001 0100. Testing Register (Register This register reserved Allayer's use. bits should 0000 0000 0000 1000. Vendor Specific Register (Register This register used program vendor specific options. also used programming Vendor Specific register location location operation status.
Table Vendor Specific Register (Register
12~8 NAME PHYAD MCIkSpd PortOrder PHYOpReg PHYSpBit PHYDxModeBit DESCRIPTION Setting this will program MDIO address addresses Setting this will reduce MDIO clock speed 17HKz. Setting this will reverse ID/port number switch. PHY's Operation Status Register Number. PHY's Data Rate Status Register Number. PHY's Operating Duplex Mode Status Register Number.
Port Monitoring Configuration Register (Register This register configures port monitoring. sets monitored port snooping ports.
Table Port Monitoring Configuration Register (Register
14~10 NAME Reserved MdPID MgIPID MgOPID should Monitored Port Snooping Port incoming frame flow. Snooping Port outgoing frame flow. DESCRIPTION
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RMON Source Destination Registers (Registers These registers used RMON manager frame counting. RMON manager counts frames (destination) from (source) these addresses stored register. 48-bit address programmed three separate registers. Source address stored registers destination address register
Table RMON Source Destination Registers (Registers
REGISTER 15~0 15~0 15~0 NAME SRCMAC [47:32] SRCMAC [31:16] SRCMAC [15:0] DESCRIPTION Monitored Source Host Address. Monitored Source Host Address. Monitored Source Host Address.
Table RMON Source Destination Registers (Registers
REGISTER 15~0 15~0 15~0 NAME DSTMAC [47:32] DSTMAC [31:16] DSTMAC [15:0] DESCRIPTION Monitored Destination Host Address. Monitored Destination Host Address. Monitored Destination Host Address.
Port Configuration Registers (Registers Registers local port configuration. There port configurations port. port configuration Port uses register Port register etc.
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Port Configuration Register Uplink this six-bit link assign uplink port local port. uplink port three types; single port, trunk, port. uplink single port, format port [0][Dev_ID][Port_ID]. uplink trunk, then bits should read [100][trunk number]. trunk number numbered [Dev_ID][Trunk_ID]. local port uplink port, uplink should port frame with unlearned will then filtered.
Table Port Configuration Register
15~10 NAME UpLinkID DESCRIPTION Uplink associated with port. 0XXYYY: Port with device port 100XXN: Trunk with device trunk 111XXX: Port. Others: Reserved. Trunk Member Port. Individual Port. Member Trunk Port. should zero. Broadcast Storm Control Enable. Storm Control Disable. broadcast frame will throttled. Storm Control Enable. accumulated number broadcast frames input buffer port over threshold specified system configuration register, incoming broadcast frames will discarded until number been reduced below threshold. Intrusion Protection security control frames received from nonuplink ports. Security Off. forwarding decision made about frames received from port will involve source address checking. Security frames received from port with unknown source address with source address learned previously from another port will discarded. Port VLAN Membership. Non-member. Broadcast frames received from port will forwarded port. Member. Broadcast frames received from port will forwarded port addition other member ports specified VLAN register port (excluding source port). Learning Disable. Source Address from this port will learned. Source Address from this port will learned.
Tmember
Reserved StormCTL
Security
CPUOn
LrnDis
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Table Port Configuration Register (Continued)
PortST Port State Control. Disable. incoming frames from will discarded; outgoing frames will masked from path PHY. Blocking-N-Listening. incoming frames except incoming BPDUs from will discarded; outgoing frames except outgoing BPDUs will masked from path PHY. Learning. incoming frames from will learned about their source information; incoming frames except incoming BPDUs from will discarded after being learned; outgoing frames except outgoing BPDUs will masked from path PHY. Forwarding. incoming frames from will learned from their source information; incoming frames will forwarded based switch routing decision; outgoing frames will transmitted PHY. Reserved (Must
Reserved
Port Configuration Register FlowCtrlFdEn this selects 802.3x full duplex flow control. When this programmed, AL100A will automatically program pause capability auto-negotiation register. FlowCtrlHdEn this selects option backpressure half-duplex flow control. types backpressure selected system configuration register. MDIOCfg this selects management mode
0001: Selects Master Mode. When AL100A this mode, will capability advertisement register. link will auto-negotiate highest capability. 0010: Selects Slave Mode. When AL100A this mode, will capability advertisement register. link will auto-negotiate highest capability. 0111: Selects Forced Mode. When AL100A this mode, will turn auto-negotiation will select link's operating mode.
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Table Port Configuration Register
15~12 NAME Reserved FlowCtrlFdEn FlowCtrlHdEn MDIOCfg [3:0] Reserved Flow Control Full Duplex Enable. Flow Control Half Duplex Enable. MDIO Configuration. 0001: Master mode management. 0010: Slave mode management. 0111: Force mode. MDIO Disable. MDIO enabled. MIDO disabled. This relevant when MDIO enabled. When MDIO disabled, this forces port into link link down state. Link Down. Link Full Duplex Mode. Half Duplex Mode. Full Duplex Mode. Half Duplex Mode. DESCRIPTION
MDIODis
LinkUp
PrtMode100F PrtMode100H PrtMode PrtMode
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Port VLAN Registers (Registers These registers provide VLAN each port. VLAN worksheet provided Appendix
Table Port VLAN Registers (Registers
REGISTER Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 NAME DESCRIPTION Port VLAN corresponding port7~port0 device with Dev_ID Non-member port. Member port.
15~8
Dev3Map
Dev2Map
Port VLAN corresponding port7~port0 device with Dev_ID Non-member port. Member port.
15~8
Dev1Map
Port VLAN corresponding port7~port0 device with Dev_ID Non-member port. Member port.
Dev0Map
Port VLAN corresponding port7~port0 device with Dev_ID Non-member port. Member port.
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Port Trunk Port Assignment Registers (Registers Port Trunk Port assignment register assigns port trunk port-based load balancing trunking. Please example trunking section. port trunk port work sheet provided Appendix
PORT NUMBER REGISTER
Table Port Trunk Port Assignment Registers (Registers
15~14 NAME Trunk DESCRIPTION Trunk Port Trunk Port Port Port Port Trunk Port Trunk Port Port Port Port Trunk Port Trunk Port Port Port Port Trunk Port Trunk Port Port Port Port Trunk Port Trunk Port Port Port Port Trunk Port Trunk Port Port Port Port
13~12
Trunk
11~10
Trunk
Trunk
Trunk
Trunk
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Table Port Trunk Port Assignment Registers (Registers (Continued)
NAME Trunk DESCRIPTION Trunk Port Trunk Port Port Port Port Trunk Port Trunk Port Port Port Port
Trunk
Table System Status Register (Register
NAME EPTimeOut DESCRIPTION EEPROM Time Out. EEPROM initialized device. Device ready programmed CPU. EEPROM Checksum Error. SGRAM Initialization Done. SRAM Initialization Done. Register Initialization Done. Traffic Counter.
10~7
CheckSumEr SGRAMinit SRAMinit REGinit Traffic Counter Reserved Chip
0000: AL100A
Port Operation Status Registers (Register Registers status indication port basis. These read only register. Port port status register Port register 3B.and port register
Table Port Operation Status Registers (Register
NAME LinkFail Port Link Status. Normal Fail Port Status. Normal Error Port Security Violation. Normal Violation DESCRIPTION
PHYError
Sviolation
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Table Port Operation Status Registers (Register (Continued)
FlowCtrl Flow Control. port mode ([1:0]) 2'b01 2'b11: Pause Disable. Pause Enable. port mode ([1:0]) 2'b00 2'b10: Back Pressure Based CRS. Back Pressure Based Collision. Port Broadcast Storm Status. Normal Stormed Port Input Buffer Full Status. Normal Input buffer full experienced. Table Entry Unavailability Learning. Normal Unavailability experienced. Port Jabber Status. Normal Jabber experienced. Port Late Collision Status. Normal Late collision experienced. Port Transmit Pause Status. transmit pause experienced. Transmit pause experienced. Port Carrier Sense Loss During Transmission Status. carrier sense loss experienced. Carrier sense loss experienced. False Carrier Status. Transmit Queue Underflow Status. Normal Underflow Experienced. Frame Time Out. Normal Frame Time Experienced. Port Operating Mode. Half Duplex. Full Duplex. Half Duplex. Full Duplex.
Stormed
InBFull
TblUNAVL
Jabbered
LateCOL
TxPaused
CRSLoss
FalseCRS Underflow
TimeOut
PortMode
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Indirect Resource Access Command Register (Register indirect resource access command allows management (Reverse EEPROM Method) access other resources other than AL100A register values. registers, both internal external address tables, SGRAM contents accessed using this command.
Table Indirect Resource Access Command Register (Register
NAME CmdDone DESCRIPTION Command Done. Execute command. Command done. Clear this execute command. When finished with command, AL100A will back "1". Read/Write operation command. Read operation. Write operation. Type accessed resource. 000: registers. 001: EEPROM. 010: SGRAM. 011: address table Read: table address read. Write: address learn. 100: address table Read: address search. Write: address delete. 101-111: Reserved External address table read. ResType Operation On-chip address table read. Off-chip address table read. address entry within accessed resource.
Operation
13~11
ResType
ExtRD
ResAddr
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Indirect Resource Access Data Register (Register Indirect Resource Access Data through used with indirect resource access command.
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data
Table Check (Register
15~8 NAME CheckSum Reserved DESCRIPTION Checksum value AL100A register contents.
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Timing Requirements
Table Transmit Timing
SYMBOL ttdv ttxev DESCRIPTION TXCLK valid time. TXCLK TXEN valid time. UNIT
Table RMII Transmit Timing
SYMBOL ttdv ttxev DESCRIPTION TXCLK valid time. TXCLK TXEN valid time. UNIT
Note: Delays assuming 20pf loading output pins.
TXCLK
ttxev ttxev
TXEN
ttdv
DATA
DATA
DATA
DATA
DATA
DATA
Figure
Transmit Timing Diagram
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Table Receive Timing
SYMBOL trxds trxdh DESCRIPTION RX_DV, RXD, RX_ER, setup time. RX_DV, RXD, RX_ER hold time. UNIT
RXCLK
trxdh
RXDV
trxds trxdh
DATA
DATA
DATA
DATA
DATA
DATA
Figure
Receive Timing
Table Management (MDIO) Read Timing
SYMBOL DESCRIPTION high time. time. period. MDIO setup time. MDIO hold time. UNIT
MDIO
Figure
MDIO Read Timing
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Table Management (MDIO) Write Timing
SYMBOL DESCRIPTION high time. time. period. MDIO output delay. UNIT
MDIO
Figure
MDIO Write Timing
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Table Timing
SYMBOL troxs troxh DESCRIPTION Setup time. Hold time. UNIT
RICLK
troxh troxs
Figure
Timing
Table SGRAM Refresh Timing
SYMBOL tchi tckh tcks DESCRIPTION Access hold time. Access setup time. PBCS#, PBRAS#, PBWE# hold time. Clock high level width. System clock cycle time. hold time. setup time. Clock level width. PBCS#, PBRAS#, PBWE# setup time. Precharge command period. Auto refresh auto refresh period. UNIT
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PBCLK tCKS tCKH
tCHI
Command
Precharge
Auto Refresh
Auto Refresh
Active
BANK
BANK
Address
Don't Care
Figure
SGRAM Refresh Timing
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Table SGRAM Read Timing
SYMBOL tchi tckh tcks tras trcd DESCRIPTION Access time. Access hold time. Access setup time. PBCS#, PBRAS#, PBWE# hold time. Clock high level width. System clock cycle time. hold time. setup time. Clock level width. PBCS#, PBRAS#, PBWE# setup time. Data high impedance time. Data impedance time. Data hold time. Active precharge command period. Active read delay. UNIT
Note: This timing requirement SGRAM running Latency Typically speed grade SGRAM needs used.
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tCHI
PBCLK
tCKS
tCKH
BURST TERM.
Command
Active
READ
A0-A7
column
PBBA
BANK BANK
tRCD (Bank Latency
Dout
Dout
Dout
Dout
Dout
Dout
location within same
tRAS (Bank
Figure
SGRAM Read Timing
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Table SGRAM Write Timing
SYMBOL tchi tckh tcks tras trcd DESCRIPTION Access hold time. Access setup time. PBCS#, PBRAS#, PBWE# hold time. Clock high level width. System clock cycle time. hold time. setup time. Clock level width. PBCS#, PBRAS#, PBWE# setup time. Data hold time. Data setup time. Active precharge command period. Active read delay. 100,000 UNIT
Note: This timing requirement SGRAM running Latency Typically speed grade SGRAM needs used.
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tCHI
PBCLK
tCKS
tCKH
Command Active write BURST TERM.
A0-A7
column
BANK
PBBA
BANK
tRCD (Bank tRAS (Bank
Don't Care location within same Undefined
Figure
SGRAM Write Timing
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Electrical Specifications
Note: Operation absolute maximum ratings could cause permanent damage device.
Table Maximum Ratings
Supply Voltage (Vcc) Input Voltage Output Voltage Supply Voltage Input Voltage Output Voltage Storage Temperature -0.3V 3.6V -0.3 0.3V -0.3 0.3V -0.6V 6.0V -0.6 Vcc5 0.3V -0.6 Vcc5 0.3V +150
Table Recommended Operation Conditions
Supply Voltage Operating Temperature Power Dissipation 3.3V 0.3V (typical)
Table Electrical Characteristics
PARAMETER DESCRIPTION Output voltage-high, Ioh=4mA Output voltage-low, Ioh=4mA High impedance state output current Input current-high (With pull-up pull-down) Input current-low (With pull-up pull-down) Input high voltage Input voltage Supply current 0.7*Vcc 0.3*Vcc UNIT
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AL100A Mechanical Data
388-pin Package
1.62 35.20 34.80
31.75 1.27
0.56 1.17
30.20 29.80
0.90 0.60
0.51 Min.
Figure
AL100A Mechanical Dimensions
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Appendix (VLAN Mapping Work Sheet)
PORT 6/REG.
PORT
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PORT 7/REG.
PORT 0/REG.
PORT 1/REG.
PORT 2/REG.
PORT 3/REG.
PORT 4/REG.
PORT 5/REG.
AL100A Revision
Appendix (Port Trunk Port Assignment Work Sheet)
PORT 0/REG.
PORT 1/REG.
PORT 2/REG.
PORT 3/REG.
PORT 4/REG.
PORT 5/REG.
PORT 6/REG.
TRUNK PORT
BIT/ VALUE
TRUNK BITS TRUNK BITS
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PORT 7/REG.
AL100A Revision
Appendix (Suggested Memory Components)
Note: This only partial list memory components that used Allayer devices. AL100A uses Frame Buffer SGRAM chips that require 32-bit wide SGRAM SDRAM, faster with latency following table lists some available memory used AL100A.
DEVICE
FREQ.
Mbit SGRAM
Mbit SGRAM
AL100A
MoSys MG802C256Q-10 Etron EM635327Q-8
MoSys MG802C512L-8 Etron EM636227Q-8 Winbond W971632AF-8 Hitachi HM5216326FP-8
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Rev. History Prelim. (7/28/99) Reformatted edited document. Added memory table appendix III. Prelim. (9/22/99) ROCTL2 output table should AC21 AF21. Prelim (11/8/99) ROCTL1 output table should AF20 AC20. power interface table, pins should listed AC15. Added transmit receive diagrams. Corrected tables reflect transmit signals clocked rising edge TX_CLK. Prelim (12/2/99) DEVID0 should AC14 DEVID1 should AF13. They were reversed. power interface table, missing from 3.3V supply voltage. diagram RMII tables were added. Allayer's logo added. Prelim. Rev. (5/00) Fully released document.
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Index
Numerics Port Mbps Port Gbps Managed Switch with Address Aging Address Learning AL100A EEPROM Mapping AL100A Interface Block Diagram AL100A Mechanical Data AL100A Overview Appendix (VLAN Mapping Work Sheet) Appendix (Port Trunk Port Assignment Work Sheet) Appendix (Suggested Memory Components) Broadcast Storm Control Data Reception Electrical Characteristics EEPROM Interface EEPROM EEPROM Random Read Cycle EEPROM Start Stop EEPROM Write Cycle False Carrier Events Flow Control Frame Filtering Frame Forwarding Frame Generation Frame Transmission Functional Description Half Duplex Flow Control (Backpressure) Half Duplex Mode Operation Illegal Frame Length Indirect Resource Access Command Register (Register Indirect Resource Access Data Register (Register Load Balancing Long Frames Maximum Ratings MDIO Interface Media Independent Interface (MII) Interface Port Interface Port Interface Port Interface Port Interface Port Interface Port Interface Port Interface Port Receive Timing Transmit Timing Miscellaneous Pins Non-Auto-negotiation Mode Other Options Management Management (MDIO) Read Timing Management Master Mode Management MDIO Management Slave Mode Descriptions Diagram Port Based Trunk Load Balancing Port Configuration Register Port Configuration Register Port Configuration Registers (Registers Port Monitoring Port Monitoring Configuration Register (Register Port Operation Status Registers (Register Port Trunk Port Assignment Registers (Registers Port VLAN Registers (Registers Power Interface Product Description Programming EEPROM with Parallel Port Queue Management Read Cycle Timing Recommended Operation Conditions Reserved Register (Register RMII Transmit Timing RMON Source Destination Registers (Registers Timing Input Interface Interface Output Interface Secure Mode Operation SGRAM Interface SGRAM Read Timing SGRAM Refresh Timing SGRAM Write Timing Spanning Tree Support Start Stop Summary Programmable Control Transmit Receive Summary Programmable Options Address Learning Summary Programmable Registers System Block Diagram
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System Configuration Register (Register System Configuration Register (Register System Configuration Register (Register System Initialization Testing Register (Register Trunk Port Assignment Trunk Port Numbering Trunking (Port Aggregation) Uplink Port Vendor Specific Register (Register VLAN Port Switch VLAN Mapping Based Loading Trunk VLAN Mapping Port Based Load Balancing Trunk VLAN Support
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