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Numerical-Integration Techniques Speed Dual-Slope Conversion Auth


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AN788
Numerical-Integration Techniques Speed Dual-Slope Conversion
Author: Gary Grandbois Freeman, Microchip Technology, Inc. integrating converter integrates signal only certain time window, Figure shows. This limited integration period results normal-mode noise rejection only when integration period equal more periods noise signal (Figure 2a). time integral this noise over integer multiples noise period course, zero. Normal-mode noise-rejection performance thus represented function (Figure that reaches peaks fundamental harmonic frequencies period defined signal-integrate time minimum period which must equal noise period, been limiting factor conversion speed. 60Hz, example, minimum signal-integrate time 16.7msec; 50Hz, it's 20msec. Because signal-integrate time only portion total conversion time, conversion rates significantly less than 1/T. standard, high-performance, dual-slope converter includes reference deintegrate phase, typically long, autozero period equal signal-integrate period total conversion time thus which, 60Hz rejection, yields maximum conversion rate samples/sec; 50Hz, yields 12.5 samples/sec. most serious constraint arises when want offer instrument international that reject both 50Hz. This feature attainable only when signal-integrate period contain cycles 60Hz noise five cycles 50Hz noise. resulting 100msec signal-integrate period dictates conversion/sec rate.
using low-cost microprocessors program-controlled numerical-integration technique, achieve good noise rejection take full advantage higher speeds offered recently developed dual-slope converters such TC7109. This similar converters overcome speed limitations imposed logic-gate analog comparator delays earlier dual-slope devices, modern units operate rates high samples/sec. Nevertheless, operating them their maximum conversion rates often makes difficult impossible achieve high normal-mode line-frequency rejection that dual-slope converters inherently offer slower conversion rates. Thus, noise considerations have often precluded these converters their rated speeds especially industrial environments, where line-frequency other low-frequency noise components particular problem.
NORMAL-MODE LINE-FREQUENCY REJECTION
understand normal-mode line-frequency rejection dual-slope converters, consider typical 12-bit converter (Figure timing diagram (Figure conversion cycle. Note that conversion depends charging integrating capacitor during fixed time interval; number counts necessary discharge capacitor zero proportional input voltage.
Integrator
Analog Input
Comparator
Signal Integration Window
Zero Crossing Detected
Integrator Output
Reference Voltage
Switch Driver Phase Control Polarity Control Control Logic Clock
Integrate Phase 2048 Counts
Deintegrate Phase 4096 Counts
Number Counts Zero Crossing Proportional
Digital Output
12-Bit Counter
FIGURE dual-slope converter operates charging capacitor from input voltage during fixed time, then discharging zero. number clock periods discharge time corresponds analog input voltage. size integrating time window determines which normal-mode noise signals rejected.
2002 Microchip Technology, Inc. DS00788A-page
AN788
can, however, overcome inherent conversion-speed limitation integrating converters. microprocessor with program-controlled numerical integration that complements converter's analog integration will speed dual-slope conversion considerably. achieve high normal-mode rejection specific frequencies with this method three conditions met. First, signalintegrate period must defined such that noise integration takes place segmented basis. Figure example, integrate window opens noise-wave-form segment that's onethird period long. Next, second signal-integrate period must point corresponding exactly point which first ended, third's beginning must correspond point which second ended. This condition only converter fixed conversion time, irrespective signal input. Finally, microprocessor must three conversions achieve total integration cycle noise. consideration these constraints TC7109 converter, example, leads relationship: fNOISE
Signal-Integration Window
Measurement
Period
NORMAL MODE REJECTION (dB)
where conversion rate, noise frequency number conversion results added. must number; Figure shows cannot even number. frequency that would require even number samples which integrate window locked phase with signal (i.e., converter signal periods synchronized). (fNOISE) (X/4) Figure 3b), result times error conversion.
0.1/T
INPUT FREQUENCY
10/T
FIGURE dual-slope converter, high normal-mode noise rejection occurs when integration period multiple noise signal's period.
Noise Amplitude
(Int Conversion Rate
Noise Amplitude
(Int Conversion Rate
FIGURE Data-conversion systems employing numerical-integration technique furnish noise rejection when number samples summed (a). Adding results conversions, though, yield twice much error does conversion converter noise frequency synchronized.
DS00788A-page 2002 Microchip Technology, Inc.
AN788
NORMAL-MODE REJECTION (dB)
100msec Signal Integrate Samples Summed 11.1msec Sample 11.1msec Signal Integrate 6070
achieve desired normal-mode rejection, must, therefore, number converter results. accomplish this summation with firmware with user-interaction software. Consider example using TC7109 converter operating 22.5 samples/sec. equation yields results Table Table indicates, converter operating 22.5 samples/ reject harmonics 10Hz maintain rolling average nine samples. This technique rejects 60Hz; it's equivalent sample taken rate samples/sec. curves Figure show normal-mode rejection resulting from 9sample averages rate 22.5 conversions/sec sample conversions/sec). fNOISE (Fundamental) 12.8 TABLE TC67109 22.5 sample/sec. Samples Summed
NORMAL-MODE NOISE FREQUENCY (Hz)
FIGURE normal-mode-rejection capability illustrated upper curve here demonstrates effectiveness taking nine conversion samples; system that curve represents rejects noise multiples 10Hz. lower curve shows result acquiring only sample employing 11.11msec signalintegration period.
Notes: converter updates 22.5 conv/sec Display updates conv/sec Output average conversions Rejects both 60Hz Continuity buzzer responds 90msec conversions) Range changes 44msec
1.11M Range Switch Qaud SPST 101k 0.068µF 184kHz Clock 1-chip Microcomputer Data Port Display Drive
REF+
High Byte STATUS LBEN HBEN CE/LOAD STATUS LBEN HBEN CHIP ENABLE
TC7109
12-bit
Byte
0.12µF
Port Buzzer
FIGURE This 3/4-digit multimeter uses numerical-integration technique reject both 60Hz normal-mode noise. Although DMM's display updates samples/sec, conversions take place 22.5 samples/sec.
2002 Microchip Technology, Inc. DS00788A-page
AN788
What's point, ask, sampling higher rate must wait result during 9-period numerical integration? After first 9-period wait, system's pipeline full then obtain result each cycle 22.5 samples/sec rate. numerical-integration technique many practical applications. Figure circuit, example, digit that uses TC7109 13-bit converter. updates display sample/sec rate easy readability, converts 22.5 samples/sec rate fast response during autoranging continuity checking. Because circuit averages nine samples, rejects both 60Hz noise. Because carry rolling average, capable changing number conversions summed; therefore accommodate specific, user-programmable rejection frequencies. Figure shows connections system using TC7109 conjunction with 6502 processor 6522 peripheral interface adapter. adapter's programmable timer provides converter's clock, thereby simplifying testing noise rejection with different clock frequencies. This circuit allows evaluate numerical-integration-based designs using either generalpurpose µP-development system prototyping board. Figure shows assembly-language listing system; flowchart appears Figure TABLE 16-channel multiplexer. Channels Scanned
100k 10µF
VOUT
REF- REF+ TC7109 Converter STATUS RUN/HOLD SEND LBEN HBEN CE/LOAD MODE CAP+ CAPINT TEST
TC7660
10µF
100k 0.01µF Input Analog Input Input
0.15µF 0.33µF 200k
SY6522 Port
FIGURE evaluate numerical integration with circuit detailed this schematic. 6522 peripheral-interface adapted provides clocking interface dual-slope converter.
DS00788A-page 2002 Microchip Technology, Inc.
AN788
094D.ASM 000D 000D 000D 000D 000D 000D 000D 000D 000D A800 0080 0080 0083 0084 0280 0280 0282 0285 0288 028B 028D 0290 0293 0296 0298 029B 029E 029E 02B0 02B0 02B3 02B4 02B6 02B8 02B9 02BB 02BD 02BE 02C0 02C3 02C5 02C7 02C9 02CB 02CD 02CF 02D1 02D4 02D5 02D7 02DA 02DC 02DE 02E0 02E2 02E4 02E6 02E8 02EA 02EC 02ED SOFTWARE DEMONSTRATE NUMERICAL INTEGRATION USING TC7109 INTERFACED 6502 MICROPROCESSOR 6522 PORT RESULTS STORED 'RESLT' ZERO-PAGE MEMORY USER MUST PROVIDE INTERRUPT VECTOR FROM 6522'S INTERRUPT ROUTINE "INTSVC" ;-;SYSTEM EQUATES A800H ;ADDRESS 6522 PORT ;RESERVE ZERO-PAGE MEMORY ;16-BIT ACCUMULATOR RESULTS, BYTE SIGN ;STORAGE LOOP COUNTER ;SAVE HIGH BYTE 0280H ;SET PORT CONTROL TC7109 #0C0H ;PB6 OUTPUTS, IOPT TIMER OUTPUT IOPT+2 (FOR 7109 CLOCK) IOPT+0BH ;SQUARE WAVE OUTPUT PB-7 #12H ;LOAD CONSTANT IOPT+4 CLOCK TIMER SETREG ;ININTIALIZE MEMORY REGISTERS IOPT+5 START 7109 CLOCK #82H ;ENABLE INTERRUPT FROM IOPT+0EM 6522 INPUT MAINPRG ;I/O PORT SETUP COMPLET, JUMP O.S. MAIN PROGRAM ;INTERRUPT SERVICE ROUTINE 0280H IOPT ;GET HIGH BYTE ;SAVE #OFH ;ZERO MSBs ARITHMATIC STORHI ;SAVE ;GET SIGN BACK #10H ;ANALOG INPUT NEGATIVE? SUBTR YES, SUBTRACT ;RESULT POSITIVE RESLT ;GET BYTE THIS CONVERSION IOPT+1 PREVIOUS READINGS RESLT SAVE BYTE RESLT+1 ;GET BYTE CONVERSION STORHI RESLT+1 SAVE BYTE RESLT+2 ;GET SIGN CARRY BIT, RESLT+ SAVE LOOPCNT ;JUMP TEST CONVERSIONS ;SET CARRY SUBTRACTION RESLT POLARITY THIS CONVERSION IOPT+1 NEGATIVE, RESLT DOUBLE-PRECISION RESLT+1 SUBTRACTION STORHI RESLT+1 RESLT+2 RESLT+2 STORX ;HAVE DONE CONVERSIONS? DIVID YES, DIVIDE RETURN
Interrupt
RESLT STORX STORHI A9C0 CLOCK 8D00A8 8D02A8 8D0BA8 A912 8D04A8 20FA02 8D05A8 A982 8D0EA8 4C2303
10PT
Read High Byte
Strip Flags, Store Magnitude
Polarity Positive? Carry Subtraction
Clear Carry Addition
AD00A8 INTSVC 290F 8584 2910 F017 A580 6D01A8 8580 A581 6584 8581 A582 6900 8582 4CE802 SUBTR A580 ED01A8 8580 A581 E584 8581 A582 E900 8582 C683 LOOPCNT F001 PAGE
Subtract Conversion Magnitude from Total
Conversion Magnitude Total
Decrement Loop Counter
Have Nine Conv. Been Integrated?
Display Result Return from Interrupt
FIGURE This assembly-language listing converter system Figure provides 9-sample numerical integration, thereby eliminating normal-mode noise frequencies that multiples 10Hz.
FIGURE This flowchart Figure assembly-language routine summarizes code necessary control Figure evaluation circuit.
2002 Microchip Technology, Inc.
DS00788A-page
AN788
Adding Channels
using analog multiplexers, take advantage these speed-improvement techniques multichannel systems. Solving equation given earlier using determine scan length number channels), keep noise-segment alignment proper phase. This segmented approach (for 16channel system that requires summation three conversion) shown Figure scan length found dividing number available channels taking integer value, then multiplying adding Table shows relationship between number samples summed number channels scanned 16-channel multiplexer. data-acquisition system using 16-channel multiplexer could TC7109 running conversions/sec reject harmonics 20Hz (including, course, 60Hz), with 5-sample average taken microprocessor. system would still respond large signal deviations single conversion. change from analog signal integration noise hybrid analog/numerical integration entails some trade-offs. quantization error, example, always present; lead significant reduction normal-mode rejection noise period carved into many segments. addition, timing instability create other error sources. maximum stability, must control converter's timing with crystal oscillator.
Channel
Signal Integrate
Channel
Signal Integrate
Channel
Signal Integrate
Channel
Signal Integrate
Auto Zero fNOISE
Auto Deintegrate Zero
Deintegrate
Auto Zero
Auto Deintegrate Zero
Deintegrate
Segment Channel
Notes: Segments Channels Scanned Channel Multiplexer
Segment Channel
FIGURE multichannel capability enhanced-speed A/D-converter designs employing µP-based numerical integration.
DS00788A-page
2002 Microchip Technology, Inc.
Information contained this publication regarding device applications like intended through suggestion only superseded updates. your responsibility ensure that your application meets with your specifications. representation warranty given liability assumed Microchip Technology Incorporated with respect accuracy such information, infringement patents other intellectual property rights arising from such otherwise. Microchip's products critical components life support systems authorized except with express written approval Microchip. licenses conveyed, implicitly otherwise, under intellectual property rights.
Trademarks Microchip name logo, Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, MATE, SEEVAL Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode Total Endurance trademarks Microchip Technology Incorporated U.S.A. Serialized Quick Turn Programming (SQTP) service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2002, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved.
Printed recycled paper.
Microchip received QS-9000 quality system certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona July 1999. Company's quality system processes procedures QS-9000 compliant PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs microperipheral products. addition, Microchip's quality system design manufacture development systems 9001 certified.
2002 Microchip Technology Inc.
DS00788A page
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*DS00788A*
DS00788A-page
2002 Microchip Technology Inc.

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