AN763 Bulk Resistance Latch-Up Protection MOSFET Drivers
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AN763
Bulk Resistance
Latch-Up Protection MOSFET Drivers
INTRODUCTION
Most CMOS ICs, given proper conditions, "latch" (like SCR), creating short circuit from positive supply voltage ground. This application note explains this occurs what done prevent MOSFET drivers.
Drain P-Channel Parasitic
CONSTRUCTION CMOS
fabricating CMOS ICs, parasitic bipolar transistors formed by-product CMOS process (see Figure These transistors inherent CMOS structure can't eliminated. P-channel device parasitic N-channel parasitic Through internal connections, parasitics form four-layer structure (see Figure Figure parasitic turned Nchannel drain raised above This action will bias drain parasitic (Q1's emitter), back through base return through bulk resistance similar situation occur drain N-channel MOSFET (emitter taken below supply.
Input from Previous Stage
P-Well Resistance
N-Channel Parasitic Drain Source
FIGURE
Equivalent Circuit.
This emitter base junction parasitic bipolar parasitic diode that also found power MOSFETs. these diodes exists every CMOS structure both P-channel devices. This corresponds with fact that there exists parasitic bipolar every MOSFET including input transistors. Turn them action will occur. most applications, triggering parasitic results destruction only time destruction does occur when supply current device limited. this case, device will resume normal operation when parasitic unlatched cycling supply current through zero.
Output
PREVENTING TRIGGERING
Grounds
Clean grounds important system, they especially important analog power processing circuits, becoming even more critical when CMOS used. Poor ground practice result device latching. example this shown Figure this example, source sends TC426 "low" signal which causes power MOSFET turn "on". ground return resistance (R1) sufficiently high, ground voltage TC426 will rise above that source, resulting input TC426 being negatively biased will cause TC426 latch. similar condition caused circuit inductance. Referring Figure assume replaced inductor. When MOSFET turns "on", current source lead builds very rapidly. Typical rise times would about nsec nsec.
P-Well
P-Channel
N-Channel
FIGURE
Output Stage Layout.
2003 Microchip Technology Inc.
DS00763B-page
AN763
example, assume that MOSFET switching circuit inductance From di/dt, generate voltage shifts 0.83V 1.66V, depending upon rise time, which more than enough trigger parasitic SCR. Troubleshooting this type problem facilitated placing series resistor, typically 100, between TC426 MOSFET gate. This slows MOSFET's transition circuit observed operation without anything being destroyed. sure take into account increased dissipation MOSFET when using this technique.
TC426
(Top View)
FIGURE
Improper Layout.
Source
TC426 TC426
Trace Resistance
Power Supply Return
FIGURE
Improper Ground.
(Top View) Power Supply Return
Figure Figure show proper "star" ground that will prevent latching. Notice grounds meet only point. board, this means traces must meet point, that they connected same trace (Figure Figure show this mistake).
FIGURE
Proper Layout.
DECOUPLING
Ripple noise power supply voltage another source latch-up problems. properly decoupled power supply, supply pins voltage transients occur. These transients generated combination fast peak currents being drawn parasitic inductances resistances power supply conductors (see Figure Figure This problem very pronounced with driving large loads, case TC426 TC429 driving power MOSFET. Upon switching, TC429 draw several amperes current from supply, causing large transients local supply voltage. TC429's input very close system supply voltage, when being driven CMOS logic, local supply drop significantly below input, triggering parasitic SCR. parasitic very fast this transition need last only nanoseconds latching occur.
TC426
Source
Star Ground From Power Supply Return
FIGURE
Proper Ground.
DS00763B-page
2003 Microchip Technology Inc.
AN763
Although lowering input voltage will help spikes that occur, they cause other same power supply suffer noise immunity problems from noise generated driver some applications, such portable instrumentation, desirable keep total power consumption minimum designers will commonly shut power unused portions system conserve battery life. This cause problems when input signal always present even though line turned "off". this case, resistor series with CMOS device's input will limit injected current value below that listed device data sheet "the maximum current into pin". When subsequently switched "on", action will prevented.
Trace Decoupling Capacitor
Trace
TC426
Decoupling Capacitor
Trace
DIODES
very reliable method preventing parasitic action guard susceptible pins with steering diodes. This most commonly done when MOSFET driver driving inductive load, such long length wire pulse transformer. Placing reverse-biased diode between each supply rail input/output pins shown Figure Figure limits applied voltage swing more than supply voltage plus forward voltage drop clamping diode. this reason, Schottky diodes usually best choice this technique, their forward voltage drop less than parasitic SCR's base emitter drop temperature. PhilipsTM/ MullardTM/AmperexBYV10-30, example, will work well higher-power applications, such MOSFET drivers. BAT54 dual diode works well surface-mount applications with lower power ICs, such operational amplifiers converters.
Trace
Capacitor
FIGURE TC426 Traces (Equivalent Circuit). TC426
Decoupling Capacitor
FIGURE
Typical Layout (TC426).
Aggravating this temperature dependence parasitic transistors. Their base emitter voltage decreases mV/°C temperature increases, making them increasingly more sensitive transients chip temperature rises. Many times system, which performed admirably bench, begins experience problems high temperatures because local decoupling marginal. obvious solution properly decouple supply that can't drop below value input signal. second, less obvious, solution reduce logic level applied input device.
TC913
FIGURE
TC913 with Diode Clamps.
2003 Microchip Technology Inc.
DS00763B-page
AN763
CONCLUSION
Latch-up CMOS preventable. Simple circuit techniques attention system design details will ensure that CMOS' full potential realized operating environments. Designers also look forward day, distant future, when even these simple precautions will longer necessary.
TC429
Source
Synopsis
prevent latch-up: Properly decouple Clamp outputs with diodes when driving inductive loads. Clamp inputs with diodes input signal exceeds negative positive rails power supply. star grounds, possible, highcurrent applications.
FIGURE Transformer.
TC429's
Driving
Pulse
Germanium diodes, such 1N270, will work well also, leaky some applications. Standard signal diodes, 1N4148 1N914, example, frequently used. Their larger junctions having lower effective forward drop than parasitic junctions work effectively over/under voltage clamps. some instances where standard junction diodes leaky (such might case Figure 10), very leakage junction (JFET) acting diode will trick. These devices have leakage picoamps very quick responding. these applications, contact Microchip Technology Inc.
RESISTORS
applications where triggering parasitic concern protecting from destruction only issue, adding resistor series with power supply will prevent device destruction. Once been triggered, supply voltage will have brought momentarily zero reset SCR, damage will have been done unless series resistor large enough limit fault current safe value. This lowest cost solution prevent device damage. Using resistor limitations, however. resistor will limit current allowed decoupling capacitor, which limits frequency that circuit driven value. This method works very well circuits, op-amps draw very little peak current circuit only amplifying component problems.
DS00763B-page
2003 Microchip Technology Inc.
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