SYNCHRONOUS DRAM MODULE JEDEC pinout 100-pin, dual in-line memory
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SDRAM DIMM
SYNCHRONOUS DRAM MODULE
JEDEC pinout 100-pin, dual in-line memory module (DIMM) Utilizes SDRAM components Single +3.3V ±0.3V power supply Fully synchronous; signals registered positive edge system clock Internal pipelined operation; column address changed every clock cycle Internal banks hiding access/precharge Programmable burst lengths: full page Auto Precharge Auto Refresh Modes Self Refresh Mode 64ms, 4,096-cycle refresh LVTTL-compatible inputs, outputs clocks Serial presence-detect (SPD) One-clock WRITE recovery (tWR) version; two-clock (tWR) supported
MT4LSDT232U
latest data sheet revisions, please refer Micron site:
ASSIGNMENT (Front View) 100-Pin DIMM
OPTIONS
Package 100-pin DIMM (gold) Timing 10ns cycle (100 clock rate)
MARKING
SDRAM COMPONENT TIMING PARAMETERS
SPEED GRADE CLOCK FREQUENCY ACCESS TIME 7.5ns SETUP TIME HOLD TIME
(READ) latency
FRONT DQMB0#
FRONT CKE0 DQMB2# DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
BACK DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB1# RAS# CAS# (CK1)
BACK (CKE1) (S1#) (S3#) DQMB3# DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
PART NUMBER
PART NUMBER MT4LSDT232UG-10_ CONFIGURATION DEVICE PACKAGE TSOP
NOTE: Symbols parentheses used this module used other modules this product family. They reference only.
NOTE: part numbers with two-place code (not shown), designating component revisions. Consult factory current revision codes. Example: MT4LSDT232UG-10C1.
SDRAM DIMM ZM04.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMM
GENERAL DESCRIPTION
MT4LSDT232U high-speed CMOS, dynamic random-access memory organized configuration. This module uses SDRAMs that configured dual memory arrays with synchronous interface (all signals registered positive edge clock signal CK0). READ WRITE accesses SDRAM module burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select bank accessed (BA0 selects bank; A0-A10 select row). address bits registered coincident with READ WRITE command used select starting column location burst access. module provides programmable READ WRITE burst lengths locations, full page, with burst terminate option. AUTO PRECHARGE function enabled provide self-timed precharge that initiated burst sequence. module uses internal pipelined architecture achieve high-speed operation. This architecture compatible with rule prefetch architectures, also allows column address changed every clock cycle achieve high-speed, fully random access. Precharging bank while accessing alternate bank will hide PRECHARGE cycles provide seamless, high-speed, random-access operation. module designed operate 3.3V, low-power memory systems. auto refresh mode provided, along with power-saving, power-down mode. inputs outputs LVTTL-compatible. SDRAM modules offer substantial advances DRAM operating performance, including ability synchronously burst data high data rate with automatic columnaddress generation, ability interleave between internal banks order hide precharge time capability randomly change column addresses each clock cycle during burst access. more information regarding SDRAM operation, refer 16Mb: SDRAM data sheet.
SERIAL PRESENCE-DETECT OPERATION
This module incorporates serial presence-detect (SPD). function implemented using 2,048-bit EEPROM. This nonvolatile storage device contains bytes. first bytes programmed Micron identify module type various SDRAM organizations timing parameters. remaining bytes storage available customer. System READ/WRITE operations between master (system logic) slave EEPROM device (DIMM) occur standard using DIMM's (clock) (data) signals, together with SA(2:0), which provide eight unique DIMM/ EEPROM addresses.
SDRAM DIMM ZM04.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMM
CLOCK DATA CONVENTIONS Data states line change only during LOW. state changes during HIGH reserved indicating start stop conditions (Figures START CONDITION commands preceded start condition, which HIGH-to-LOW transition when HIGH. device continuously monitors lines start condition will respond command until this condition been met. STOP CONDITION communications terminated stop condition, which LOW-to-HIGH transition when HIGH. stop condition also used place device into standby power mode. ACKNOWLEDGE Acknowledge software convention used indicate successful data transfers. transmitting device, either master slave, will release after transmitting eight bits. During ninth clock cycle, receiver will pull line acknowledge that received eight bits data (Figure device will always respond with acknowledge after recognition start condition slave address. both device WRITE operation have been selected, device will respond with acknowledge after receipt each subsequent eight-bit word. read mode device will transmit eight bits data, release line monitor line acknowledge. acknowledge detected stop condition generated master, slave will continue transmit data. acknowledge detected, slave will terminate further data transmissions await stop condition return standby power mode.
DATA STABLE DATA CHANGE DATA STABLE
Figure DATA VALIDITY
START
STOP
Figure DEFINITION START STOP
from Master
Data Output from Transmitter
Data Output from Receiver Acknowledge
Figure ACKNOWLEDGE RESPONSE FROM RECEIVER
SDRAM DIMM ZM04.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMM
FUNCTIONAL BLOCK DIAGRAM MT4LSDT232U (8MB)
DQMB0 DQMB1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
RAS# CAS# CKE0 A0-A10
RAS#: SDRAMs U0-U3 CAS#: SDRAMs U0-U3 CKE0: SDRAMs U0-U3 A0-A10: SDRAMs U0-U3 SDRAMs U0-U3
SDRAMs U0-U3 SDRAMs U0-U3
10pF
NOTE: resistor values ohms. U0-U3 MT48LC2M8A1 SDRAMs
SDRAM DIMM ZM04.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMM
DESCRIPTIONS
NUMBERS SYMBOL WE#, RAS#, CAS# TYPE Input Input DESCRIPTION Command Inputs: WE#, RAS# CAS# (along with S0#, S2#) define command being entered. Clock: driven system clock. SDRAM input signals sampled positive edge also increments internal burst counter controls output registers. Clock Enable: CKE0 activates (HIGH) deactivates (LOW) signal. Deactivating clock provides POWER-DOWN SELF REFRESH operation (all banks idle) CLOCK SUSPEND operation (burst access progress). CKE0 synchronous except after device enters power-down self refresh modes, where CKE0 becomes asynchronous until after exiting same mode. input buffers, including CK0, disabled during powerdown self refresh modes, providing standby power. Chip Select: enable (registered LOW) disable (registered HIGH) command decoder. commands masked when registered HIGH. considered part command code. Input/Output Mask: DQMB input mask signal WRITE accesses output enable signal READ accesses. Input data masked when DQMB sampled HIGH during WRITE cycle. output buffers placed High-Z state (after two-clock latency) when DQMB sampled HIGH during READ cycle. Bank Address: defines which bank ACTIVE, READ, WRITE PRECHARGE command being applied. also used program 12th mode register. Address Inputs: A0-A10 sampled during ACTIVE command (row-address A0-A10) READ/WRITE command (column-address A0-A8, with defining AUTO PRECHARGE) select location memory array respective bank. sampled during PRECHARGE command determine both banks precharged (A10 HIGH). address inputs also provide op-code during LOAD MODE REGISTER command. Data I/O: Data bus.
CKE0
Input
S0#,
Input
DQMB0-DQMB3
Input
Input
13-18, 63-67
A0-A10
Input
2-5, 7-10, 38-41, 43-46, 52-55, 57-60, 88-91, 93-96
DQ0-DQ31
Input/ Output Supply
Power Supply: +3.3V ±0.3V.
SDRAM DIMM ZM04.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMM
DESCRIPTIONS (continued)
NUMBERS SYMBOL TYPE Supply Input/Output Ground. Serial Presence-Detect Data: bidirectional used transfer addresses data into data presence-detect portion module. Serial Clock Presence-Detect: used synchronize presence-detect data transfer from module. Presence-Detect Address Inputs: These pins used configure presence-detect device. Reserved Future Use: These pins should left unconnected. Use: This connected this module assigned compatible DRAM version. DESCRIPTION
Input
98-100
SA0-SA2
Input
SDRAM DIMM ZM04.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMM
SERIAL PRESENCE-DETECT MATRIX
BYTE 36-61 NOTE: DESCRIPTION NUMBER BYTES USED MICRON TOTAL NUMBER MEMORY BYTES MEMORY TYPE NUMBER ADDRESSES NUMBER COLUMN ADDRESSES NUMBER BANKS MODULE DATA WIDTH MODULE DATA WIDTH (continued) MODULE VOLTAGE INTERFACE LEVELS SDRAM CYCLE TIME (CAS LATENCY SDRAM ACCESS FROM CLOCK (CAS LATENCY MODULE CONFIGURATION TYPE REFRESH RATE/TYPE SDRAM WIDTH (PRIMARY SDRAM) ERROR CHECKING SDRAM DATA WIDTH MIN. CLOCK DELAY FROM BACK-TO-BACK RANDOM COLUMN ADDRESSES BURST LENGTHS SUPPORTED NUMBER BANKS SDRAM DEVICE LATENCIES SUPPORTED LATENCY LATENCY SDRAM MODULE ATTRIBUTES SDRAM DEVICE ATTRIBUTES: GENERAL SDRAM CYCLE TIME (CAS LATENCY SDRAM ACCESS FROM (CAS LATENCY SDRAM CYCLE TIME (CAS LATENCY SDRAM ACCESS FROM (CAS LATENCY MINIMUM PRECHARGE TIME MINIMUM ACTIVE ACTIVE MINIMUM RAS# CAS# DELAY MINIMUM RAS# PULSE WIDTH MODULE BANK DENSITY COMMAND/ADDRESS SETUP COMMAND/ADDRESS HOLD DATA SIGNAL INPUT SETUP DATA SIGNAL INPUT HOLD RESERVED BYTES ENTRY (VERSION) SYMBOL BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 SDRAM LVTTL NONPARITY 15.6µs/SELF NONE PAGE NONBUFFERED
tCCD
tRRD tRCD tRAS tAS,tCMS tAH,tCMH
"1"/"0": Serial Data, "driven HIGH"/"driven LOW."
SDRAM DIMM ZM04.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMM
SERIAL PRESENCE-DETECT (contined)
BYTE 65-71 DESCRIPTION REVISION CHECKSUM BYTES 0-62 MANUFACTURER'S JEDEC CODE MANUFACTURER'S JEDEC CODE (CONT.) MANUFACTURING LOCATION ENTRY (VERSION) SYMBOL BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 REV. MICRON
73-90
MODULE PART NUMBER (ASCII) IDENTIFICATION CODE
95-98 99-127 NOTE:
IDENTIFICATION CODE (CONT.) YEAR MANUFACTURE WEEK MANUFACTURE MODULE SERIAL NUMBER MANUFACTURE SPECIFIC DATA (RSVD)
"1"/"0": Serial Data, "driven HIGH"/"driven LOW." Variable Data.
SDRAM DIMM ZM04.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMM
COMMANDS
Truth Table provides quick reference available commands. more detailed description commands operations, refer 16Mb: SDRAM data sheet.
TRUTH TABLE Commands DQMB Operation
(Notes: NAME (FUNCTION) COMMAND INHIBIT (NOP) OPERATION (NOP) ACTIVE (Select bank activate row) READ (Select bank column, start READ burst) WRITE (Select bank column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate bank banks) AUTO REFRESH SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output enable Write Inhibit/Output High-Z RAS# CAS# DQMB ADDR Bank/Row Bank/Col Bank/Col Code Op-code Valid Active Active High-Z NOTES
NOTE: HIGH commands shown except SELF REFRESH. A0-A10 define op-code written Mode Register. A0-A10 provide address determines which bank made active (BA0 Bank HIGH Bank A0-A8 provide column address; HIGH enables auto precharge feature (nonpersistent), while disables auto precharge feature; determines which bank being read from written (BA0 Bank HIGH Bank LOW: determines which bank being precharged (BA0 Bank HIGH Bank HIGH: both banks precharged "Don't Care." This command AUTO REFRESH HIGH, SELF REFRESH LOW. Internal refresh counter controls addressing; inputs I/Os "Don't Care" except CKE. Activates deactivates during WRITEs (zero-clock delay) READs (two-clock delay).
SDRAM DIMM ZM04.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMM
Address
Table BURST DEFINITION
Burst Length Starting Column Order Accesses Within Burst Address Type Sequential Type Interleaved 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
Mode Register (Mx)
Reserved*
Mode
Latency
Burst Length
*Should program M11, ensure compatibility with future devices.
Burst Length Reserved Reserved Reserved Full Page Reserved Reserved Reserved Reserved
Burst Type Sequential Interleaved
Latency Reserved Reserved Reserved Reserved Reserved
Full Page (512)
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 A0-A8 (location 0-511)
Supported
NOTE:
M6-M0 Defined
Operating Mode Standard Operation other states reserved
Write Burst Mode Programmed Burst Length Single Location Access
Figure MODE REGISTER DEFINITION
burst length two, A1-A8 select block-oftwo burst; selects starting column within block. burst length four, A2-A8 select block-offour burst; A0-A1 select starting column within block. burst length eight, A3-A8 select block-ofeight burst; A0-A2 select starting column within block. full-page burst, full selected, A0-A8 select starting column. Whenever boundary block reached within given sequence above, following access wraps within block. burst length one, A0-A8 select unique column accessed, mode register ignored.
SDRAM DIMM ZM04.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMM
ABSOLUTE MAXIMUM RATINGS*
Voltage Supply Relative +4.6V Voltage Inputs, Pins Relative +4.6V Operating Temperature, (ambient) +70°C Storage Temperature (plastic) -55°C +125°C Power Dissipation *Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS
(Notes: (VDD +3.3V ±0.3V) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs INPUT LEAKAGE CURRENT: input (All other pins under test OUTPUT LEAKAGE CURRENT: disabled; VOUT OUTPUT LEVELS: Output High Voltage (IOUT -2mA) Output Voltage (IOUT 2mA) RAS#, CAS#, A0-A10, BA0, WE#, CK0, CKE0 S0#, S2#, DQMB0-DQMB3 DQ0-DQ31 SYMBOL -0.5 UNITS NOTES
SPECIFICATIONS CONDITIONS
(Notes: (VDD +3.3V ±0.3V) PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN); latency 15ns STANDBY CURRENT: Power-Down Mode; 15ns; LOW; banks idle STANDBY CURRENT: Active Mode; S0#, HIGH; HIGH; 15ns; banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; 15ns; banks active; latency AUTO REFRESH CURRENT: (MIN); latency HIGH; S0#, HIGH; 15ns SELF REFRESH CURRENT: 0.2V SYMBOL ICC1 SIZE UNITS NOTES
ICC2 ICC3
ICC4 ICC5 ICC6
SDRAM DIMM ZM04.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMM
CAPACITANCE
PARAMETER Input Capacitance: A0-A10, BA0, RAS#, CAS#, WE#, CK0, CKE0 Input Capacitance: S0#, Input Capacitance: DQMB0#-DQMB7# Input Capacitance: SCL, SA0-SA2 Input/Output Capacitance: DQ0-DQ31, SYMBOL UNITS NOTES
SDRAM COMPONENT* ELECTRICAL CHARACTERISTICS
(Notes:
CHARACTERISTICS PARAMETER Access time from (positive edge) Address hold time Address setup time high-level width low-level width Clock cycle time hold time setup time CS#, RAS#, CAS#, WE#, hold time CS#, RAS#, CAS#, WE#, setup time Data-in hold time Data-in setup time Data-out high-impedance time Data-out low-impedance time Data-out hold time ACTIVE PRECHARGE command period AUTO REFRESH ACTIVE ACTIVE command period ACTIVE READ WRITE delay Refresh period (4,096 cycles) PRECHARGE command period ACTIVE bank ACTIVE bank command period Transition time WRITE recovery time Exit SELF REFRESH ACTIVE command *Specifications SDRAM components used module. SYMBOL tCKH tCKS tCMH tCMS tRAS tRCD tREF tRRD
tXSR
120,000
UNITS
NOTES
SDRAM DIMM ZM04.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMM
FUNCTIONAL CHARACTERISTICS
(Notes:
PARAMETER READ/WRITE command READ/WRITE command clock disable power-down entry mode clock enable power-down exit setup mode input data delay data mask during WRITEs data high-impedance during READs WRITE command input data delay Data-in ACTIVATE command Data-in precharge Last data-in BURST STOP command Last data-in READ/WRITE command Last data-in PRECHARGE command LOAD MODE REGISTER command ACTIVE REFRESH command Data-out high-impedance from PRECHARGE command SYMBOL tCCD tCKED tPED tDQD tDQM tDQZ tDWD tDAL tDPL tBDL tCDL tRDL tMRD tROH tROH tROH UNITS NOTES
SDRAM DIMM ZM04.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMM
SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS
(Notes: (VDD +3.3V ±0.3V) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs OUTPUT VOLTAGE: IOUT INPUT LEAKAGE CURRENT: OUTPUT LEAKAGE CURRENT: VOUT STANDBY CURRENT: 0.3V; other inputs 3.3V +10% POWER SUPPLY CURRENT: clock frequency SYMBOL UNITS NOTES
SERIAL PRESENCE-DETECT EEPROM ELECTRICAL CHARACTERISTICS
(Notes: (VDD +3.3V ±0.3V)
PARAMETER/CONDITION data-out valid Time must free before transition start Data-out hold time fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant SCL, inputs Clock period rise time clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time SYMBOL tBUF tHD:DAT tHD:STA tHIGH tLOW tSCL tSU:DAT tSU:STA tSU:STO tWRC UNITS NOTES
SDRAM DIMM ZM04.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMM
NOTES
voltages referenced VSS. This parameter sampled. +3.3V; MHz. dependent output loading cycle rates. Specified values obtained with minimum cycle time outputs open. Enables on-chip refresh address counters. minimum specifications used only indicate cycle time which proper operation over full temperature range (0°C 70°C) ensured. initial pause 100µs required after power-up, followed AUTO REFRESH commands, before proper device operation ensured. AUTO REFRESH command wake-ups should repeated time tREF refresh requirement exceeded. characteristics assume 1ns. addition meeting transition rate specification, clock must transit between between VIH) monotonic manner. Outputs measured 1.5V with equivalent load:
50pF
defines time which output achieves open circuit condition; reference VOL. last valid data element will meet before going High-Z. timing tests have with timing referenced 1.5V crossover point. Other input signals allowed transition more than once 30ns period otherwise valid levels. specifications tested after device properly initialized.
Timing actually specified tCKS; clock(s) specified reference only minimum cycle rate. Timing actually specified plus tRP; clock(s) specified reference only minimum cycle rate. Timing actually specified tWR. Required clocks specified JEDEC functionality dependent timing parameter. current will decrease latency reduced. This fact that maximum cycle rate slower latency reduced. Address transitions average transition every 30ns. must toggled minimum times during this period. Based -10. EEPROM WRITE cycle time (tWRC) time from valid stop condition write sequence EEPROM internal erase/program cycle. During WRITE cycle, EEPROM interface circuit disabled, remains HIGH pull-up resistor, EEPROM does respond slave address. recommended that DRAM controller clocks support future design requirements. overshoot: (MAX) pulse width 10ns, pulse width cannot greater than third cycle rate. undershoot: (MIN) pulse width 10ns, pulse width cannot greater than third cycle rate. clock frequency must remain constant during access precharge states (READ, WRITE, including tWR, PRECHARGE commands). used reduce data rate. Auto precharge mode only. Precharge mode only. JEDEC specifies three clocks.
SDRAM DIMM ZM04.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMM
EEPROM
tLOW
tHIGH
SU:STA HD:STA HD:DAT SU:DAT SU:STO
,,,,,,
tBUF
SYMBOL tHIGH tLOW tSU:DAT tSU:STA tSU:STO
UNDEFINED
SERIAL PRESENCE-DETECT EEPROM TIMING PARAMETERS
SYMBOL tBUF tHD:DAT tHD:STA UNITS UNITS
SDRAM DIMM ZM04.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMM
100-PIN DIMM DF-22
3.557 (90.34) 3.545 (90.04) .125 (3.18)
.079 (2.00) (2X)
1.255 (31.88) 1.245 (31.62)
.118 (3.00) (2X) .118 (3.00)
.700 (17.78)
.118 (3.00)
.250 (6.35) .039 (1.00) R(2X)
.128 (3.25) (2X) .118 (3.00) .039 (1.00) .050 (1.27)
.054 (1.37) .046 (1.17)
2.850 (72.39)
NOTE:
dimensions inches (millimeters) typical where noted.
8000 Federal Way, P.O. Boise, 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron registered trademark Micron Technology, Inc.
SDRAM DIMM ZM04.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
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