SYNCHRONOUS DRAM MODULE PC100-compliant; includes CONCURRENT AUTO
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SDRAM DIMMs
SYNCHRONOUS DRAM MODULE
PC100-compliant; includes CONCURRENT AUTO PRECHARGE JEDEC-standard, 168-pin, dual in-line memory module (DIMM) Nonbuffered ECC-optimized pinout 16MB 32MB Single +3.3V ±0.3V power supply Fully synchronous; signals registered positive edge system clock Internal pipelined operation; column address changed every clock cycle Internal banks hiding access/precharge Programmable burst lengths: full page Auto Precharge Auto Refresh Modes Self Refresh Mode 64ms, 4,096-cycle refresh LVTTL-compatible inputs outputs Serial presence-detect (SPD)
MT9LSDT272A, MT18LSDT472A
latest data sheet revisions, please refer Micron site:
ASSIGNMENT (Front View) 168-Pin DIMM
OPTIONS
Package 168-pin DIMM (gold) Frequency/CAS Latency MHz/CL (8ns SDRAMs) MHz/CL (10ns SDRAMs) Component Revision Designator Alpha character
MARKING
-10B -662
Factory Defined
Printed Circuit Board Revision Designator Numeric character Factory Defined
SDRAM COMPONENT TIMING PARAMETERS
MODULE MARKING -10B -662 SPEED GRADE LATENCY ACCESS TIME SETUP TIME HOLD TIME
SYMBOL SYMBOL DQMB2 DQMB3 DQ16 DQ10 DQ17 DQ11 DQ18 DQ12 DQ19 DQ13 DQ20 DQ14 DQ15 CKE1* DQ21 DQ22 DQ23 DQ24 DQMB0 DQ25 DQMB1 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 NC/WP** *32MB version only **-10B version only
SYMBOL DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CAS# DQMB4 DQMB5 S1#* RAS#
SYMBOL CKE0 S3#* DQMB6 DQMB7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
SDRAM DIMMs ZM01.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMMs
PART NUMBERS
PART NUMBER MT9LSDT272AG-10B_ MT9LSDT272AG-662_ MT18LSDT472AG-10B_ MT18LSDT472AG-662_ CONFIGURATION SYSTEM SPEED
NOTE: part numbers with two-place code (not shown), designating component revisions. Consult factory current revision codes. Example: MT9LSDT272AG-10BD2.
GENERAL DESCRIPTION
MT9LSDT272A MT18LSDT472A high-speed CMOS, dynamic random-access, 16MB 32MB solidstate memories organized configuration. These modules SDRAMs that internally configured dual memory arrays with synchronous interface (all signals registered positive edge clock signals CK0-CK3). Read write accesses SDRAM module burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select bank accessed (BA0 selects bank; A0-A10 select row). address bits registered coincident with READ WRITE command used select starting column location burst access. modules provide programmable READ WRITE burst lengths locations, full page, with burst terminate option. AUTO PRECHARGE function enabled provide self-timed precharge that initiated burst sequence.
modules internal pipelined architecture achieve high-speed operation. This architecture compatible with rule prefetch architectures, also allows column address changed every clock cycle achieve high-speed, fully random access. Precharging bank while accessing alternate bank will hide PRECHARGE cycles provide seamless, high-speed, random-access operation. modules designed operate 3.3V, low-power memory systems. auto refresh mode provided, along with power-saving, power-down mode. inputs outputs LVTTL-compatible. SDRAM modules offer substantial advances DRAM operating performance, including ability synchronously burst data high data rate with automatic column-address generation, ability interleave between internal banks order hide precharge time capability randomly change column addresses each clock cycle during burst access. more information regarding SDRAM operation, refer 16Mb: SDRAM data sheet.
SERIAL PRESENCE-DETECT OPERATION
This module incorporates serial presence-detect (SPD). function implemented using 2,048-bit EEPROM. This nonvolatile storage device contains bytes. first bytes programmed Micron identify module type various SDRAM organizations timing parameters. remaining bytes storage available customer. System READ/WRITE operations between master (system logic) slave EEPROM device (DIMM) occur standard using DIMM's (clock) (data) signals, together with SA(2:0), which provide eight unique DIMM/EEPROM addresses.
SDRAM DIMMs ZM01.p65 Rev. 6/98
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SDRAM DIMMs
CLOCK DATA CONVENTIONS Data states line change only during LOW. state changes during HIGH reserved indicating start stop conditions (Figures START CONDITION commands preceded start condition, which HIGH-to-LOW transition when HIGH. device continuously monitors lines start condition will respond command until this condition been met. STOP CONDITION communications terminated stop condition, which LOW-to-HIGH transition when HIGH. stop condition also used place device into standby power mode. ACKNOWLEDGE Acknowledge software convention used indicate successful data transfers. transmitting device, either master slave, will release after transmitting eight bits. During ninth clock cycle, receiver will pull line acknowledge that received eight bits data (Figure device will always respond with acknowledge after recognition start condition slave address. both device WRITE operation have been selected, device will respond with acknowledge after receipt each subsequent eight-bit word. read mode device will transmit eight bits data, release line monitor line acknowledge. acknowledge detected stop condition generated master, slave will continue transmit data. acknowledge detected, slave will terminate further data transmissions await stop condition return standby power mode.
DATA STABLE DATA CHANGE DATA STABLE
Figure DATA VALIDITY
START
STOP
Figure DEFINITION START STOP
from Master
Data Output from Transmitter
Data Output from Receiver Acknowledge
Figure ACKNOWLEDGE RESPONSE FROM RECEIVER
SDRAM DIMMs ZM01.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM MT9LSDT272A (16MB)
DQMB0 DQMB1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQMB4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
RAS# CAS# CKE0 A0-A10
RAS#: SDRAMs U0-U8 CAS#: SDRAMs U0-U8 CKE0: SDRAMs U0-U8 WE#: SDRAMs U0-U8 A0-A10: SDRAMs U0-U8 SDRAMs U0-U8 SDRAMs U0-U8 SDRAMs U0-U8 CK2, SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM
3.3pF
CK1,
10pF VERSIONS
10pF VERSIONS
NOTE: resistor values ohms unless otherwise specified.
U0-U8 MT48LC2M8A1TG SDRAMs
SDRAM DIMMs ZM01.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM MT18LSDT472A (32MB)
DQMB0 DQMB1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQMB6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
CKE1 CKE0 CAS# RAS# A0-A10
CKE: SDRAMs U9-U17 CKE: SDRAMs U0-U8 CAS#: SDRAMs U0-U17 RAS#: SDRAMs U0-U17 WE#: SDRAMs U0-U17 A0-A10: SDRAMs U0-U17 SDRAMs U0-U17 SDRAMs U0-U17 SDRAMs U0-U17
3.3pF
SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM
3.3pF
VERSIONS
NOTE: resistor values ohms unless otherwise specified.
VERSIONS
U0-U17 MT48LC2M8A1TG SDRAMs
SDRAM DIMMs ZM01.p65 Rev. 6/98
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SDRAM DIMMs
DESCRIPTIONS
NUMBERS 115, 111, 125, SYMBOL RAS#, CAS#, CK0-CK3 TYPE Input Input DESCRIPTION Command Inputs: RAS#, CAS# (along with S0#-S3#) define command being entered. Clock: CK0-CK3 driven system clock. SDRAM input signals sampled positive edge also increments internal burst counter controls output registers. Clock Enable: CKE0-CKE1 activate (HIGH) deactivate (LOW) CK0-CK3 signals. Deactivating clock provides POWER-DOWN SELF REFRESH operation (all banks idle) CLOCK SUSPEND operation (burst access progress). CKE0-CKE1 synchronous except after device enters power-down self refresh modes, where CKE0-CKE1 become asynchronous until after exiting same mode. input buffers, including CK0CK3, disabled during power-down self refresh modes, providing standby power. Chip Select: S0#-S3# enable (registered LOW) disable (registered HIGH) command decoder. commands masked when S0#-S3# registered HIGH. S0#-S3# considered part command code. Input/Output Mask: DQMB input mask signal write accesses output enable signal read accesses. Input data masked when DQMB sampled HIGH during WRITE cycle. output buffers placed High-Z state (two-clock latency) when DQMB sampled HIGH during READ cycle. Bank Address: defines which bank ACTIVE, READ, WRITE PRECHARGE command being applied. also used program 12th Mode Register. Address Inputs: A0-A10 sampled during ACTIVE command (row-address A0-A10) READ/WRITE command (column-address A0-A8, with defining AUTO PRECHARGE) select location memory array respective bank. sampled during PRECHARGE command determine both banks precharged (A10 HIGH). address inputs also provide op-code during LOAD MODE REGISTER command. Data I/O: Data bus.
128,
CKE0, CKE1
Input
114,
S0#-S3#
Input
28-29, 46-47, 112-113, 130-131
DQMB0-DQMB7
Input
Input
33-38, 117-121
A0-A10
Input
2-5, 7-11, 13-17, 19-20, 55-58, 65-67, 69-72, 74-77, 86-89, 91-95, 97-101, 103, 104, 139-142, 144, 149-151, 153-156, 158-161 105, 106, 136,
SDRAM DIMMs ZM01.p65 Rev. 6/98
DQ0-DQ63
Input/ Output
CB0-CB7
Input/ Output
Check Bits.
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMMs
DESCRIPTIONS (continued)
NUMBERS 102, 110, 124, 133, 143, 157, 107, 116, 127, 138, 148, 152, SYMBOL TYPE Supply DESCRIPTION Power Supply: +3.3V ±0.3V.
Supply
Ground.
Input Input/Output
Write Protect: Serial presence-detect hardware write protect. Applies -10B version only. Serial Presence-Detect Data: bidirectional used transfer addresses data into presence-detect portion module. Serial Clock Presence-Detect: used synchronize presence-detect data transfer from module. Presence-Detect Address Inputs: These pins used configure presence-detect device. Reserved Future Use: These pins should left unconnected. Use: These pins connected these modules assigned pins compatible DRAM version.
Input
165-167 123, 126,
SA0-SA2
Input
SDRAM DIMMs ZM01.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMMs
SERIAL PRESENCE-DETECT MATRIX
BYTE DESCRIPTION NUMBER BYTES USED MICRON TOTAL NUMBER MEMORY BYTES MEMORY TYPE NUMBER ADDRESSES NUMBER COLUMN ADDRESSES NUMBER BANKS MODULE DATA WIDTH MODULE DATA WIDTH (continued) MODULE VOLTAGE INTERFACE LEVELS SDRAM CYCLE TIME (CAS LATENCY SDRAM ACCESS FROM CLOCK (CAS LATENCY MODULE CONFIGURATION TYPE REFRESH RATE/TYPE SDRAM WIDTH (PRIMARY SDRAM) ERROR-CHECKING SDRAM DATA WIDTH MINIMUM CLOCK DELAY FROM BACK-TO-BACK RANDOM COLUMN ADDRESSES BURST LENGTHS SUPPORTED NUMBER BANKS SDRAM DEVICE LATENCIES SUPPORTED LATENCY LATENCY SDRAM MODULE ATTRIBUTES SDRAM DEVICE ATTRIBUTES: GENERAL SDRAM CYCLE TIME (CAS LATENCY SDRAM ACCESS FROM (CAS LATENCY SDRAM CYCLE TIME (CAS LATENCY SDRAM ACCESS FROM (CAS LATENCY MINIMUM PRECHARGE TIME MINIMUM ACTIVE ACTIVE MINIMUM RAS# CAS# DELAY MINIMUM RAS# PULSE WIDTH MODULE BANK DENSITY COMMAND ADDRESS SETUP TIME ENTRY (VERSION) SYMBOL BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 SDRAM (16MB) (32MB) LVTTL (-10B) (-662) (-10B) (-662) 15.6µs/SELF PAGE NONBUFFERED (-10B) (-662) (-10B) (-662) (-10B) (-662) (-10B) (-662) 16MB (-10B) (-662)
tCCD
tRRD tRCD tRAS
tAS,tCMS
NOTE:
"1"/"0": Serial Data, "driven HIGH"/"driven LOW."
SDRAM DIMMs ZM01.p65 Rev. 6/98
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SDRAM DIMMs
SERIAL PRESENCE-DETECT MATRIX (continued)
BYTE 36-61 DESCRIPTION COMMAND ADDRESS HOLD TIME DATA SIGNAL INPUT SETUP TIME DATA SIGNAL INPUT HOLD TIME RESERVED REVISION CHECKSUM BYTES 0-62 ENTRY (VERSION) (-10B) (-662) (-10B) (-662) (-10B) (-662) REV. (-10B) REV. (-662) 16MB (-10B) 16MB (-662) 32MB (-10B) 32MB (-662) MICRON SYMBOL BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 tAH,tCMH
65-71
MANUFACTURER'S JEDEC CODE MANUFACTURER'S JEDEC CODE (CONT.) MANUFACTURING LOCATION
73-90
MODULE PART NUMBER (ASCII) IDENTIFICATION CODE
95-98 99-125
IDENTIFICATION CODE (CONT.) YEAR MANUFACTURE WEEK MANUFACTURE MODULE SERIAL NUMBER MANUFACTURER-SPECIFIC DATA (RSVD) SYSTEM FREQUENCY SDRAM COMPONENT CLOCK DETAIL
(-10B) (-662) 16MB (-10B) 32MB (-10B) (-662)
NOTE:
"1"/"0": Serial Data, "driven HIGH"/"driven LOW." Variable Data.
SDRAM DIMMs ZM01.p65 Rev. 6/98
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SDRAM DIMMs
COMMANDS
Truth Table provides general reference available commands. more detailed description commands operations, refer 16Mb: SDRAM data sheet.
TRUTH TABLE Commands DQMB Operation
(Notes: NAME (FUNCTION) COMMAND INHIBIT (NOP) OPERATION (NOP) ACTIVE (Select bank activate row) READ (Select bank column, start READ burst) WRITE (Select bank column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate bank banks) AUTO REFRESH SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z RAS# CAS# DQMB ADDR Bank/Row Bank/Col Code Op-code Active Active High-Z NOTES
Bank/Col Valid
NOTE: HIGH commands shown except SELF REFRESH. A0-A10 define op-code written Mode Register. A0-A10 provide address, determines which bank made active (BA0 Bank HIGH Bank A0-A8 provide column address; HIGH enables auto precharge feature (nonpersistent), while disables auto precharge feature; determines which bank being read from written (BA0 Bank HIGH Bank LOW: determines which bank being precharged (BA0 Bank HIGH Bank HIGH: both banks precharged "Don't Care." This command AUTO REFRESH HIGH, SELF REFRESH LOW. Internal refresh counter controls addressing; inputs I/Os "Don't Care" except CKE. Activates deactivates during WRITEs (zero-clock delay) READs (two-clock delay).
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SDRAM DIMMs
Address
Table BURST DEFINITION
Burst Length
Mode Register (Mx)
Reserved*
Mode
Latency
Burst Length
Starting Column Order Accesses Within Burst Address Type Sequential Type Interleaved 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
*Should program M11, ensure compatibility with future devices.
Burst Length Reserved Reserved Reserved Full Page
Reserved Reserved Reserved Reserved
Burst Type Sequential Interleaved
Latency Reserved Reserved Reserved Reserved Reserved
Full Page (512)
A0-A8 (location 0-511)
Supported
NOTE:
M6-M0 Defined
Operating Mode Standard Operation other states reserved
Write Burst Mode Programmed Burst Length Single Location Access
Figure MODE REGISTER DEFINITION
burst length two, A1-A8 select block-oftwo burst; selects starting column within block. burst length four, A2-A8 select block-offour burst; A0-A1 select starting column within block. burst length eight, A3-A8 select block-ofeight burst; A0-A2 select starting column within block. full-page burst, full selected, A0-A8 select starting column. Whenever boundary block reached within given sequence above, following access wraps within block. burst length one, A0-A8 select unique column accessed, Mode Register ignored.
SDRAM DIMMs ZM01.p65 Rev. 6/98
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SDRAM DIMMs
ABSOLUTE MAXIMUM RATINGS*
Voltage Supply Relative +4.6V Voltage Inputs, Pins Relative +4.6V Operating Temperature, (ambient) +70°C Storage Temperature (plastic) -55°C +125°C Power Dissipation *Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS
(Notes: (VDD +3.3V ±0.3V) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs INPUT LEAKAGE CURRENT: input (All other pins under test OUTPUT LEAKAGE CURRENT: disabled; VOUT OUTPUT LEVELS: Output High Voltage (IOUT -2mA) Output Voltage (IOUT 2mA) DQMB0-DQMB7 CK0-CK3, S0#-S3# CKE0-CKE1 RAS#, CAS#, A0-A10, BA0, DQ0-DQ63, CB0-CB7 SYMBOL -0.5 UNITS NOTES
SPECIFICATIONS CONDITIONS
(Notes: (VDD +3.3V ±0.3V) PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN); latency 15ns (10ns -10B) STANDBY CURRENT: Power-Down Mode; 15ns (10ns -10B); LOW; banks idle STANDBY CURRENT: Active Mode; S0#-S3# HIGH; 15ns (10ns -10B); HIGH; banks active after tRCD met; accesses progress
SYMBOL ICC1 32MB 1,350 ICC2 16MB 32MB 16MB ICC3 32MB ICC4 32MB 1,530 ICC5 ICC6 16MB 32MB 1,260 16MB 32MB 1,125 1,125 16MB 1,125 1,170 SIZE 16MB -10B -662 UNITS NOTES
OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; 15ns (10ns -10B); banks active; latency AUTO REFRESH CURRENT: (MIN); latency HIGH; S0#-S3# HIGH; 15ns (10ns -10B) SELF REFRESH CURRENT: 0.2V
SDRAM DIMMs ZM01.p65 Rev. 6/98
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SDRAM DIMMs
CAPACITANCE
16MB PARAMETER Input Capacitance: A0-A10, BA0, RAS#, CAS#, Input Capacitance: S0#-S3#, CK0-CK3 Input Capacitance: CKE0, CKE1 Input Capacitance: DQMB0#-DQMB7# Input Capacitance: SCL, SA0-SA2 Input/Output Capacitance: DQ0-DQ63, SDA, CB0-CB7 SYMBOL 32MB UNITS NOTES
SDRAM COMPONENT* ELECTRICAL CHARACTERISTICS
(Notes:
CHARACTERISTICS PARAMETER Access time from (positive edge) Address hold time Address setup time high-level width low-level width Clock cycle time hold time setup time CS#, RAS#, CAS#, WE#, hold time CS#, RAS#, CAS#, WE#, setup time Data-in hold time Data-in setup time Data-out high-impedance time Data-out low-impedance time Data-out hold time ACTIVE PRECHARGE command period AUTO REFRESH, ACTIVE command period ACTIVE READ WRITE delay Refresh period (4,096 cycles) PRECHARGE command period ACTIVE bank ACTIVE bank command period Transition time WRITE recovery time Exit SELF REFRESH ACTIVE command *Specifications SDRAM components used module. -10B SYMBOL tCKH tCKS tCMH tCMS tRAS tRCD tREF tRRD
tXSR
-662
120,000
UNITS NOTES 120,000
SDRAM DIMMs ZM01.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMMs
FUNCTIONAL CHARACTERISTICS
(Notes:
PARAMETER READ/WRITE command READ/WRITE command clock disable power-down entry mode clock enable power-down exit setup mode input data delay data mask during WRITEs data high-impedance during READs WRITE command input data delay Data-in ACTIVE command Data-in PRECHARGE command Last data-in PRECHARGE command Last data-in burst STOP command Last data-in READ/WRITE command LOAD MODE REGISTER command ACTIVE REFRESH command Data-out high-impedance from PRECHARGE command SYMBOL tCCD tCKED tPED tDQD tDQM tDQZ tDWD tDAL tDPL tRDL tBDL tCDL tMRD tROH tROH tROH -10B -662 UNITS NOTES
SDRAM COMPONENT* ELECTRICAL TIMING CHARACTERISTICS BETWEEN SPEED OPTIONS
(Notes:
CHARACTERISTICS PARAMETER Access time from (pos. edge) SYMBOL UNITS NOTES tRCD 2-2-2 2-2-2 3-2-2 3-2-3 3-3-3 CLKs
Clock cycle time
ACTIVE READ WRITE delay PRECHARGE command period AUTO REFRESH, ACTIVE command period WRITE recovery time Speed Reference (CL-tRCD-tRP)
*Specifications SDRAM components used module.
SDRAM DIMMs ZM01.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMMs
SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS
(Notes: (VDD +3.3V ±0.3V) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs OUTPUT VOLTAGE: IOUT INPUT LEAKAGE CURRENT: OUTPUT LEAKAGE CURRENT: VOUT STANDBY CURRENT: 0.3V; other inputs 3.3V +10% POWER SUPPLY CURRENT: clock frequency SYMBOL UNITS NOTES
SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS
(Notes: (VDD +3.3V ±0.3V)
PARAMETER/CONDITION data-out valid Time must free before transition start Data-out hold time fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant SCL, inputs Clock period rise time clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time SYMBOL tBUF tHD:DAT tHD:STA tHIGH tLOW tSCL tSU:DAT tSU:STA tSU:STO tWRC UNITS NOTES
SDRAM DIMMs ZM01.p65 Rev. 6/98
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SDRAM DIMMs
NOTES
voltages referenced VSS. This parameter sampled. +3.3V; MHz. dependent output loading cycle rates. Specified values obtained with minimum cycle time outputs open. Enables on-chip refresh address counters. minimum specifications used only indicate cycle time which proper operation over full temperature range (0°C 70°C) ensured. initial pause 100µs required after power-up, followed AUTO REFRESH commands, before proper device operation ensured. AUTO REFRESH command wake-ups should repeated time tREF refresh requirement exceeded. characteristics assume 1ns. addition meeting transition rate specification, clock must transit between between VIH) monotonic manner. Outputs measured 1.5V with equivalent load: Timing actually specified tWR. Required clocks specified JEDEC functionality dependent timing parameter. current will decrease latency reduced. This because maximum cycle rate slower latency reduced. Address transitions average transition every 30ns (20ns -10B). must toggled minimum times during this period. Based -10B -662. 16MB module values will half those shown. EEPROM WRITE cycle time (tWRC) time from valid stop condition write sequence EEPROM internal erase/program cycle. During WRITE cycle, EEPROM interface circuit disabled, remains HIGH pull-up resistor, EEPROM does respond slave address. recommended that DRAM controller clocks support future design requirements. overshoot: (MAX) pulse width 10ns, pulse width cannot greater than third cycle rate. undershoot: (MIN) pulse width 10ns, pulse width cannot greater than third cycle rate. clock frequency must remain constant during access precharge states (READ, WRITE, including tWR, PRECHARGE commands). used reduce data rate. Auto precharge mode only. Precharge mode only. JEDEC PC100 specify three clocks. These five parameters vary between speed grades define differences between SDRAM speeds: -8A, -8B, -8C, -8E. other timing parameters remain constant.
50pF
defines time which output achieves open circuit condition; reference VOL. last valid data element will meet before going High-Z. timing tests have with timing referenced 1.5V crossover point. Other input signals allowed transition more than once 30ns period (20ns -10B) otherwise valid levels. specifications tested after device properly initialized. Timing actually specified tCKS; clock(s) specified reference only minimum cycle rate. Timing actually specified plus tRP; clock(s) specified reference only minimum cycle rate.
SDRAM DIMMs ZM01.p65 Rev. 6/98
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SDRAM DIMMs
EEPROM
tLOW tHIGH
SU:STA HD:STA HD:DAT SU:DAT SU:STO
,,,,,,
tBUF
SERIAL PRESENCE-DETECT EEPROM TIMING PARAMETERS
SYMBOL tBUF tHD:DAT tHD:STA UNITS SYMBOL tHIGH tLOW tSU:DAT tSU:STA tSU:STO
UNDEFINED
UNITS
SDRAM DIMMs ZM01.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMMs
168-PIN DIMM DF-19 (32MB, MHz)
FRONT VIEW
5.256 (133.50) 5.244 (133.20) .157 (4.00)
.079 (2.00) (2X) 1.155 (29.34) 1.145 (29.08) .118 (3.00) (2X) .118 (3.00) .250 (6.35) .118 (3.00) 1.661 (42.18) 2.625 (66.68) .039 (1.00)R (2X) .039 (1.00) .050 (1.27) .128 (3.25) (2X) .118 (3.00) .054 (1.37) .046 (1.17) .700 (17.78)
(PIN backside)
4.550 (115.57)
(PIN BACKSIDE)
168-PIN DIMM DF-20 (16MB, MHz)
FRONT VIEW
5.256 (133.50) 5.244 (133.20) .125 (3.18)
.079 (2.00) (2X) 1.155 (29.34) 1.145 (29.08) .118 (3.00) (2X) .118 (3.00) .250 (6.35) .118 (3.00) 1.661 (42.18) 2.625 (66.68) .039 (1.00)R (2X) .039 (1.00) .050 (1.27) .128 (3.25) (2X) .118 (3.00) .054 (1.37) .046 (1.17) .700 (17.78)
(PIN backside)
4.550 (115.57)
(PIN BACKSIDE)
NOTE:
dimensions inches (millimeters)
typical where noted.
SDRAM DIMMs ZM01.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
SDRAM DIMMs
168-PIN DIMM DF-24 (16MB, MHz)
FRONT VIEW
5.256 (133.50) 5.244 (133.20) .125 (3.18)
.079 (2.00) (2X) 1.255 (31.88) 1.245 (31.62) .118 (3.00) (2X) .118 (3.00) .250 (6.35) .118 (3.00) 1.661 (42.18) 2.625 (66.68) .039 (1.00)R (2X) .039 (1.00) .050 (1.27) .128 (3.25) (2X) .118 (3.00) .054 (1.37) .046 (1.17) .700 (17.78)
(PIN backside)
4.550 (115.57)
(PIN BACKSIDE)
168-PIN DIMM DF-25 (32MB, MHz)
FRONT VIEW
5.256 (133.50) 5.244 (133.20) .157 (4.00)
.079 (2.00) (2X) 1.255 (31.88) 1.245 (31.62) .118 (3.00) (2X) .118 (3.00) .250 (6.35) .118 (3.00) 1.661 (42.18) 2.625 (66.68) .039 (1.00)R (2X) .039 (1.00) .050 (1.27) .128 (3.25) (2X) .118 (3.00) .054 (1.37) .046 (1.17) .700 (17.78)
(PIN backside)
4.550 (115.57)
(PIN BACKSIDE)
NOTE:
dimensions inches (millimeters)
typical where noted.
SDRAM DIMMs ZM01.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
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