Industry-standard pinouts, timing, functions packages High-performance

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Industry-standard pinouts, timing, functions packages High-performance CMOS silicon-gate process Single ±10% power supply* inputs, outputs clocks TTL-compatible 512-cycle refresh column addresses) Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR) HIDDEN Extended Data-Out (EDO) PAGE MODE access BYTE WRITE BYTE READ access cycles
MT4C16270
latest data sheet revisions, please refer Micron site:
ASSIGNMENT (Top View) 40-Pin
OPTIONS
Package Plastic (400 mil) Timing 40ns access 50ns access 60ns access
MARKING
Part Number Example: MT4C16270DJ-4
NOTE: symbol indicates signal active LOW. *40ns 50ns access specifications limited range ±5%.
TIMING PARAMETERS
SPEED
tRAC tCAC tCAS
75ns 100ns 110ns
40ns 50ns 60ns
15ns 20ns 25ns
20ns 25ns 30ns
12ns 15ns 15ns
10ns
10ns
RAS#
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 CASL# CASH#
GENERAL DESCRIPTION
MT4C16270 randomly accessed, solid-state memory containing 4,194,304 bits organized configuration. MT4C16270 both BYTE WRITE WORD WRITE access cycles CAS# pins. MT4C16270 CAS# function timing determined first CAS# (CASL# CASH#) transition last transition back HIGH. CASL# CASH# function like CAS# that either CASL#
256K DRAM W06.p65 Rev. 6/98
CASH# will generate internal CAS#. Using only signals results BYTE WRITE cycle. CASL# transitioning selects WRITE cycle lower byte (DQ0-DQ7), CASH# transitioning selects WRITE cycle upper byte (DQ8-DQ15). BYTE READ cycles achieved through CASL# CASH# same manner.
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
256K FUNCTIONAL BLOCK DIAGRAM
CASL# CASH#
CAS#
CONTROL LOGIC
DATA-IN BUFFER
CLOCK GENERATOR DATA-OUT BUFFER
DQ15
COLUMNADDRESS BUFFER REFRESH CONTROLLER
COLUMN DECODER
SENSE AMPLIFIERS GATING REFRESH COUNTER ROWADDRESS BUFFERS DECODER MEMORY ARRAY
RAS#
CLOCK GENERATOR
FUNCTIONAL DESCRIPTION
Each uniquely addressed through address bits during READ WRITE cycles. These entered nine bits -A8) time. RAS# used latch first nine bits CAS#, latter nine bits. CAS# control also determines whether cycle will refresh cycle (RAS#-ONLY) active cycle (READ, WRITE READ-WRITE) once RAS# goes LOW. MT4C16270 CAS# controls: CASL# CASH#. CASL# CASH# inputs internally generate CAS# signal that functions like single CAS# input other 256K DRAMs. difference that each CAS# controls corresponding tristate logic conjunction with OE#, RAS#). CASL# controls DQ0DQ7 CASH# controls DQ8-DQ15.
256K DRAM W06.p65 Rev. 6/98
MT4C16270 CAS# function determined first CAS# (CASL# CASH# transitioning last transitioning back HIGH. CAS# controls give MT4C16270 both BYTE READ BYTE WRITE cycle capabilities. (See Figures logic HIGH dictates read mode, while logic dictates write mode. During WRITE cycle, data-in latched falling edge CAS# (CASL# CASH#), whichever occurs last. EARLY WRITE occurs when taken prior either CAS# falling. LATE WRITE READ-MODIFY-WRITE occurs when falls after CAS# (CASL# CASH#) taken LOW. During EARLY WRITE cycles, data outputs will remain High-Z, regardless state OE#. During
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
256K WORD WRITE RAS# LOWER BYTE WRITE
CASL#
CASH#
STORED DATA
INPUT DATA
INPUT DATA
STORED STORED DATA DATA
INPUT DATA
INPUT DATA
STORED DATA
LOWER BYTE (DQ0-DQ7) WORD
UPPER BYTE (DQ8-DQ15) WORD
ADDRESS
ADDRESS EFFECTIVE (DON'T CARE)
Figure WORD BYTE WRITE EXAMPLE
WORD READ RAS# LOWER BYTE READ
CASL#
CASH#
LOWER BYTE (DQ0-DQ7) WORD
STORED DATA
OUTPUT DATA
OUTPUT DATA
STORED STORED DATA DATA
OUTPUT DATA
OUTPUT DATA
STORED DATA
UPPER BYTE (DQ8-DQ15) WORD
ADDRESS High-Z
ADDRESS
Figure WORD BYTE READ EXAMPLE
256K DRAM W06.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
256K FUNCTIONAL DESCRIPTION (continued)
LATE WRITE READ-MODIFY-WRITE cycles, must taken HIGH disable data outputs prior applying input data. LATE WRITE READ-MODIFY-WRITE attempted while keeping LOW, WRITE will occur, data outputs will drive read data from accessed location. Additionally, both bytes must always same mode operation both bytes active. CAS# precharge must satisfied prior changing modes operation between upper lower bytes. example, EARLY WRITE byte LATE WRITE other byte allowed during same cycle. However, EARLY WRITE byte LATE WRITE other byte, after CAS# precharge been satisfied, permissible. data inputs data outputs routed through pins using common I/O, direction controlled OE#, RAS#. EDO-PAGE-MODE operations allow faster data operations (READ, WRITE READ-MODIFY-WRITE) within row-address-defined -A8) page boundary. EDOPAGE-MODE cycle always initiated with address strobed RAS#, followed column address strobed CAS#. Additional columns accessed providing valid column addresses, strobing CAS# holding RAS# thus executing faster memory cycles. Returning RAS# HIGH terminates EDO-PAGE-MODE operation.
BYTE ACCESS CYCLE
BYTE WRITE cycle determined CASL# CASH#. Enabling CASL# selects lower BYTE WRITE cycle (DQ0-DQ7), while enabling CASH# selects upper BYTE WRITE cycle (DQ8-DQ15). Enabling both CASL# CASH# selects WORD WRITE cycle. MT4C16270 viewed 256K DRAMs that have common input controls. Figure illustrates BYTE WRITE WORD WRITE cycles. BYTE READ accomplished same manner (see Figure
RAS#
CASL#/CASH#
ADDR
,,,,, ,,,,, ,,,,, ,,,,
COLUMN COLUMN COLUMN COLUMN OPEN
VALID DATA
VALID DATA
VALID DATA OEHC
VALID DATA
VALID DATA
back Low-Z tOES met.
remain High-Z until next CAS# cycle tOEHC met.
remain High-Z until next CAS# cycle tOEP met.
DON'T CARE UNDEFINED
Figure CONTROL
256K DRAM W06.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
256K PAGE MODE
DRAM READ cycles have traditionally turned output buffers (High-Z) with rising edge CAS#. CAS# goes HIGH, (active), output buffers will disabled. MT4C16270 offers accelerated page mode cycle eliminating output disable from CAS# HIGH. This option called EDO, allows CAS# precharge time (tCP) occur without output data going invalid (see READ EDO-PAGE-MODE READ waveforms). operates like DRAM READ FAST-PAGEMODE READ, except data held valid after CAS# goes HIGH, long RAS# held held HIGH. brought HIGH while CAS# RAS# LOW, will transition between valid data High-Z. Using OE#, there methods disable outputs keep them disabled during CAS# HIGH time. first method have HIGH when CAS# transitions HIGH keep HIGH tOEHC. This will tristate they will remain tristate, regardless OE#, until CAS# falls again. second method have when CAS# transitions HIGH. Then pulse HIGH minimum tOEP anytime during CAS# HIGH period will tristate remain tristate, regardless OE#, until CAS# falls again. (Please refer Figure further detail toggling condition.) During other cycles, outputs disabled tOFF time after RAS# CAS# HIGH tWHZ after transitions LOW. tOFF time referenced from rising edge RAS# CAS#, whichever occurs last. also perform function turning output drivers under certain conditions, shown Figure Returning RAS# CAS# HIGH terminates memory cycle decreases chip current reduced standby level. chip also preconditioned next cycle during RAS# HIGH time. Memory cell data retained correct state maintaining power executing RAS# cycle (READ, WRITE) RAS# REFRESH cycle (RAS#-ONLY, HIDDEN) that combinations RAS# addresses (A0-A8) executed least every 8ms, regardless sequence. REFRESH cycle will also invoke refresh counter controller row-address control.
RAS#
CASL#/CASH#
ADDR
,,,,,, ,,,,, ,,,,,
COLUMN COLUMN COLUMN COLUMN OPEN
VALID DATA
VALID DATA
INPUT DATA
High-Z falls, tWPZ met, will remain High-Z until CAS# goes with HIGH (i.e., until READ cycle initiated).
used disable prepare input data EARLY WRITE cycle. will remain High-Z until CAS# goes with HIGH (i.e., until READ cycle initiated).
Figure CONTROL
DON'T CARE UNDEFINED
256K DRAM W06.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
256K ABSOLUTE MAXIMUM RATINGS*
Voltage Relative Operating Temperature, (ambient) +70°C Storage Temperature (plastic) -55°C +150°C Power Dissipation 1.2W *Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS
(Notes: (VCC ±10%)** PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Valid Logic inputs INPUT VOLTAGE: Valid Logic inputs INPUT LEAKAGE CURRENT: input other pins under test OUTPUT HIGH VOLTAGE: IOUT -2.5mA OUTPUT VOLTAGE: IOUT 2.1mA OUTPUT LEAKAGE CURRENT: disabled; VOUT **40 50ns specifications limited range ±5%. SYMBOL VCC** -1.0 UNITS NOTES
256K DRAM W06.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
256K OPERATING CONDITIONS MAXIMUM LIMITS
(Notes: (VCC ±10%)** PARAMETER/CONDITIONS STANDBY CURRENT: (RAS# CAS# VIH) STANDBY CURRENT: CMOS (RAS# CAS# 0.2V) OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: [MIN]) OPERATING CURRENT: PAGE MODE Average power supply current (RAS# VIL, CAS#, address cycling: [MIN]; tCP, tASC 10ns) REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS# VIH: [MIN]) REFRESH CURRENT: Average power supply current (RAS#, CAS#, address cycling: [MIN]) **40 50ns specifications limited range ±5%. SYMBOL ICC1 ICC2 UNITS NOTES
ICC3
ICC4
ICC5
ICC6
256K DRAM W06.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
256K CAPACITANCE
PARAMETER Input Capacitance: A0-A8 Input Capacitance: RAS#, CASL#, CASH#, WE#, Input/Output Capacitance: SYMBOL UNITS NOTES
ELECTRICAL CHARACTERISTICS
(Notes: (VCC ±10%)*
CHARACTERISTICS PARAMETER Access time from column address Column-address setup CAS# precharge during WRITE Column-address hold time (referenced RAS#) Column-address setup time Row-address setup time Column address delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# hold time (CBR Refresh) Last CAS# going first CAS# returning HIGH CAS# output Low-Z Data output hold after CAS# CAS# precharge time Access time from CAS# precharge CAS# RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# delay time WRITE command CAS# lead time Data-in hold time Data-in setup time Output disable time Output enable time hold time from during READ-MODIFY-WRITE cycle HIGH hold time from CAS# HIGH HIGH pulse width CAS# HIGH setup time Output buffer turn-off delay from CAS# RAS# SYMBOL tACH
tASC tASR tAWD tCAC tCAH tCAS tCHR tCLCH tCLZ tCOH tCPA tCRP tCSH tCSR tCWD tCWL tOEH tOEHC tOEP tOES tOFF
10,000
UNITS NOTES
10,000
10,000
*40ns 50ns specifications limited range ±5%.
256K DRAM W06.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
256K ELECTRICAL CHARACTERISTICS
(Notes: (Vcc ±10%)*
CHARACTERISTICS PARAMETER setup prior RAS# during HIDDEN REFRESH cycle EDO-PAGE-MODE READ WRITE cycle time EDO-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# column-address delay time address hold time RAS# pulse width RAS# pulse width (EDO PAGE MODE) Random READ WRITE cycle time RAS# CAS# delay time READ command hold time (referenced CAS#) READ command setup time Refresh period (512 cycles) RAS# precharge time RAS# CAS# precharge time READ command hold time (referenced RAS#) RAS# hold time READ-WRITE cycle time RAS# delay time WRITE command RAS# lead time Transition time (rise fall) WRITE command hold time WRITE command hold time (referenced RAS#) WRITE command setup time Output disable delay from WRITE command pulse width pulse widths disable outputs hold time (CBR Refresh) setup time (CBR Refresh) SYMBOL tORD
tPRWC tRAC tRAD tRAH tRAS tRASP tRCD tRCH tRCS tREF tRPC tRRH tRSH tRWC tRWD tRWL tWCH tWCR tWCS tWHZ tWPZ tWRH tWRP
UNITS NOTES
10,000 100,000
10,000 100,000
10,000 100,000
*40ns 50ns specifications limited range ±5%.
256K DRAM W06.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
256K NOTES
voltages referenced VSS. This parameter sampled. MHz; 25°C. pins assumed left floating tested leakage. dependent output loading cycle rates. Specified values obtained with minimum cycle time output open. Enables on-chip refresh address counters. minimum specifications used only indicate cycle time which proper operation over full temperature range (0°C 70°C) ensured. initial pause 100µs required after power-up, followed eight RAS# refresh cycles (RAS#-ONLY CBR), before proper device operation ensured. eight RAS# cycle wake-ups should repeated anytime tREF refresh requirement exceeded. characteristics assume 2ns. (MIN) (MAX) reference levels measuring timing input signals. Transition times measured between between VIH). addition meeting transition rate specification, input signals must transit between between VIH) monotonic manner. CAS# RAS# data output High-Z. CAS# data output contain data from last valid READ cycle. Measured with load equivalent gate 50pF; 0.8V CAS# falling edge RAS#, will maintained from previous cycle. initiate cycle clear buffer, CAS# RAS# must pulsed HIGH tCP. tRCD (MAX) limit longer specified. tRCD (MAX) specified reference point only. tRCD greater than specified tRCD (MAX) limit, then access time controlled exclusively tCAC [tRAC longer applied]. With without tRCD (MAX) limit, tAA, tRAC tCAC must always met. tRAD (MAX) limit longer specified. tRAD (MAX) specified reference point only. tRAD greater than specified tRAD (MAX) limit, then access time controlled exclusively [tRAC tCAC longer applied]. With without tRAD (MAX) limit, tAA, tRAC tCAC must always met. Either tRCH tRRH must satisfied READ cycle. tOFF (MAX) defines time which output achieves open circuit condition; reference VOL.
256K DRAM W06.p65 Rev. 6/98
tWCS, tRWD, tAWD tCWD restrictive operating parameters LATE WRITE READMODIFY-WRITE cycles only. tWCS tWCS (MIN), cycle EARLY WRITE cycle data output will remain open circuit throughout entire cycle. tRWD tRWD (MIN), tAWD tAWD (MIN) tCWD tCWD (MIN), cycle READ-WRITE data output will contain data read from selected cell. neither above conditions met, state access time until CAS# RAS# back indeterminate. held HIGH taken after CAS# goes result LATE WRITE (OE#controlled) cycle. These parameters referenced CAS# leading edge EARLY WRITE cycles leading edge LATE WRITE READ-MODIFY-WRITE cycles. During READ cycle, then taken HIGH before CAS# goes HIGH, goes open. tied permanently LOW, LATE WRITE READMODIFY-WRITE operation possible. HIDDEN REFRESH also performed after WRITE cycle. this case, HIGH. other inputs -0.2V. Write command defined going LOW. LATE WRITE READ-MODIFY-WRITE cycles must have both tOEH (OE# HIGH during WRITE cycle) order ensure that output buffers will open during WRITE cycle. will provide previously written data CAS# remains taken back after tOEH met. open during READ cycles once tOFF occur. first CAS#x edge transition LOW. last CAS#x edge transition HIGH. Output parameter (DQx) referenced corresponding CAS# input, DQ0-DQ7 CASL# DQ8-DQ15 CASH#. Last falling CAS#x edge first rising CAS#x edge. Last rising CAS#x edge next cycle's last rising CAS#x edge. Last rising CAS#x edge first falling CAS#x edge. First controlled first CAS#x LOW. Last controlled last CAS#x HIGH. Each CAS#x must meet minimum pulse width. Last CAS#x LOW. controlled, regardless CASL# CASH#. Column address changed once each cycle. minimum parameter guaranteed design.
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
256K READ CYCLE
tRAS tCSH tRSH tCAS tRRH
RAS#
CASH#/CASL#
ADDR
,,,, ,,,,,,,, ,,,,,,,
tCRP tRCD tCLCH tRAD tRAH tASR tASC tCAH COLUMN tRCS tRCH tRAC tCAC tCLZ NOTE tOFF OPEN VALID DATA OPEN
TIMING PARAMETERS
SYMBOL
tASC tASR tCAC tCAH tCAS tCLCH tCLZ tCRP tCSH
DON'T CARE UNDEFINED
10,000 10,000
UNITS 10,000 SYMBOL tOES
tOFF tRAC tRAD tRAH tRAS tRCD tRCH tRCS tRRH tRSH
UNITS
10,000
10,000
10,000
NOTE: tOFF referenced from rising edge RAS# CAS#, whichever occurs last.
256K DRAM W06.p65 Rev. 6/98 Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
256K EARLY WRITE CYCLE
tRAS tCSH tRSH tCRP tRCD tCAS tCLCH
RAS#
CASL#/CASH#
ADDR
,,,,, ,,,,,, ,,,,
tRAD tRAH tASR tASC tCAH tACH COLUMN tCWL tRWL tWCR tWCH tWCS VALID DATA
TIMING PARAMETERS
SYMBOL tACH
tASC tASR tCAH tCAS tCLCH tCRP tCSH tCWL
DON'T CARE UNDEFINED
10,000 10,000
UNITS 10,000 SYMBOL tRAD
tRAH tRAS tRCD tRSH tRWL tWCH tWCR tWCS
UNITS
10,000
10,000
10,000
256K DRAM W06.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
256K READ-WRITE CYCLE (LATE WRITE READ-MODIFY-WRITE cycles)
tRWC tRAS tCSH tRSH tCRP CASL#/CASH# tRCD tCAS tCLCH
RAS#
ADDR
,,,, ,,,,
tRAD tASR tRAH tASC tCAH tACH COLUMN tRWD tCWL tRWL tRCS tCWD tAWD tRAC tCAC OPEN VALID VALID OPEN tOEH
TIMING PARAMETERS
SYMBOL
tACH tASC tASR tAWD tCAC tCAH tCAS tCLCH tCLZ tCRP tCSH tCWD tCWL
10,000 10,000
UNITS 10,000 SYMBOL
tOEH tRAC tRAD tRAH tRAS tRCD tRCS tRSH tRWC tRWD tRWL
10,000
DON'T CARE UNDEFINED
UNITS
10,000
10,000
256K DRAM W06.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
256K EDO-PAGE-MODE READ CYCLE
tRASP tCSH tCRP tRCD tCAS, tCLCH (NOTE tCAS, tCLCH tRSH tCAS, tCLCH
RAS#
CASH#/CASL#
ADDR
,,,,,
tRAD tRAH tASR tASC tCAH COLUMN tRCS tRAC tCAC tCLZ OPEN tOES
tASC
COLUMN
tCOH
VALID DATA
,,,,,
tCAH tASC tCAH COLUMN tRCH tRRH tCPA tCPA tCAC tCAC tCLZ tOFF VALID DATA tOEHC VALID DATA OPEN tOES tOEP
DON'T CARE UNDEFINED
TIMING PARAMETERS
SYMBOL
tASC tASR tCAC tCAH tCAS tCLCH tCLZ tCOH tCPA tCRP tCSH
10,000
UNITS 10,000 SYMBOL tOEHC tOEP
tOES tOFF tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRRH tRSH
100,000
100,000
UNITS
10,000
100,000
NOTE: measured from falling edge CAS# falling edge CAS#, from rising edge CAS# rising edge CAS#. Both measurements must meet specification.
256K DRAM W06.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
256K EDO-PAGE-MODE EARLY WRITE CYCLE
tRASP tCSH tCRP tRCD tCAS, tCLCH tCAS, tCLCH tRSH tCAS, tCLCH
RAS#
CASL#/CASH#
ADDR
,,,, ,,,, ,,,, ,,,,, ,,,,, ,,,, ,,,,,
tACH tRAD tACH tACH tASR tRAH tASC tCAH tASC tCAH tASC tCAH COLUMN COLUMN COLUMN tCWL tCWL tCWL tWCS tWCH tWCS tWCH tWCS tWCH tWCR tRWL VALID DATA VALID DATA VALID DATA
DON'T CARE UNDEFINED
TIMING PARAMETERS
tACH tASC tASR tCAH tCAS tCLCH tCRP tCSH tCWL
UNITS
tRAD tRAH tRASP tRCD tRSH tRWL tWCH tWCR tWCS
100,000
100,000
UNITS 100,000
10,000
10,000
10,000
256K DRAM W06.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
256K EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE READ-MODIFY-WRITE cycles)
tRASP tCSH tCRP tRCD tCAS, tCLCH tPRWC NOTE tCAS, tCLCH tRSH tCAS, tCLCH
RAS#
CASL#/CASH#
ADDR
,,,,,,, ,,,, ,,,,,,,
tRAD tRAH tASR tASC tCAH tASC tCAH COLUMN COLUMN tRWD tRCS tCWL tCWL tAWD tCWD tAWD tCWD tRAC tCPA tCAC tCLZ tCAC tCLZ OPEN VALID VALID VALID VALID
tASC
COLUMN
tCPA tCAC tCLZ
TIMING PARAMETERS
SYMBOL
tASC tASR tAWD tCAC tCAH tCAS tCLCH tCLZ tCPA tCRP tCSH tCWD tCWL
,,,,
tCAH tRWL tCWL tAWD tCWD VALID VALID OPEN
DON'T CARE UNDEFINED
10,000
UNITS 10,000 SYMBOL
tOEH tPRWC tRAC tRAD tRAH tRASP tRCD tRCS tRSH tRWD tRWL
100,000
100,000
UNITS
10,000
100,000
NOTE: measured from falling edge falling edge CAS#, from rising edge rising edge CAS#. Both measurements must meet specification.
256K DRAM W06.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
256K EDO-PAGE-MODE READ EARLY WRITE CYCLE (Psuedo READ-MODIFY-WRITE)
RASP RAS#
CASL#/CASH#
,,,,,
tASR ADDR COLUMN COLUMN OPEN VALID DATA VALID DATA
COLUMN
VALID DATA
TIMING PARAMETERS
SYMBOL tACH
tASC tASR tCAC tCAH tCAS tCOH tCPA tCRP tCSH
DON'T CARE UNDEFINED
10,000 10,000
UNITS 10,000 SYMBOL
tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRSH tWCH tWCS tWHZ
100,000
UNITS
100,000
100,000
256K DRAM W06.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
256K READ CYCLE (with WE#-controlled disable)
RAS# tCSH
CASL#/CASH#
ADDR
,,,, ,,,,, ,,,,,,,,,,,,,,,,,
tCRP tRCD tCAS tRAD tRAH tASR tASC tCAH tASC COLUMN COLUMN tRCS tRCH tWPZ tRCS tRAC tCAC tCLZ tWHZ tCLZ OPEN VALID DATA OPEN
DON'T CARE UNDEFINED
TIMING PARAMETERS
SYMBOL
tASC tASR tCAC tCAH tCAS tCLZ tCRP tCSH
10,000
UNITS 10,000 SYMBOL
tRAC tRAD tRAH tRCH tRCD tRCS tWHZ tWPZ
UNITS
10,000
256K DRAM W06.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
256K RAS#-ONLY REFRESH CYCLE (OE#, DON'T CARE)
tRAS
RAS#
CASL#/CASH#
ADDR
tCRP
tASR
tRAH
tRPC OPEN
REFRESH CYCLE (Addresses; OE#, DON'T CARE)
RAS# tRPC CASH#, CASL# OPEN tCSR tCHR tRPC tCSR tCHR tRAS tRAS
10,000
DON'T CARE UNDEFINED
TIMING PARAMETERS
SYMBOL tASR tCHR
tCRP tCSR
UNITS SYMBOL tRAH
tRAS tRPC
10,000 UNITS
10,000
256K DRAM W06.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
256K HIDDEN REFRESH CYCLE (WE# HIGH; LOW)
tRAS tRAS
RAS#
CASL#/CASH#
ADDR
,,,,,,,,,,,,, ,,,,,,,, ,,,,
tCRP tRCD tRSH tCHR tRAD tASR tRAH tASC tCAH COLUMN tRAC tCAC tCLZ NOTE tOFF OPEN VALID DATA OPEN tORD
DON'T CARE UNDEFINED
TIMING PARAMETERS
SYMBOL
tASC tASR tCAC tCAH tCHR tCLZ tCRP
UNITS SYMBOL
tOFF tORD tRAC tRAD tRAH tRAS tRCD tRSH
10,000
UNITS
10,000
10,000
256K DRAM W06.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.
256K 40-PIN PLASTIC (400 mil) DA-5
1.029 (26.14) 1.023 (25.98)
.405 (10.29) .399 (10.13) .445 (11.30) .435 (11.05)
INDEX
.050 (1.27) .950 (24.13)
.032 (0.81) .026 (0.66)
.150 (3.81) .138 (3.51)
.105 (2.67) .090 (2.29)
SEATING PLANE
.037 (0.94) DAMBAR PROTRUSION
.020 (0.51) .015 (0.38)
.380 (9.65) .360 (9.14)
.025 (0.64)
NOTE:
dimensions inches (millimeters) typical where noted. Package width length include mold protrusion; allowable mold protrusion .01" side.
8000 Federal Way, P.O. Boise, 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron registered trademark Micron Technology, Inc.
256K DRAM W06.p65 Rev. 6/98
Micron Technology, Inc., reserves right change products specifications without notice. ©1998, Micron Technology, Inc.

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