most systems microcontroller master external peripheral devices slaves

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AN554
most systems microcontroller master external peripheral devices slaves. these cases this application note used attach slaves PIC16CXXX (the master) microcontroller. multi-master system implemented because extremely difficult meet timing specifications using software. true slave multi-master system, some interface hardware necessary (like START STOP detection). addition level single master routines, collection high level routines with various message structures given. These high level macros/routines used canned routines interface most slave devices. example, test program talks Serial EEPROMs (Microchip's 24LC04 24LC01).
Software Implementation I2CBus Master
Amar Palacherla Microchip Technology Inc.
INTRODUCTION
This application note describes software implementation interface routines PIC16CXXX family devices. Only master mode interface implemented this application note. This implementation single master communication multiple slave devices. Some PIC16CXXX devices, such PIC16C64 PIC16C74, have on-chip hardware which implements slave interface, while other PIC16CXXX devices, such PIC16C71 PIC16C84, have same on-chip hardware. This application note does describe specifications user assumed have understanding Bus. detailed information bus, user advised read Specification document from Philips/Signetics (order number 98-8080-575). two-wire serial with multiple possible masters multiple possible slaves connected each other through wires. wires consists clock line (SCL) data line (SDA) with both lines being bi-directional. Bi-directional communication facilitated through wire connection (the lines either active-low passive high). protocol also allows collision detection, clock synchronization hand-shaking multi-master systems. clock always generated master, slave hold generate wait state.
IMPLEMENTATION
levels software routines provided. low-level routines "i2c_low.asm" provided Appendix high level routines "i2c_high.asm" provided Appendix messages passed (communicated wire network) abbreviated certain notation used represent Start, Stop other conditions. These abbreviations described Table
TABLE
Abbreviations SlvAR SlvAW
DESCRIPTION ABBREVIATIONS USED
Explanation Start Condition Stop Condition Slave Address (for read operation) Slave Address (for write operation) Acknowledge condition (positive ACK) Negative Acknowledge condition (NACK) Data byte, D[0] represents byte D[1] represents second byte
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Message Format
high level routines, basic structure message given. Every slave supports more message structures. example, Microchip's 24LC04 Serial EEPROM supports following message write byte Serial EEPROM current address counter) S-SlvAW-A-D-A-P which basically means following sequence operations required: Send Start Send Slave Address Write Operations Expect Acknowledge Send Data Byte Expect Acknowledge Issue STOP Condition
CLOCK STRETCHING
Bus, clock (SCL line) always provided master. However, slave hold line even though master released master must check this condition wait slave release clock line. This provides built-in wait state Bus. This feature implemented turned assembly time option configuring _ENABLE_BUS_FREE_TIME flag TRUE FALSE). clock held long, then error condition assumed T0CKI interrupt generated.
ARBITRATION
specifies both bit-by-bit byte mode arbitration procedures multi-master systems. However, arbitration needed single master system, therefore implemented this application note.
Slave Address
Both 10-bit 7-Bit addressing schemes implemented specified specification. Before calling certain sub-routine (high level low-level), address slave being addressed must loaded using either "LOAD_ADDR_8" (for 7-bit address slaves) "LOAD_ADDR_10" macro (for 10-bit address slaves). These macros only load address slaves following operations, also setup conditions 10-bit addressing modes. macros section more details.
HARDWARE
pins used emulate Clock Line, SCL, Data Line, SDA. example test program, used line line. initialization, these lines configured input pins (tri-state) their respective latches loaded with '0's. emulate high state (passive), these lines configured inputs. emulate active state, pins configured outputs (with assumption having external pull-up resistors both lines). devices that have on-chip hardware (SSP module), slope control implemented pins. software implemented pins module, external components slope control required system.
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ROUTINES
Status Register (File Register "Bus_Status")
definitions status register described table given below. These bits reflect status Bus. Name _Bus_Busy _Abort _Txmt_Progress _Rcv_Progress _Txmt_Success _Rcv_Success _Fatal_Error _ACK_Error Start transmitted STOP condition when fatal error condition detected. user must clear this bit. This when clock line, SCL, stuck low. transmission progress reception progress transmission successfully completed error condition reception successfully completed error condition FATAL error occurred (the communication aborted). slave sent while master expecting ACK. This happen example slave responding message. Description
Control Register (File Register "Bus_Control")
definitions control register described table given below. These bits must software prior performing certain operations. Some high level routines described later this section these bits automatically. Name _10BitAddr _Slave_RW _Last_Byte_Rcv _SlaveActive 10-bit slave addressing 7-bit addressing. READ operation WRITE operation. last byte must received. Used send ACK. Unused bits, used general purpose bits. status indicating slave responding. This cleared calling I2C_TEST_DEVICE macro. description this I2C_TEST_DEVICE macro. status indicating clock stretched more than indicating error. this time out, operation aborted. Description
_TIME_OUT_
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Lower Level Routines
Function Name
InitI2CBus_Master TxmtStartBit TxmtStopBit LOAD_ADDR_8 LOAD_ADDR_10 Txmt_Slave_Addr
Description Initializes Control/Status Registers, lines. Must called initialization. Transmits START condition. Transmits STOP condition. 7-bit slave's address must passed constant parameter. 10-bit slave's address must passed constant parameter. Transmits slave address. Prior calling this routine, address slave being addressed must loaded using LOAD_ADDR_8 LOAD_ADDR_10 routines. Also Read/Write condition must control register. Transmits byte data. Prior calling this routine, byte transmitted must loaded into DataByte file register. Receives byte data DataByte file register. data byte received last byte, _Last_Byte_Rcv control register must prior calling this routine.
SendData GetData
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MACROS
High Level
high level routines implemented mixture function calls macros. These high level routines call level routines described previously. most cases only high level routines needed user remove include routines that necessary conserve program memory space. Examples given functions.
I2C_TEST_DEVICE
Parameters Purpose Description None test slave present network. Before using this macro, address slave being tested must loaded using LOAD_ADDR_8 LOAD_ADDR_10 macro. slave under test present, then "_SlaveActive" status Bus_Control file register) set. not, then this cleared, indicating that slave either present network listening. S-SlvAW-A-P
Message Example
LOAD_ADDR_8 I2C_TEST_DEVICE btfss goto
0xA0 _SlaveActive SlaveNotPresent
24LC04 address slave responding 24LC04 present Slave present Continue with program
I2C_WR
Parameters _BYTES_, _SourcePointer_ _BYTES_ Number bytes starting from pointer _SourcePointer_ _SourcePointer_ Data Start Buffer pointer (file registers) basic macro writing block data slave This macro writes block data bytes _BYTES_) slave. starting address block data _SourcePointer_. error occurs, message aborted user must check Status flags (e.g. _Txmt_Success bit) S-SlvAW-A-D[0]-A.A-D[N-1]-A-P
Purpose Description
Message Example
btfsc goto LOAD_ADDR_8 I2C_WR
_Bus_Busy _Slave_1_Addr 0x09, DataBegin
Check free
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I2C_WR_SUB
Parameters _BYTES_, _SourcePointer_, _Sub_Address_ _BYTES_ Number bytes starting from pointer _SourcePointer_ _SourcePointer_ Data Start Buffer pointer (file Registers) _Sub_Address_ Sub-address Slave Write block data slave starting slave's sub-addr Same I2C_WR function, except that starting address slave also specified. example, while writing Memory Device, sub-addr specifies starting address memory. prove more efficient than this macro most situations. Advantages will found Random Address Block Writes Slaves with Auto Increment Sub-addresses (like Microchip's 24CXX series Serial EEPROMs).
LOAD_ADDR_8 I2C_WR_SUB _Slave_2_Addr 0x08, DataBegin+1, 0x30 Load addr 7-bit slave
Purpose Description
Message: Example
above example, Bytes data starting from addr (DataBegin+1) written 24LC04 Serial EEPROM beginning 0x30 address
I2C_WR_SUB_SWINC
Parameters _BYTES_, _SourcePointer_, _Sub_Address_ _BYTES_ Number bytes starting from pointer _SourcePointer_ _SourcePointer_ Data Start Buffer pointer (file Registers) _Sub_Address_ Sub-address Slave Write block data slave starting slave's sub-addr Same I2C_WR_SUB function, except that sub-address (incremented) sent after every data byte. very inefficient message structure given after each data byte. This useful when slave does have auto-increment sub-address feature.
Purpose Description
Message
S-SlvAW-A-(SubA+0)-A-D[0]-A-P S-SlvAW-A-(SubA+1)-A-D[1]-A-P until Bytes
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I2C_WR_BYTE_MEM Parameters _BYTES_, _SourcePointer_, _Sub_Address_ _BYTES_ Number bytes starting from pointer _SourcePointer_ _SourcePointer_ Data Start Buffer pointer (file Registers) _Sub_Address_ Sub-address Slave Write block data slave starting slave's sub-address Same I2C_WR_SUB_SWINC, except that delay added between each message. This necessary some devices, like EEPROMs, which accept only byte time programming (devices without on-chip buffer) after each byte delay necessary before next byte written.
Purpose Description
Message
S-SlvAW-A-(SubA+0)-A-D[0]-A-P Delay S-SlvAW-A-(SubA+1)-A-D[1]-A-P Delay until Bytes
I2C_WR_BUF_MEM Parameters _BYTES_, _SourcePointer_, _Sub_Address_, _Device_BUF_SIZE_ _BYTES_ Number bytes starting from pointer _SourcePointer_ _SourcePointer_ Data Start Buffer pointer (file Registers) _Sub_Address_ Sub-address Slave _Device_BUF_SIZE_ slaves on-chip buffer size Write block data slave starting slave's sub-addr This Macro/Function writes _BYTES_ memory device. However some devices, especially EEPROMs, must wait while device enters into programming mode. some devices have on-chip temperature data hold buffer used store data before device actually enters into programming mode. example, 24C04 series Serial EEPROMs from Microchip have 8-byte data buffer. send bytes data time then device enters programming mode. master either wait until fixed time then retry program continuously poll then transmit next block data programming. I2C_SUB_WR operations performed loop each time data buffer BUF_SIZE output device. Then device checked busy when busy another block data written.
Purpose Description
Message
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I2C_READ
Parameters _BYTES_, _DestPointer_ _BYTES_ Number bytes starting from pointer _SourcePointer_ _DestPointer_ Data Start Buffer pointer (file Registers) basic macro reading block data from slave This macro reads block data (number bytes _BYTES_) from slave. starting address block data _DestPointer_. error occurs, message aborted user must check Status flags (e.g. _Rcv_Success bit). Note that last byte receive, NACK sent. S-SlvAR-A-D[0]-A-.-A-D[N-1]-N-P
Purpose Description
Message Example
LOAD_ADDR_10 I2C_READ_SUB btfss goto goto
_Slave_3_Addr DataBegin _Rcv_Success ReceiveError ReceiveSuccess
example above, bytes data read from 10-bit slave stored master's starting address DataBegin.
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I2C_READ_SUB
Parameters _BYTES_, _DestPointer_, _SubAddress _BYTES_ Number bytes starting from pointer _SourcePointer_ _DestPointer_ Data Start Buffer pointer (file Registers) _SubAddress_ Sub-address slave basic macro reading block data from slave This macro reads block data bytes _BYTES_) from slave starting slave's sub-address _SubAddress. data received stored master's starting address _DestAddress. error occurs, message aborted user must check Status flags (e.g. _Rcv_Success bit). This MACRO/Subroutine reads message from slave device preceded write sub-address between sub-address write following reads, STOP condition issued "REPEATED START" condition used that another master will take over bus, also that other master will overwrite sub-address same slave. This function very commonly used accessing Random/Sequential reads from memory device (e.g., 24CXX serial Serial EEPROMs from Microchip). Message Example
LOAD_ADDR_10 I2C_READ btfss goto goto _Slave_3_Addr DataBegin, 0x60 _Rcv_Success ReceiveError ReceiveSuccess
Purpose Description
example above, bytes data read from 10-bit slave (starting address 0x60h) stored master's starting address DataBegin.
I2C_READ_BYTE I2C_READ_STATUS
Parameters _DestPointer_ _DestPointer_ Data Start Buffer pointer (file Registers) Purpose Description read Status Byte from Slave Several Devices send Status Byte upon reception control byte. This Macro reads Status byte from slave master's location _DestPointer_. This function basically same I2C_READ single byte read. example this command, 24Cxx serial Serial EEPROM from Microchip will send memory data current location when I2C_READ_STATUS function called. successful operation this command, register else register errors.
Message
S-SlvAR-A-D-A-N-P
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I2C_WR_SUB_WR
Parameters _Bytes1_, _SrcPtr1_, _SubAddr_, _Bytes2_, _SrcPtr2_ _Bytes1_ _SrcPtr1_ _SubAddr_ _Bytes2_ _SrcPtr2_ Purpose Description Number bytes first data block Starting address first data block Sub-address slave Number bytes second data block Starting address second data block
send blocks data slave address This Macro writes blocks data variable length) starting slave's sub-address _SubAddr_. This Macro essentially same calling I2C_WR_SUB twice, STOP sent in-between transmission blocks. This given This function useful devices which need blocks data which first block extended address slave device. example, large memory device, teletext device with extended addressing scheme, need multiple bytes data first block that represents actual physical address followed second block that actually represents data.
Message
I2C_WR_SUB_RD
Parameters _Count1_, _SrcPtr_, _SubAddr_, _Count2_, _DestPtr_ _Count1_ _SrcPtr_ _SubAddr_ _Count2_ _DestPtr_ Purpose Description Length source buffer Source pointer address Sub-address slave Length destination buffer Address destination buffer
send block data then receive block data This macro writes block data length _Count1_) slave starting sub-address _SubAddr_ then reads block data length _Count2_) master's destination buffer (starting address _DestPtr_). Although this operation performed using previously defined Macros, this function does give between block writes block reads. This achieved using Repeated Start Condition.
Message
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I2C_WR_COM_WR
Parameters _Count1_, _SrcPtr1_, _Count2_, _SrcPtr2_ _Count1_ _SrcPtr1_ _Count2_ _SrcPtr2_ Purpose Description Length first data block Source pointer first data block Length second data block Source pointer second data block
send blocks data slave message. This macro writes block data length _Count1_) slave then sends another block data length _Count2_) without giving bus. example, this kind transaction used driver where block control address information needed then another block actual data displayed needed.
Message
APPLICATIONS
simple wire serial protocol inter-IC communications. Many peripheral devices (acting slaves) available market with interface (e.g., serial EEPROM, clock/calendar, Port expanders, drivers, converters). Although some PIC16CXXX devices have on-chip hardware interface, high speed throughput microcontroller (250 input clock), implemented using software.
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Please check Microchip latest version source code. Microchip's Worldwide Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership required).
APPENDIX
I2C_TEST.H
I2C_TEST.ASM 4-4-1997 14:47:18 PAGE
MPASM 01.40.01 Intermediate
OBJECT CODE VALUE
LINE SOURCE TEXT
00001 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029 00030 00031 00032 00033 00034
Title SubTitle
"I2C Slave Mode Implemetation" "Rev April 1997"
Slave Mode Using Software Polling Start detected connecting RB0/INT Other bits, including STOP Repeated Start Conditions Software Polled software implemented using PIC16C84 thus ported Enhanced core PIC16CXX products ;RB1 (Any used instead) RB0/INT (Must this START detect when idle mode) Since Slave Mode always Application Dependent, Test Program, PIC16C84 used emulate partial functionality Microchip's 24Cxx Serial EEPROMs Program: I2C_TEST.ASM Revision Date: 1993 4-04-97 Compatibility with MPASMWIN 1.40 #define _MY_ADDRESS 0xD6 This slave's address #define AtoD_Slave #define EE_Slave
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00F42400 003D0900
00000020
00000021
00000008 00000009 00000008 00000009
00000000 00000007
00035 00036 00037 00038 00039 00040 00041 00042 00043 00044 00045 00046 00047 00048 00049 00050 00051 00052 00053 00054 00055 00001 00002 00142 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00001
LIST 16C71 ERRORLEVEL Radix EXPAND _ClkIn _ClkOut ControlByte #define #define #define #define SlvStatus
16000000 (_ClkIn
_STOP _START _ACK
0x20 ControlByte, ControlByte, ControlByte, ControlByte, 0x21
include LIST P16C71.INC LIST _eedata _eeadr _eecon1 _eecon2 #define #define #define #define #define
"p16c71.inc" Microchip Technology, Inc.
Standard Header File, Version 1.00
0x08 0x09 0x08 0x09 _wren _wrerr _eeif
bank _eecon1,0 _eecon1,1 _eecon1,2 _eecon1,3 _eecon1,4
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include "i2c.h" 00002 Header File 00003 00004
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003D0900
00000010 00000012 00000014
0000000C 0000000D 0000000E 0000000F 00000010 00000011 00000012 00000013 00000014 00000015 00000016 00000017 00000018
00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029 00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 00040 00041 00042 00043 00044 00045 00046 00047 00048 00049 00050 00051
_ClkOut
(_ClkIn
Compute delay constants setup hold times _40uS_Delay (_ClkOut/250000) _47uS_Delay (_ClkOut/212766) _50uS_Delay (_ClkOut/200000) #define _OPTION_INIT (0xC0 0x03) #define _SCL PORTB,0 #define _SDA PORTB,1 #define _SCL_TRIS #define _SDA_TRIS #define _WRITE_ #define _READ_ _trisb,0 _trisb,1 Prescaler TMR0 Appox mSec timeout
Register File Variables
CBLOCK
0x0C SlaveAddr SlaveAddrHi DataByte BitCount Bus_Status Bus_Control DelayCount DataByteCopy SubAddr SrcPtr tempCount StoreTemp_1 _End_I2C_Ram
Slave Addr must loaded into this addressing mode load this with data transmitted number (0:7) transmitted received Status both TXMT RCVE control Register
copy DataByte Left Shifts (destructive) sub-address slave (used I2C_HIGH.ASM) source pointer data transmitted temp variable scratch temp variable scratch RAM, disturb contents unused, only allocation
ENDC Status Definitions
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00052 00053 00054 00055 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075
#define #define #define #define #define #define #define #define
_Bus_Busy _Abort _Txmt_Progress _Rcv_Progress _Txmt_Success _Rcv_Success _Fatal_Error _ACK_Error
Bus_Status,0 Bus_Status,1 Bus_Status,2 Bus_Status,3 Bus_Status,4 Bus_Status,5 Bus_Status,6 Bus_Status,7
Control Register #define _10BitAddr Bus_Control,0 #define _Slave_RW Bus_Control,1 #define _Last_Byte_Rcv Bus_Control,2 #define _SlaveActive #define _TIME_OUT_ Bus_Control,6 Bus_Control,7
00076 General Purpose Macros 00077 00078 00079 RELEASE_BUS MACRO 00080 STATUS,RP0 select Bank1 00081 _SDA tristate 00082 _SCL tristate 00083 _Bus_Busy Busy, TEMP ????, set/clear Start Stop 00084 ENDM 00085 00086 00087 MACRO Load Address Address Registers 00088 00089 SLAVE_ADDRESS constant loaded into SlaveAddress Register(s) depending 00090 addressing modes 00091 00092 00093 LOAD_ADDR_10 MACRO SLAVE_ADDRESS 00094
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DS00554C-page 00000018 00000019 0000001A 0000001B 00000020 0000 0000 2815 0004 1997 Microchip Technology Inc. 0004
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00095 00096 00097 00098 00099 00100 00101 00102 00103 00104 00105 00106 00107 00108 00109 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 00095 00096 00097 00098 00099 00100 00101 00102 00103 00104
movlw movwf movlw movwf ENDM LOAD_ADDR_8 MACRO movlw movwf
_10BitAddr (SLAVE_ADDRESS 0xff) SlaveAddr (((SLAVE_ADDRESS 0x06) 0xF0) SlaveAddr+1
Slave address load byte address addr 11110XX0 order address
SLAVE_ADDRESS _10BitAddr Address Mode (SLAVE_ADDRESS 0xff) SlaveAddr
CBLOCK
_End_I2C_Ram SaveStatus SaveW register byteCount HoldData
copy STATUS copy register
ENDC CBLOCK ENDC goto 0x04 Interrupt Service Routine Slave routines, only Rb0/INT interrupt used START Detect From Idle Mode Interrupt: first check START Detect (currently only interrupt enabled, other Interrupts enabled, then check other interrupts) 0x00 Start 0x20 DataBegin
Data read written stored here
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0004 1C8B 0005 0009
0006 0099 0007 0E03 0008 0098 0009 000A 000B 000C 000D 000E 1283 1C06 280F 1886 280F 282A
000F 000F 0010 0011 0012 0E18 0083 0E99 0E19
0013 108B 0014 0009
0015 0015 2019 0016 178B 0017 0017 0064 0018 2817
00105 00106 00107 00108 00109 00110 00111 00112 00113 00114 00115 00116 00117 00118 00119 00120 00121 00122 00123 00124 00125 00126 00127 00128 00129 00130 00131 00132 00133 00134 00135 00136 00137 00138 00139 00140 00141 00142 00143 00144 00145 00146 00147 00148 00149 00150 00151
other interrupt, simply return enable Save Status movwf SaveW register swapf STATUS,W affects STATUS bits Only save STATUS ????? movwf SaveStatus STATUS,RP0 btfss _SCL Most likely START Bit, Hold Time START must valid from here goto RestoreStatus Valid START btfsc _SDA valid Falling Edge when high, must goto RestoreStatus Valid START goto StartBitDetect Valid Start Detected, process then Branch "Restore Status" Restore Status RestoreStatus: swapf movwf swapf swapf retfie Start: call wait: clrwdt goto INTCON,GIE Enable Interrupts Init_I2C_Slave Initialize Slave Mode, wait START detect INTCON,INTF SaveStatus,W STATUS SaveW register, SaveW register,W btfss retfie INTCON,INTF
restore STATUS save register restore register
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wait
User write code here, will interrupted Falling Edge Loop until Start Detect
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0019 0019 001A 001B 001C 001D 001E 001F 0020 0021 0022 01A0 1683 30C3 0081 1406 1486 1283 0806 39FC 0086
0023 0194
0024 0189 0025 1683 0026 0188
0027 018B 0028 160B 0029 0008
002A 002A 2045 002B 0064 002C 1820
00152 00153 00154 00155 00156 00157 00158 00159 00160 00161 00162 00163 00164 00165 00166 00167 00168 00169 00170 00171 00172 00173 00174 00175 00176 00177 00178 00179 00180 00181 00182 00183 00184 00185 00186 00187 00188 00189 00190 00191 00192 00193 00194 00195 00196 00197 00198
Init_I2C_Slave: clrf movlw movwf movf andlw movwf ControlByte STATUS,RP0 _OPTION_INIT OPTION_REG _SCL _SDA STATUS,RP0 PORTB,W 0xFC PORTB
initially Falling Edge TRIS inputs, pulled external resistors
Port Pins zero. From simply play with tris
clrf SubAddr Address Zero Initialize Setup EEPROM Control Regs ;#if AtoD_Slave ;#else
movlw movwf clrf clrf clrf
0x01 _adcon0 STATUS,RP0 _adcon1 _eeadr STATUS,RP0 _eecon1
Select Channel turn Module with Fosc/2 Sampling Rate already Bank0, STATUS,RP0 analog channels with internal Vref already Bank0, init EEPROM Addr clear flag
;#endif clrf return INTCON INTCON,INTE Enable Falling Edge Interrupt (connected RB0/INT pin)
In-Line Code I2C-Slave Returns detect next Start after STOP Detected This implementation very in-efficient Master constantly sending Repeated START Condition StartBitDetect: call clrwdt btfsc RcvByte _STOP byte received DataByte
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002D 283F 002E 18A0 002F 282A
0030 0031 0032 0033 0034 0035 0036 0037
1120 180E 1520 100E 080E 3AD6 1D03 283D
0038 0039 003A 003B 003C
1403 20B3 1920 287B 2867
003D 003D 1003 003E 20B3 003F 003F 0040 0041 0042 0043 0044
0064 1683 108B 1406 1486 280F
0045 0045 01A1 0046 3008
00199 00200 00201 00202 00203 00204 00205 00206 00207 00208 00209 00210 00211 00212 00213 00214 00215 00216 00217 00218 00219 00220 00221 00222 00223 00224 00225 00226 00227 00228 00229 00230 00231 00232 00233 00234 00235 00236 00237 00238 00239 00240 00241 00242 00243 00244 00245
Repeated START condition received byte DataByte contains Address address address match send else NACK btfsc DataByte,LSB byte received contains info DataByte,LSB movf xorlw btfss goto DataByte,W _MY_ADDRESS STATUS,Z SendNACK
goto btfsc goto
i2c_start_wait _START StartBitDetect
STOP Detected, wait another START
match, then Address Match, NACK
Address Match Occured, send call btfsc goto goto STATUS,C SendAck SendReqData RcvReqData SendAck routine sends Carry
read operation, send current Data receive bytes data, sub-addr data byte
SendNACK: STATUS,C SendAck routine sends NACK Carry call SendAck address wait another start i2c_start_wait: clrwdt STATUS,RP0 INTCON,INTF _SCL release line, held _SDA release goto RestoreStatus Receive Byte Data RcvByte: clrf movlw SlvStatus 0x08
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0047 008F 0048 1283 0049 1806 004A 2849 004B 1683 004C 1406 004D 1283 004E 004E 004F 0050 0051 0052 0052 0053 0054 0054 0055 0056 0057 0058 0059 005A 005A 005B 005C 005C 005D 005E 005F 0060 0061
1C06 284E 1886 285A 1003 0D8E 1C06 2862 1C86 2854 1420 0008
1403 0D8E 1C06 2862 1886 285C 14A0 0008
0062 0062 0B8F 0063 284E
0064 1683 0065 1006 0066 0008
00246 00247 00248 00249 00250 00251 00252 00253 00254 00255 00256 00257 00258 00259 00260 00261 00262 00263 00264 00265 00266 00267 00268 00269 00270 00271 00272 00273 00274 00275 00276 00277 00278 00279 00280 00281 00282 00283 00284 00285 00286 00287 00288 00289 00290 00291 00292
movwf btfsc goto RcvNextBit: btfss goto btfsc goto Rcvd_0: _WaitClkLo1: btfss goto btfss goto return Rcvd_1: _WaitClkLo2: btfss goto btfsc goto return next1: decfsz goto
BitCount STATUS,RP0 _SCL STATUS,RP0 _SCL STATUS,RP0
wait until then Read Control Byte
release CLK, possibly held
_SCL _SDA Rcvd_1 STATUS,C DataByte, _SCL next1 _SDA _WaitClkLo1 _STOP
wait until clock high, valid data
left shift data first)
must still when high, else STOP
STATUS,C DataByte, _SCL next1 _SDA _WaitClkLo2 _START
went low, process next must still high when high, else Repeated START
BitCount, RcvNextBit
complete Byte Received, HOLD Master's Clock Line force wait state STATUS,RP0 _SCL force wait state return
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0067 0067 0068 0069 006A 006B 006C 006D 006E 006F 0070
2045 080E 0094 0064 1820 283F 18A0 282A 1403 20B3
0071 0072 0073 0074 0075 0076 0077 0078 0079 007A
2045 0064 1820 283F 18A0 282A 1403 20B3 20CD 280F
007B 007B 1283 007C 0814 007D 0089
007E
00293 00294 00295 00296 00297 00298 00299 00300 00301 00302 00303 00304 00305 00306 00307 00308 00309 00310 00311 00312 00313 00314 00315 00316 00317 00318 00319 00320 00321 00322 00323 00324 00325 00326 00327 00328 00329 00330 00331 00332 00333 00334 00335 00336 00337 00338 00339
Write Operation Requested Read Address Data Byte Acknowledge, errors Currently Only Byte Programmed Time, Buffering scheme unimplemented RcvReqData call movf movwf clrwdt btfsc goto btfsc goto call RcvByte DataByte,W SubAddr _STOP i2c_start_wait _START StartBitDetect STATUS,C SendAck Sub-Address Byte Received DataByte, store Sub-Addr
STOP Detected, wait another START Repeated START condition SendAck routine sends Carry Sub-Addr Received, Send
Receive Data Byte Write EEPROM call RcvByte clrwdt btfsc _STOP goto i2c_start_wait btfsc _START goto StartBitDetect STATUS,C call SendAck call EEpromWrite goto RestoreStatus
Sub-Address Byte Received DataByte, store Sub-Addr
STOP Detected, wait another START Repeated START condition SendAck routine sends Carry Sub-Addr Received, Send Program EEPROM STOP Detected, wait another START
Read Operation Requested Send Data Required Channel until NACK Master SendReqData:
AN554
movf movwf SendNextByte:
STATUS,RP0 SubAddr,W _eeadr
Load Sub_Addr EEPRO
DS00554C-page 1997 Microchip Technology Inc.
AN554
007E 007F 0080 0081 0082 0083 0084 0085 0086 0087 0088 0089 008A 008B 008C
1683 1408 1283 0808 008E 0A89 208D 0064 18A0 283F 20C0 0064 1DA0 283F 287E
008D 008D 008E 008F 0090 0091
080E 0093 3008 008F 01A1
0092 0092 1683 0093 0D93 0094 0095 0096 0096 0097 0098 0099 009A 009B 009C 009D 009E 009F 00A0 1803 28A1 1086 0000 1406 1283 1C06 289A 1806 289C 1683 1006 28AD
00A1
00340 00341 00342 00343 00344 00345 00346 00347 00348 00349 00350 00351 00352 00353 00354 00355 00356 00357 00358 00359 00360 00361 00362 00363 00364 00365 00366 00367 00368 00369 00370 00371 00372 00373 00374 00375 00376 00377 00378 00379 00380 00381 00382 00383 00384 00385 00386
movf movwf incf call clrwdt btfsc goto call clrwdt btfss goto goto
STATUS,RP0 STATUS,RP0 _eedata,W DataByte _eeadr, TxmtByte _START i2c_start_wait ReadACK
read EEPRO
DataByte EEPROM(addr) auto-increment sub-address send EEPROM Data check abnormal START
_ACK _ACK Rcvd i2c_start_wait NACK Received, START STOP condition occur SendNextByte continue send until NACK
TxmtByte: movf movwf movlw movwf clrf TxmtNextBit: btfsc goto Txmt_0 btfss goto btfsc goto goto _SDA _SCL STATUS,RP0 _SCL _SCL STATUS,RP0 _SCL Q_TxmtNextBit release clock line, master pull high STATUS,RP0 DataByteCopy, First STATUS,C Txmt_1 DataByte,W DataByteCopy 0x08 BitCount SlvStatus make copy DataByte
wait until goes high wait until goes went low, continue hold
Txmt_1
1997 Microchip Technology Inc. DS00554C-page
00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A7 00A8 00A9 00AA
1486 0000 1406 1283 1C06 28A5 1C86 28B1 1806 28A7
00AB 1683 00AC 1006 00AD 00AD 00AE 00AF 00B0
0B8F 2892 1486 0008
00B1 00B1 14A0 00B2 0008
00B3 00B3 00B4 00B5 00B6 00B7 00B8 00B9 00BA 00BB 00BC 00BD 00BE
1683 1803 1086 1406 1283 1C06 28B8 1806 28BA 1683 1006 1486
00387 00388 00389 00390 00391 00392 00393 00394 00395 00396 00397 00398 00399 00400 00401 00402 00403 00404 00405 00406 00407 00408 00409 00410 00411 00412 00413 00414 00415 00416 00417 00418 00419 00420 00421 00422 00423 00424 00425 00426 00427 00428 00429 00430 00431 00432 00433
btfss goto _IsClkLo_1 btfss goto btfsc goto Q_TxmtNextBit decfsz goto return MayBeErr_Txmt: return
_SDA _SCL STATUS,RP0 _SCL _SDA MayBeErr_Txmt _SCL _IsClkLo_1 STATUS,RP0 _SCL release clock line, master pull high
wait until goes high
must never come here, illegal Repeated Start wait until goes
went low, continue hold
BitCount, TxmtNextBit _SDA
release Master's
_START
illegal Repeated START condition during byte transfer
Send ACK/NACK Master Prior calling this routine, CARRY sending CARRY NACK SendAck: btfsc btfss goto btfsc goto STATUS,RP0 STATUS,C _SDA _SCL STATUS,RP0 _SCL _SCL STATUS,RP0 _SCL _SDA Carry else NACK pull send release line, master
loop until High
AN554
loop until Low, sent HOLD Line over, release line Master control
DS00554C-page 1997 Microchip Technology Inc.
AN554
00BF 0008
00C0 00C0 00C1 00C2 00C3 00C4 00C5 00C6 00C7 00C8 00C9 00CA 00CB 00CC
1683 1406 1283 1C06 28C3 15A0 1886 11A0 1806 28C8 1683 1006 0008
00CD 00CD 00CE 00CF 00D0 00D1 00D2 00D3 00D4 00D5 00D6 00D7 00D8 00D9
1283 0814 0089 080E 0088 1683 1508 1188 3055 0089 30AA 0089 1488
00DA 1406 00DB 1486 00DC 0064 00DD 1888
00434 00435 00436 00437 00438 00439 00440 00441 00442 00443 00444 00445 00446 00447 00448 00449 00450 00451 00452 00453 00454 00455 00456 00457 00458 00459 00460 00461 00462 00463 00464 00465 00466 00467 00468 00469 00470 00471 00472 00473 00474 00475 00476 00477 00478 00479 00480
return Read Sent Master then _ACK SlaveStatus Reg, else ReadACK: STATUS,RP0 _SCL release clock STATUS,RP0 btfss _SCL goto wait until clock high bit:ACK) _ACK expecting btfsc _SDA _ACK NACK rcvd, stop transmission btfsc _SCL goto wait until Clock STATUS,RP0 _SCL force Clock return Write Byte Data EEPROM Array Sub-Addr EEpromWrite: STATUS,RP0 movf SubAddr,W movwf _eeadr load sub-address movf DataByte,W movwf _eedata load data written into EEDATA STATUS,RP0 _wren enable write operation _wrerr clear previous error flags movlw 0x55 movwf _eecon2 movlw 0xAA movwf _eecon2 start Write Operation _SCL release line, held _SDA release clrwdt btfsc Poll until Over
1997 Microchip Technology Inc. DS00554C-page
00DE 28DC 00DF 1108 00E0 0064 00E1 108B 00E2 0008
00481 goto 00482 00483 _wren disable write operations 00484 clrwdt 00485 INTCON,INTF 00486 00487 return 00488 00489 00490 00491 Unused)
MEMORY USAGE (`X' Used,
0000 0040 0080 00C0
X-XXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXX-
XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
other memory blocks unused. Program Memory Words Used: Program Memory Words Free:
Errors Warnings Messages
reported, reported,
suppressed suppressed
AN554
DS00554C-page 1997 Microchip Technology Inc.
AN554
Please check Microchip latest version source code. Microchip's Worldwide Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership required).
APPENDIX
TEST.ASI2CTEST.ASM 4-4-1997 14:45:51 PAGE
MPASM 01.40.01 Intermediate
OBJECT CODE VALUE
LINE SOURCE TEXT
00F42400
00001 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029 00030 00031 00001 00002 00142
Title SubTitle
"I2C Master Mode Implemetation" "Rev April 1997"
Software Implementation Master Mode Master Transmitter Master Receiver Implemented software Slave Mode implemented hardware Refer Signetics/Philips I2C-Bus Specification software implemented using PIC16C71 thus ported Enhanced core PIC16CXX product (Any used instead) RB0/INT (Any used instead) Program: I2CTEST.ASM Revision Date: 1993 4-04-97 Compatibility with MPASMWIN 1.40 LIST 16C71 ERRORLEVEL -302 Radix _ClkIn include LIST P16C71.INC LIST 16000000 Input Clock Frequency PIC16C71 <p16c71.inc> Microchip Technology, Inc.
Standard Header File, Version 1.00
1997 Microchip Technology Inc. DS00554C-page
00000001 00000000 00000000 00000007
003D0900
00000010 00000012 00000014
00032 00033 00034 00035 00036 00037 00038 00039 00040 00041 00042 00043 00044 00045 00046 00047 00048 00049 00001 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029
TRUE FALSE
#define _Slave_1_Addr #define _Slave_2_Addr #define _Slave_3_Addr
0xA0 0xAC 0xD6
Serial EEPROM Serial EEPROM Slave PIC16CXX
#define _ENABLE_BUS_FREE_TIME TRUE #define _CLOCK_STRETCH_CHECK TRUE #define _INCLUDE_HIGH_LEVEL_I2C TRUE
include "i2c.h" Header File _ClkOut (_ClkIn
Compute delay constants setup hold times _40uS_Delay (_ClkOut/250000) _47uS_Delay (_ClkOut/212766) _50uS_Delay (_ClkOut/200000) #define _OPTION_INIT (0xC0 0x03) #define _SCL PORTB,0 #define _SDA PORTB,1 #define _SCL_TRIS #define _SDA_TRIS #define _WRITE_ #define _READ_ _trisb,0 _trisb,1 Prescaler TMR0 Appox mSec timeout
AN554
Register File Variables
CBLOCK
0x0C
DS00554C-page 1997 Microchip Technology Inc.
AN554
0000000C 0000000D 0000000E 0000000F 00000010 00000011 00000012 00000013 00000014 00000015 00000016 00000017 00000018
00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 00040 00041 00042 00043 00044 00045 00046 00047 00048 00049 00050 00051 00052 00053 00054 00055 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076
SlaveAddr SlaveAddrHi DataByte BitCount Bus_Status Bus_Control DelayCount DataByteCopy SubAddr SrcPtr tempCount StoreTemp_1 _End_I2C_Ram ENDC
Slave Addr must loaded into this addressing mode load this with data transmitted number (0:7) transmitted received Status both TXMT RCVE control Register
copy DataByte Left Shifts (destructive) sub-address slave (used I2C_HIGH.ASM) source pointer data transmitted temp variable scratch temp variable scratch RAM, disturb contents unused, only allocation
Status Definitions #define #define #define #define #define #define #define #define _Bus_Busy _Abort _Txmt_Progress _Rcv_Progress _Txmt_Success _Rcv_Success _Fatal_Error _ACK_Error Bus_Status,0 Bus_Status,1 Bus_Status,2 Bus_Status,3 Bus_Status,4 Bus_Status,5 Bus_Status,6 Bus_Status,7
Contro Register #define _10BitAddr Bus_Control,0 #define _Slave_RW Bus_Control,1 #define _Last_Byte_Rcv Bus_Control,2 #define _SlaveActive #define _TIME_OUT_ Bus_Control,6 Bus_Control,7
General Purpose Macros
1997 Microchip Technology Inc. 00000018 00000019 0000001A 0000001B DS00554C-page 00000020 0000
00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 00095 00096 00097 00098 00099 00100 00101 00102 00103 00104 00105 00106 00107 00108 00109 00050 00051 00052 00053 00054 00055 00056 00057 00058 00059 00060 00061 00062 00063
RELEASE_BUS MACRO ENDM MACRO Load Address Address Registers SLAVE_ADDRESS constant loaded into SlaveAddress Register(s) depending addressing modes LOAD_ADDR_10 MACRO movlw movwf movlw movwf ENDM LOAD_ADDR_8 MACRO movlw movwf ENDM CBLOCK _End_I2C_Ram SaveStatus SaveW register byteCount HoldData SLAVE_ADDRESS _10BitAddr Address Mode (SLAVE_ADDRESS 0xff) SlaveAddr SLAVE_ADDRESS _10BitAddr Slave address (SLAVE_ADDRESS 0xff) SlaveAddr load byte address (((SLAVE_ADDRESS 0x06) 0xF0) addr 11110XX0 SlaveAddr+1 order address STATUS,RP0 _SDA _SCL _Bus_Busy select Bank1 tristate tristate Busy, TEMP ????, set/clear Start Stop
copy STATUS copy register
ENDC
AN554
CBLOCK ENDC
0x20 DataBegin
Data read written stored here
0x00
DS00554C-page 1997 Microchip Technology Inc.
AN554
0000 2956 0004
0004
0004 0099 0005 0E03 0006 0098 0007 0008 0009 000A 1D0B 280B 1791 110B
000B 000B 0000 000C 000C 000D 000E 000F 0010
0E18 0083 0E99 0E19 0009
00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 00095 00096 00097 00098 00099 00100 00101 00102 00103 00104 00105 00106 00107 00108 00001 00002
goto
Start
0x04 Interrupt Service Routine routines, only TMR0 interrupt used TMR0 Interrupts enabled only Clock Stretching Used TMR0 timeout interrupt, disable TMR0 Interrupt, clear pending flags, MUST _TIME_OUT_ flag saying possibly FATAL error occurred user choose retry operation again later Interrupt: Save Interrupt Status register STATUS regs) movwf SaveW register Save register swapf STATUS,W affects STATUS bits Only save STATUS ????? movwf SaveStatus Save STATUS _CLOCK_STRETCH_CHECK TMR0 Interrupts enabled only Clock Stretching Used btfss INTCON,T0IF goto MayBeOtherInt other Interrupts _TIME_OUT_ MUST this Flag, take other desired actions here INTCON,T0IF endif Check Other Interrupts Here, This program usesd only TMR0 Interrupt MayBeOtherInt: RestoreIntStatus: Restore Interrupt Status swapf SaveStatus,W movwf STATUS restore STATUS swapf SaveW register, swapf SaveW register,W restore register retfie Include High Level Level Routines _INCLUDE_HIGH_LEVEL_I2C include "i2c_high.inc"
1997 Microchip Technology Inc. DS00554C-page
00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029 00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 00040 00041 00042 00043 00044 00045 00046 00047 00048 00049
Master General Purpose Macros Subroutines High Level Routines, Uses level Routines I2C_LOW.ASM) Program: I2C_HIGH.ASM Revision Date: 1-16-97 Compatibility with MPASMWIN 1.40
I2C_TEST_DEVICE MACRO Slave Device listening, then _SlaveActive set, else cleared Parameter NONE Sequence Operations S-SlvAW-A-P device listening, else either busy, present error condition This test also used check eample Serial EEPROM internal programming mode NOTE address slave must loaded into SlaveAddress Registers, mode addressing must I2C_TEST_DEVICE MACRO call ENDM IsSlaveActive TEMP ???? Assembler Error with this MACRO
Test Device SlaveAddr Present
AN554
Slave Address present, NACK present maybe device responding. presense checked constantly master (for Operating System Access.Bus constantly issue this command) Assume Slave Address bit) loaded SlaveAddr _10BitAddr Control Address slave else
DS00554C-page 1997 Microchip Technology Inc.
AN554
0011 0011 1091 0012 2057 0013 206B 0014 0015 0016 0017 0018 1311 1F90 1711 205F 0008
00050 00051 00052 00053 00054 00055 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 00095 00096
Returns
_SlaveActive slave responding else
IsSlaveActive call call btfss call return _SlaveActive _ACK_Error _SlaveActive TxmtStopBit skip NACK, device present responding received, device present listening _Slave_RW write operation TxmtStartBit send START Txmt_Slave_Addr successful, then _Txmt_Success
I2C_WRITE basic macro writing block data slave Parameters _BYTES_ bytes starting from pointer _SourcePointer_ _SourcePointer_ Data Start Buffer pointer (file Registers) Sequence S-SlvAW-A-D[0]-A.A-D[N-1]-A-P error occurs then routine simply returns user should check flags Bus_Status (for _Txmt_Success flag) NOTE address slave must loaded into SlaveAddress Registers, mode addressing must
I2C_WR
MACRO movlw movwf movlw movwf call call
_BYTES_, _SourcePointer_ _BYTES_ tempCount _SourcePointer_ _i2c_block_write TxmtStopBit Issue stop slave transmission
1997 Microchip Technology Inc. DS00554C-page
0019 0019 2057 001A 1091 001B 206B 001C 001C 001D 001E 001F 0020 0021 0022 0023 0024
1E10 0008 0800 008E 0A84 2095 0B96 281C 0008
00097 00098 00099 00100 00101 00102 00103 00104 00105 00106 00107 00108 00109 00110 00111 00112 00113 00114 00115 00116 00117 00118 00119 00120 00121 00122 00123 00124 00125 00126 00127 00128 00129 00130 00131 00132 00133 00134 00135 00136 00137 00138 00139 00140 00141 00142 00143
_i2c_block_write: call TxmtStartBit send START _Slave_RW write operation call Txmt_Slave_Addr successful, then _Txmt_Success _block_wr1_loop: btfss _Txmt_Success return movf INDF,W movwf DataByte start from first byte starting _DataPointer_ incf FSR, call SendData send next byte, our's decfsz tempCount, goto _block_wr1_loop loop until desired bytes data transmitted slave return I2C_WRITE_SUB Writes message just like I2C_WRITE, except that data preceeded sub-address slave device. serial EEPROM would need address memory location Random Writes Parameters _BYTES_ bytes starting from pointer _SourcePointer_ (constant) _SourcePointer_ Data Start Buffer pointer (file Registers) _Sub_Address_ Sub-address Slave (constant) Sequence error occurs then routine simply returns user should check flags Bus_Status (for _Txmt_Success flag Returns register success, else register NOTE address slave must loaded into SlaveAddress Registers, mode addressing must COMMENTS I2C_WR prove more efficient than this macro most situations Advantages will found Random Address Block Writes Slaves with Auto Increment Sub-Addresses (like Microchip's 24CXX series Serial EEPROMS)
AN554
DS00554C-page 1997 Microchip Technology Inc.
AN554
00144 00145 00146 00147 00148 00149 00150 00151 00152 00153 00154 00155 00156 00157 00158 00159 00160 00161 00162 00163 00164 00165 00166 00167 00168 00169 00170 00171 00172 00173 00174 00175 00176 00177 00178 00179 00180 00181 00182 00183 00184 00185 00186 00187 00188 00189 00190
I2C_WR_SUB MACRO movlw movwf movlw movwf movf movwf movlw movwf call movf movwf call ENDM I2C_WR_SUB_SWINC Parameters _BYTES_ bytes starting from pointer _SourcePointer_ (constant) _SourcePointer_ Data Start Buffer pointer (file Registers) _Sub_Address_ Sub-address Slave (constant) Sequence S-SlvAW-A-(SubA+0)-A-D[0]-A-P S-SlvAW-A-(SubA+1)-A-D[1]-A-P until Bytes error occurs then routine simply returns user should check flags Bus_Status (for _Txmt_Success flag Returns register success, else register COMMENTS Very In-efficient, given after every Byte Write Some devices addresed with sub-address increment automatically after access each byte. Thus block data sent must have sub-address followed data byte. _BYTES_, _SourcePointer_, _Sub_Address_ (_BYTES_ tempCount (_SourcePointer_ INDF,W StoreTemp_1 _Sub_Address_ INDF
temporarily store contents (_SourcePointer_ store temporarily sub-address (_SourcePointer_ write _BYTES_+1 block data
_i2c_block_write StoreTemp_1,W (_SourcePointer_ TxmtStopBit
restore contents (_SourcePointer_
Issue stop slave transmission
1997 Microchip Technology Inc. 0025 0025 0026 0027 0028 0029 002A 002B 002C 002D 002E 002F 0030 0031 0032 0033 0034 2057 1091 206B 1E10 2835 0814 008E 2095 1E10 2835 0815 008E 2095 1E10 2835 2837 DS00554C-page 0035
00191 00192 00193 00194 00195 00196 00197 00198 00199 00200 00201 00202 00203 00204 00205 00206 00207 00208 00209 00210 00211 00212 00213 00214 00215 00216 00217 00218 00219 00220 00221 00222 00223 00224 00225 00226 00227 00228 00229 00230 00231 00232 00233 00234 00235 00236 00237
I2C_WR_SUB_SWINC MACRO _BYTES_, _SourcePointer_, _Sub_Address_ TEMP ???? Assembler Does Support This
variable
while _BYTES_) movf (_Source_Pointer_ i),W movwf SrcPtr movf (_Sub_Address_ i),W movwf SubAddr call _i2c_byte_wr_sub write byte data address endw ENDM
Write Byte Data SrcPtr) slave sub-address (SubAddr)
_i2c_byte_wr_sub: call call btfss goto movf movwf call btfss goto movf movwf call btfss goto goto return back called _block_wr1_fail:
TxmtStartBit _Slave_RW Txmt_Slave_Addr _Txmt_Success _block_wr1_fail SubAddr,W DataByte SendData _Txmt_Success _block_wr1_fail SrcPtr,W DataByte SendData _Txmt_Success _block_wr1_fail _block_wr1_pass
send START write operation successful, then _Txmt_Success start from first byte starting _DataPointer_ send next byte start from first byte starting _DataPointer_ send next byte
AN554
failed, return register successful, return register
routine from either _block_wr1_pass _block_wr1_fail
DS00554C-page 1997 Microchip Technology Inc.
AN554
0035 0036 0037 0037 0038
205F 3400 205F 3401
00238 00239 00240 00241 00242 00243 00244 00245 00246 00247 00248 00249 00250 00251 00252 00253 00254 00255 00256 00257 00258 00259 00260 00261 00262 00263 00264 00265 00266 00267 00268 00269 00270 00271 00272 00273 00274 00275 00276 00277 00278 00279 00280 00281 00282 00283 00284
call retlw _block_wr1_pass: call retlw
TxmtStopBit FALSE TxmtStopBit TRUE
Issue stop slave transmission
Issue stop slave transmission
I2C_WR_MEM_BYTE Some devices like EEPROM need wait some time after every byte write (when entered into internal programming mode). This MACRO same I2C_WR_SUB_SWINC, addition adds delay after each byte. Some EERPOM memories (like Microchip's 24Cxx Series have on-chip data buffer), hence this routine efficient these cases. such cases I2C_WR I2C_WR_SUB block data then insert delay until whole buffer written. Parameters _BYTES_ bytes starting from pointer _SourcePointer_ (constant) _SourcePointer_ Data Start Buffer pointer (file Registers) _Sub_Address_ Sub-address Slave (constant) Sequence S-SlvAW-A-(SubA+0)-A-D[0]-A-P Delay mSec user chnage this value desired delay S-SlvAW-A-(SubA+1)-A-D[1]-A-P Delay mSec until Bytes I2C_WR_BYTE_MEM MACRO _BYTES_, _SourcePointer_, _Sub_Address_ TEMP ???? Assembler Does Support This
variable
while _BYTES_) movf (_Source_Pointer_ i),W movwf SrcPtr movf (_Sub_Address_ i),W movwf SubAddr call _i2c_byte_wr_sub write byte data address call Delay50uSec
1997 Microchip Technology Inc. DS00554C-page
00285 00286 00287 00288 00289 00290 00291 00292 00293 00294 00295 00296 00297 00298 00299 00300 00301 00302 00303 00304 00305 00306 00307 00308 00309 00310 00311 00312 00313 00314 00315 00316 00317 00318 00319 00320 00321 00322 00323 00324 00325 00326 00327 00328 00329 00330 00331
endw
ENDM I2C_WR_MEM_BUF This Macro/Function writes _BYTES_ memory device. However some devices, esp. EEPROMs must wait while device enters into programming mode. some devices have onchip temp data hold buffer used store data before device actually enters into programming mode. example, 24C04 series Serial EEPROMs from Microchip have byte data buffer. send bytes data time then device enters programming mode. master either wait until fixed time then retry program continiously poll then transmit next Block data programming Parameters _BYTES_ bytes write memory _SourcePointer_ Pointer block data _SubAddress_ Sub-address slave _Device_BUF_SIZE_ chip buffer size slave Sequence operations I2C_SUB_WR operations performed loop each time data buffer BUF_SIZE output device. Then device checked busy when busy another block data written I2C_WR_BUF_MEM MACRO _BYTES_, _SourcePointer_, _SubAddress_, _Device_BUF_SIZE_
variable
!_BYTES_) exitm elif _BYTES_ I2C_WR_SUB exitm _Device_BUF_SIZE_) _BYTES_, _SourcePointer_, _SubAddress_
AN554
DS00554C-page 1997 Microchip Technology Inc.
AN554
00332 00333 00334 00335 00336 00337 00338 00339 00340 00341 00342 00343 00344 00345 00346 00347 00348 00349 00350 00351 00352 00353 00354 00355 00356 00357 00358 00359 00360 00361 00362 00363 00364 00365 00366 00367 00368 00369 00370 00371 00372 00373 00374 00375 00376 00377 00378
else (_BYTES_ _Device_BUF_SIZE_) while I2C_WR_SUB _Device_BUF_SIZE_, (_SourcePointer_ i*_Device_BUF_SIZE_) call btfss goto endw (_BYTES_ i*_Device_BUF_SIZE_) I2C_WR_SUB (_SourcePointer_ i*_Device_BUF_SIZE_), (_SubAddress_ endif endif ENDM IsSlaveActive _SlaveActive
i*_Device_BUF_SIZE_)
I2C_READ basic MACRO/procedure read block message from slave device Parameters _BYTES_ constant bytes receive _DestPointer_ destination pointer (File Registers) Sequence S-SlvAR-A-D[0]-A-.-A-D[N-1]-N-P last byte, then Master will Acknowledge (send NACK) NOTE address slave must loaded into SlaveAddress Registers, mode addressing must
1997 Microchip Technology Inc. DS00554C-page
0039 0039 003A 003B 003C 003D 003E 003F 0040 0041 0041 0042 0043 0044 0045 0046 0047 0048 0049 004A 004B 004C
2057 1491 1111 206B 1A10 2841 205F 3400
20CC 080E 0080 0A84 0B96 2841 1511 20CC 080E 0080 205F 3401
00379 00380 00381 00382 00383 00384 00385 00386 00387 00388 00389 00390 00391 00392 00393 00394 00395 00396 00397 00398 00399 00400 00401 00402 00403 00404 00405 00406 00407 00408 00409 00410 00411 00412 00413 00414 00415 00416 00417 00418 00419 00420 00421 00422 00423 00424 00425
I2C_READ
MACRO
_BYTES_, _DestPointer_
movlw movwf movlw movwf call ENDM _i2c_block_read: call call btfsc goto call retlw _block_rd1_loop: call movf movwf incf decfsz goto call movf movwf call retlw
(_BYTES_ tempCount _DestPointer_ _i2c_block_read
because, last byte used loop FIFO destination address pointer
TxmtStartBit _Slave_RW _Last_Byte_Rcv Txmt_Slave_Addr _Txmt_Success _block_rd1_loop TxmtStopBit FALSE
send START read operation last byte successful, then _Txmt_Success
Issue stop slave transmission Error device responding
GetData DataByte,W INDF FSR, tempCount, _block_rd1_loop _Last_Byte_Rcv GetData DataByte,W INDF TxmtStopBit TRUE
start receiving data, starting Destination Pointer
loop until desired bytes data transmitted slave last byte rcv, send NACK
Issue stop slave transmission
I2C_READ_SUB This MACRO/Subroutine reads message from slave device preceeded write sub-address Between sub-address write following reads, STOP condition issued "REPEATED START" condition used that other master will take over bus, also that other master will overwrite sub-address same slave. This function very commonly used accessing Random/Sequential reads from memory device (e.g 24Cxx serial Serial EEPROMs from Microchip).
AN554
DS00554C-page 1997 Microchip Technology Inc.
AN554
00426 00427 00428 00429 00430 00431 00432 00433 00434 00435 00436 00437 00438 00439 00440 00441 00442 00443 00444 00445 00446 00447 00448 00449 00450 00451 00452 00453 00454 00455 00456 00457 00458 00459 00460 00461 00462 00463 00464 00465 00466 00467 00468 00469 00470 00471 00472
Parameters _BYTES_ bytes read _DestPointer_ destination pointer data received. _BubAddress_ sub-address slave Sequence I2C_READ_SUB MACRO call call movlw movwf call _BYTES_, _DestPointer_, _SubAddress_ _Slave_RW write operation TxmtStartBit send START Txmt_Slave_Addr successful, then _Txmt_Success _SubAddress_ DataByte SendData
START address EEPROM(slave write address
send STOP after this, REPEATED START condition I2C_READ _BYTES_, _DestPointer_
I2C_READ_STATUS This Macro/Function reads status word byte) from slave. Several devices send status byte upon reception control byte This basically same I2C_READ MACRO reading single byte example, Serial EEPROM (Microchip's 24Cxx serial EEPROMs) will send memory data current address location success register else
1997 Microchip Technology Inc. DS00554C-page
00473 00474 00475 00476 00477 00478 00479 00480 00481 00482 00483 00484 00485 00486 00487 00488 00489 00490 00491 00492 00493 00494 00495 00496 00497 00498 00499 00500 00501 00502 00503 00504 00505 00506 00507 00508 00509 00510 00511 00512 00513 00514 00515 00516 00517 00518 00519
I2C_READ_STATUS MACRO
_DestPointer_
call call btfsc goto call retlw _byte_rd1_loop: call movf movwf call btfss retlw retlw
TxmtStartBit _Slave_RW Txmt_Slave_Addr _Txmt_Success _byte_rd1_loop TxmtStopBit FALSE _Last_Byte_Rcv GetData DataByte,W _DestPointer_ TxmtStopBit _Rcv_Success FALSE TRUE
send START read operation successful, then _Txmt_Success read byte Issue stop slave transmission Error device responding last byte rcv, send NACK
Issue stop slave transmission
I2C_READ_BYTE MACRO _DestPointer_ _DestPointer_
I2C_READ_STATUS MACRO
I2C_WR_SUB_WR This Macro writes Blocks Data (variable length) slave sub-address. This useful devices which need blocks data which first block extended address slave device. example, large memory device, teletext device with extended addressing scheme, need multiple bytes data block that represents actual physical address followed block that actually represents data. Parameters _BYTES1_ block bytes _SourcePointer1_ Start Pointer block _SubAddress_ Sub-Address slave
AN554
DS00554C-page 1997 Microchip Technology Inc.
AN554
00520 00521 00522 00523 00524 00525 00526 00527 00528 00529 00530 00531 00532 00533 00534 00535 00536 00537 00538 00539 00540 00541 00542 00543 00544 00545 00546 00547 00548 00549 00550 00551 00552 00553 00554 00555 00556 00557 00558 00559 00560 00561 00562 00563 00564 00565 00566
_BYTES2_ block bytes _SourcePointer2_ Start Pointer block Sequence Note This MACRO basically same calling I2C_WR_SUB twice, STOP sent (bus given between I2C_WR_SUB Check Txmt_Success flag transmission errors I2C_WR_SUB_WR MACRO movlw movwf movlw movwf movf movwf movlw movwf call movf movwf Block write over Send Block movlw movwf movlw movwf call call ENDM StoreTemp_1,W (_SourcePointer1_ restore contents (_SourcePointer_ _COUNT1_, _SourcePointer1_, _Sub_Address_, _COUNT2_, _SourcePointer2_ (_COUNT1_ tempCount (_SourcePointer1_ INDF,W StoreTemp_1 temporarily store contents (_SourcePointer_ _Sub_Address_ INDF store temporarily sub-address (_SourcePointer_ _i2c_block_write write _BYTES_+1 block data
_COUNT2_ tempCount _SourcePointer2_ _block_wr1_loop TxmtStopBit Issue stop slave transmission
I2C_WR_SUB_RD This macro writes block data from SourcePointer length _COUNT1_ slave
1997 Microchip Technology Inc. DS00554C-page
00567 00568 00569 00570 00571 00572 00573 00574 00575 00576 00577 00578 00579 00580 00581 00582 00583 00584 00585 00586 00587 00588 00589 00590 00591 00592 00593 00594 00595 00596 00597 00598 00599 00600 00601 00602 00603 00604 00605 00606 00607 00608 00609 00610 00611 00612 00613
sub-address then Reads block Data length _COUNT2_ destination address pointer Message Structure Parameters _COUNT1_ Length Source Buffer _SourcePointer_ Source Pointer Address _Sub_Address_ Address slave _COUNT2_ length Destination Buffer _DestPointer_ start address Destination Pointer I2C_WR_SUB_RD MACRO movlw movwf movlw movwf movf movwf movlw movwf call restore contents (_SourcePointer_ Without sending STOP bit, read block data using REPEATED Start Condition I2C_READ _COUNT2_, _DestPointer_ ENDM movf movwf StoreTemp_1,W (_SourcePointer1_ _COUNT1_, _SourcePointer_, _Sub_Address_, _COUNT2_, _DestPointer_ (_COUNT1_ tempCount (_SourcePointer_ INDF,W StoreTemp_1 temporarily store contents (_SourcePointer_ _Sub_Address_ INDF store temporarily sub-address (_SourcePointer_ _i2c_block_write write _BYTES_+1 block data
AN554
I2C_WR_COM_WR This Macro write blocks data buffers slave message. This need give after sending first block. example, this kind transaction used driver where
DS00554C-page 1997 Microchip Technology Inc.
AN554
00614 00615 00616 00617 00618 00619 00620 00621 00622 00623 00624 00625 00626 00627 00628 00629 00630 00631 00632 00633 00634 00635 00636 00637 00638 00639 00640 00641 00642 00643 00644 00645 00646 00647 00648 00649 00650 00651 00652 00653 00654 00655 00656 00657 00001 00002 00003
block control addresss info needed then another block actual data displayed needed. Message Structure NOTE This message same calling I2C_WR Macros, except that given between sending blocks (this done sending STOP inbetween) Parameters _COUNT1_ Length Source Buffer _SourcePointer1_ Source Pointer Address buffer _COUNT2_ length Destination Buffer _SourcePointer2_ Source Pointer Address Buffer I2C_WR_COM_WR MACRO movlw movwf movlw movwf call First block sent, movlw movwf movlw movwf call call ENDM _COUNT1_, _SourcePointer1_, _COUNT2_, _SourcePointer2_ _COUNT1_ tempCount _SourcePointer1_ _i2c_block_write send block data _COUNT2_ tempCount _SourcePointer2_ _block_wr1_loop TxmtStopBit Double buffer txmt
INCLUDE Level Routines Here include "i2c_low.inc" Level Routines
1997 Microchip Technology Inc. 004D 004D 004E 004F 0050 1283 0806 39FC 0086 0051 1683 0052 1486 0053 1406 0054 0190 0055 0191 0056 0008 DS00554C-page 0057 0057 1683 0058 1486 0059 1406
00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029 00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 00040 00041 00042 00043 00044 00045 00046
Single Master Transmitter Single Master Receiver Routines These routines very easily converted Multi-Master System when PIC16C6X with chip Slave Hardware, Start Stop detection available. generic high level routines given I2C_HIGH.ASM Program: I2C_LOW.ASM Revision Date: 1-16-97 Compatibility with MPASMWIN 1.40
Initialization InitI2CBus_Master: STATUS,RP0 movf PORTB,W andlw 0xFC movwf PORTB RELEASE_BUS STATUS,RP0 _SDA _SCL _Bus_Busy clrf Bus_Status clrf Bus_Control return
Port Pins zero. From simply play with tris select Bank1 tristate tristate Busy, TEMP ????, set/clear Start Stop reset status clear Bus_Control Reg, reset addressing
Send Start TxmtStartBit:
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STATUS,RP0 _SDA _SCL
select Bank1 high clock high
DS00554C-page 1997 Microchip Technology Inc.
AN554
005A 210D 005B 1086 005C 210B 005D 1410 005E 0008
005F 005F 0060 0061 0062 0063 0064
1683 1006 1086 1406 210D 1486
0065 210B
0066 1010 0067 0008
0068 0068 205F
00047 00048 00049 00050 00051 00052 00053 00054 00055 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093
Setup time REPEATED START condition (4.7 call Delay40uSec only necessary setup time _SDA give falling edge while clock high call Delay47uSec only necessary START HOLD time _Bus_Busy start condition busy return
Send Stop TxmtStopBit: call _ENABLE_BUS_FREE_TIME delay make sure START sent immediately after STOP, ensure Free Time tBUF call Delay47uSec endif _Bus_Busy stop condition considered Free return STATUS,RP0 _SCL _SDA _SCL Delay40uSec _SDA select Bank1 Clock pulled Setup Time STOP Condition give rising edge while CLOCK high
Abort Transmission Send STOP Abort Flag AbortTransmission: call TxmtStopBit
1997 Microchip Technology Inc. DS00554C-page
0069 1490 006A 0008
006B 006B 1390 006C 1C11 006D 2886 006E 1C91 006F 287D
0070 0070 0071 0072 0073 1091 207D 1E10 3400
0074 2057 0075 1491 0076 0077 0078 0079 007A 080D 008E 140E 2095 288C
007B 1E10 007C 2890
00094 00095 00096 00097 00098 00099 00100 00101 00102 00103 00104 00105 00106 00107 00108 00109 00110 00111 00112 00113 00114 00115 00116 00117 00118 00119 00120 00121 00122 00123 00124 00125 00126 00127 00128 00129 00130 00131 00132 00133 00134 00135 00136 00137 00138 00139 00140
return
_Abort
Transmit Address (1st Byte)& Read/Write Operation Transmits Slave Addr byte operation Slave Address must loaded into SlaveAddr operation must Bus_Status (bit _SLAVE_RW): Write Read Success, return TRUE register, else FALSE register desired, failure tested bits Status Txmt_Slave_Addr: _ACK_Error reset Acknowledge error btfss _10BitAddr goto SevenBitAddr btfss _Slave_RW goto TenBitAddrWR simply send addr Required READ slave, first send Then Repeated Start then Byte Only read opreation TenBitAddrRd: call btfss retlw call movf movwf call goto _Slave_RW TenBitAddrWR _Txmt_Success FALSE TxmtStartBit _Slave_RW SlaveAddr+1,W DataByte DataByte,LSB SendData _AddrSendTest temporarily operation skip successful
send REPEATED START condition slave Read
Read Operation send ONLY high byte addr slave Addr Send Slave Read Over
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successfully transmitted, expect btfss _Txmt_Success successful, generate STOP abort transfer goto _AddrSendFail
DS00554C-page 1997 Microchip Technology Inc.
AN554
007D 007D 080D 007E 008E 007F 100E
0080 2095
0081 1E10 0082 2890 0083 080C 0084 008E 0085 288B 0086 0086 0087 0088 0089 008A
080C 008E 100E 1891 140E
008B 008B 2095
008C 008C 008D 008E 008F
1E10 2890 0064 3401
0090 0090 0064 0091 1F90 0092 3400
00141 00142 00143 00144 00145 00146 00147 00148 00149 00150 00151 00152 00153 00154 00155 00156 00157 00158 00159 00160 00161 00162 00163 00164 00165 00166 00167 00168 00169 00170 00171 00172 00173 00174 00175 00176 00177 00178 00179 00180 00181 00182 00183 00184 00185 00186 00187
TenBitAddrWR: movf movwf SlaveAddr+1,W DataByte DataByte,LSB
Operation Ready transmit data Interrupt Driven (i.e Clock Stretched Enabled) then save RETURN Address Pointer call SendData send high byte addr slave successfully transmitted, expect btfss _Txmt_Success successful, generate STOP abort transfer goto _AddrSendFail movf SlaveAddr,W movwf DataByte load addr DatByte transmission goto EndTxmtAddr SevenBitAddr: movf movwf btfsc
SlaveAddr,W DataByte DataByte,LSB _Slave_RW DataByte,LSB
load addr DatByte transmission skip then write operation Read Operation
EndTxmtAddr: call SendData send bits address, our's successfully transmitted, expect _AddrSendTest: btfss _Txmt_Success skip successful goto _AddrSendFail clrwdt retlw TRUE _AddrSendFail: clrwdt btfss _ACK_Error retlw FALSE Addr Txmt Unsuccessful, return Address Acknowledged, send STOP
1997 Microchip Technology Inc. DS00554C-page
0093 205F 0094 3400
0095
0095 2896
0096 0096 0097 0098 0099 009A 009B 009C
080E 0093 1510 1210 3008 008F 1683
009D 0801 009E 39C3 009F 0081
00A0 00A0 00A1 00A2 00A3 00A4
0064 1006 0D93 1086 1803
00188 00189 00190 00191 00192 00193 00194 00195 00196 00197 00198 00199 00200 00201 00202 00203 00204 00205 00206 00207 00208 00209 00210 00211 00212 00213 00214 00215 00216 00217 00218 00219 00220 00221 00222 00223 00224 00225 00226 00227 00228 00229 00230 00231 00232 00233 00234
Addr Txmt Unsuccessful, return Transmit Byte Data data transmitted must loaded into DataByte Clock stretching allowed slave. slave pulls clock low, then, stretch detected Interrupt Rising edge enabled also TMR0 timeout interrupt enabled clock stretching slows down transmit rate because checking done software. However, system fast slaves needs clock stretching, then this feature disabled during Assembly time setting _CLOCK_STRETCH_ENABLED must FALSE. SendData: TXmtByte Send Data same, check errors here before calling TxmtByte future compatibility, user MUST call SendData TxmtByte goto TxmtByte TxmtByte: movf DataByte,W movwf DataByteCopy make copy DataByte _Txmt_Progress status txmt progress _Txmt_Success reset status movlw 0x08 movwf BitCount STATUS,RP0 _CLOCK_STRETCH_CHECK TMR0 timeout mSec disturb user's selection RPUB OPTION Register movf andlw movwf endif OPTION_REG,W _OPTION_INIT OPTION_REG
call retlw
TxmtStopBit FALSE
defined I2C.H header file
AN554
TxmtNextBit: clrwdt btfsc clear WDT, mSec _SCL DataByteCopy, first, Note DataByte Lost _SDA STATUS,C
DS00554C-page 1997 Microchip Technology Inc.
AN554
00A5 00A6 00A7 00A8 00A9 00AA 00AB 00AC 00AD 00AE 00AE 00AF 00B0 00B1 00B2 00B3 00B4
1486 210B 1406 210D 1283 0181 110B 168B 1391 1B91 28FC 1283 1C06 28AE 128B 1683
00B5 0B8F 00B6 28A0
00B7 00B8 00B9 00BA 00BB 00BC 00BD 00BE
1006 1486 210B 1406 210D 1283 1886 28C5
00BF 1683 00C0 1006 00C1 00C2 00C3 00C4 00C5 1110 1610 1390 0008
00C5 1683 00C6 1486 00C7 1406 00C8 1110
00235 00236 00237 00238 00239 00240 00241 00242 00243 00244 00245 00246 00247 00248 00249 00250 00251 00252 00253 00254 00255 00256 00257 00258 00259 00260 00261 00262 00263 00264 00265 00266 00267 00268 00269 00270 00271 00272 00273 00274 00275 00276 00277
_SDA call Delay47uSec _SCL call Delay40uSec _CLOCK_STRETCH_CHECK STATUS,RP0 clrf TMR0 INTCON,T0IF INTCON,T0IE _TIME_OUT_ Check_SCL_1: btfsc _TIME_OUT_ goto Bus_Fatal_Error STATUS,RP0 btfss _SCL goto Check_SCL_1 INTCON,T0IE STATUS,RP0 endif decfsz BitCount, goto TxmtNextBit Check Acknowledge _SCL _SDA call Delay47uSec _SCL call Delay40uSec STATUS,RP0 btfsc _SDA goto _TxmtErrorAck STATUS,RP0 _SCL return _TxmtErrorAck: RELEASE_BUS STATUS,RP0 _SDA _SCL _Bus_Busy _Txmt_Progress _Txmt_Progress _Txmt_Success _ACK_Error
guarantee TIME tLOW Setup time clock high, check clock high, else clock being stretched guarantee HIGH TIME tHIGH
clear TMR0 clear pending flags elable TMR0 Interrupt reset timeout error flag
TMR0 timeout Error then Abort return Possible FATAL Error clock being stretched, must high loop until high TMR0 timeout interrupt Clock good, disable TMR0 interrupts
reset clock Release line Slave pull down guarantee TIME tLOW Setup time clock slave guarantee HIGH TIME tHIGH select Bank0 test PortB should pulled slave
reset clock reset TXMT Status transmission successful
select Bank1 tristate tristate Busy, TEMP ????, set/clear Start Stop reset TXMT Status
1997 Microchip Technology Inc. DS00554C-page
00C9 1210 00CA 1790 00CB 0008
00CC 00CC 28CD 00CD 00CD 1590 00CE 1290 00CF 3008 00D0 008F 00D1 1683
00D2 0801 00D3 39C3 00D4 0081
00D5 00D5 00D6 00D7 00D8 00D9 00DA 00DB
0064 1683 1006 1486 210B 1406 210D
00DC 1283
00278 00279 00280 00281 00282 00283 00284 00285 00286 00287 00288 00289 00290 00291 00292 00293 00294 00295 00296 00297 00298 00299 00300 00301 00302 00303 00304 00305 00306 00307 00308 00309 00310 00311 00312 00313 00314 00315 00316 00317 00318 00319 00320 00321 00322 00323 00324
return
_Txmt_Success _ACK_Error
transmission successful From Slave
Receive Byte Data From Slave assume address already sent last byte received, acknowledge slave (last byte testted from _Last_Byte_Rcv control reg) Data Received successful reception DataReg register GetData: goto RcvByte: _Rcv_Progress _Rcv_Success status txmt progress reset status RcvByte
movlw 0x08 movwf BitCount _CLOCK_STRETCH_CHECK STATUS,RP0 TMR0 timeout mSec disturb user's selection RPBU OPTION Register movf andlw movwf endif OPTION_REG,W _OPTION_INIT OPTION_REG
defined I2C.H header file
RcvNextBit: clrwdt STATUS,RP0 _SCL _SDA call Delay47uSec _SCL call Delay40uSec _CLOCK_STRETCH_CHECK STATUS,RP0 clear WDT, mSec Bank1 TRIS manipulation
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removed from loop guarantee TIME tLOW Setup time clock high, data sent slave guarantee HIGH TIME tHIGH
DS00554C-page 1997 Microchip Technology Inc.
AN554
00DD 00DE 00DF 00E0 00E1 00E1 00E2 00E3 00E4 00E5 00E6 00E7 00E8 00E9 00EA 00EB
0181 110B 168B 1391 1B91 28FC 1283 1C06 28E1 128B 1683 1283 1003 1886 1403
00EC 0D8E 00ED 0B8F 00EE 28D5
00EF 00F0 00F1 00F2 00F3 00F4 00F5 00F6 00F7 00F7
1683 1006 1086 1911 1486 210B 1406 210D 1006
00F8 1190 00F9 1690 00FA 1390 00FB 0008
00325 00326 00327 00328 00329 00330 00331 00332 00333 00334 00335 00336 00337 00338 00339 00340 00341 00342 00343 00344 00345 00346 00347 00348 00349 00350 00351 00352 00353 00354 00355 00356 00357 00358 00359 00360 00361 00362 00363 00364 00365 00366 00367 00368 00369 00370 00371
clrf Check_SCL_2: btfsc goto btfss goto endif btfsc decfsz goto
TMR0 INTCON,T0IF INTCON,T0IE _TIME_OUT_ _TIME_OUT_ Bus_Fatal_Error STATUS,RP0 _SCL Check_SCL_2 INTCON,T0IE STATUS,RP0 STATUS,RP0 STATUS,C _SDA STATUS,C DataByte, BitCount, RcvNextBit
clear TMR0 clear pending flags enable TMR0 Interrupt reset timeout error flag
TMR0 timeout Error then Abort return Possible FATAL Error clock being stretched, must high loop until high TMR0 timeout interrupt Clock good, diable TMR0 interrupts
select Bank0 read Ports
TEMP ???? Majority detect left shift data first)
Generate last byte read, last byte Generate NACK send last byte, main routine will send STOP STATUS,RP0 _SCL _SDA pulling btfsc _Last_Byte_Rcv _SDA last byte, send NACK setting high call Delay47uSec guarantee TIME tLOW Setup time _SCL call Delay40uSec guarantee HIGH TIME tHIGH RcvEnd: _SCL reset clock return _CLOCK_STRETCH_CHECK Fatal Error Slave pulling clock long Line stuck low. _Rcv_Progress _Rcv_Success _ACK_Error reset TXMT Status transmission successful
1997 Microchip Technology Inc. DS00554C-page
00FC
00FC 128B
00FD 1683 00FE 1486 00FF 1406
0100 0101 0102 0103
1490 1710 1110 1210
0104 205F 0105 0008
0106 0106 3006 0107 0107 0092 0108 0B92
00372 00373 00374 00375 00376 00377 00378 00379 00380 00381 00382 00383 00384 00385 00386 00387 00388 00389 00390 00391 00392 00393 00394 00395 00396 00397 00398 00399 00400 00401 00402 00403 00404 00405 00406 00407 00408 00409 00410 00411 00412 00413 00414
This occurs during Transmission, stuck period longer than appox TMR0 times appox 4096 cycles prescaler 16). Bus_Fatal_Error: disable TMR0 Interrupt INTCON,T0IE RELEASE_BUS STATUS,RP0 _SDA _SCL _Bus_Busy select Bank1 tristate tristate Busy, TEMP ????, set/clear Start Stop
disable TMR0 interrupts, until next TXMT
Bus_Status Bits appropriately _Abort _Fatal_Error _Txmt_Progress _Txmt_Success TxmtStopBit transmission aborted FATAL Error occured Transmission Progress Transmission Unsuccesful
call return endif sending STOP bit, successful
General Purpose Delay Routines Delay4uS wait loop uSec Delay47uS wait loop uSec Delay50uS wait loop uSec Delay50uSec: movlw DlyK movwf decfsz
AN554
((_50uS_Delay-5)/3 DelayCount DelayCount,
DS00554C-page 1997 Microchip Technology Inc.
AN554
0109 2908 010A 0008 010B 010B 3004 010C 2907 010D 010D 3003 010E 2907
010F
010F 1011 0110 30A0 0111 008C 0112
0112 2011 0113 1F11 0114 2912 0115 0064
0116 1091 0117 2057 0118 206B 0119 3050 011A 008E 011B 2095
00415 00416 00417 00418 00419 00420 00421 00422 00423 00424 00425 00426 00109 00110 00111 00112 00113 00114 00115 00116 00117 00118 00119 00120 00121 00122 00123 00124 00125
goto return
Delay47uSec: movlw ((_47uS_Delay-8)/3 goto DlyK Delay40uSec: movlw ((_40uS_Delay-8)/3 goto DlyK endif ReadSlave1:
EEPROM (24C04) write mode (busy), check sending control byte LOAD_ADDR_8 movlw movwf _Slave_1_Addr Address Mode
_10BitAddr (0xA0 0xff) SlaveAddr
wait1: I2C_TEST_DEVICE call IsSlaveActive TEMP ???? Assembler Error with this MACRO
btfss _SlaveActive slave responding goto wait1 stuck forever, recover from WDT, other schemes clrwdt I2C_READ_SUB DataBegin+1, 0x50 call call movlw movwf call _Slave_RW write operation TxmtStartBit send START Txmt_Slave_Addr successful, then _Txmt_Success 0x50 DataByte SendData
START address EEPROM(slave write address
send STOP after this, REPEATED START condition
1997 Microchip Technology Inc. DS00554C-page
011C 011D 011E 011F
3007 0096 3021 0084
0120 2039
0121 1011 0122 30AC 0123 008C 0124
0124 2011 0125 1F11 0126 2924 0127 0064
0128 1091 0129 2057 012A 206B 012B 3060 012C 008E 012D 2095
00126 00127 00128 00129 00130 00131 00132 00133 00134 00135
I2C_READ DataBegin+1
movlw movwf movlw movwf call
tempCount DataBegin+1 _i2c_block_read
because, last byte used loop FIFO destination address pointer
Read bytes data from Slave starting from Sub-Address 0x60 LOAD_ADDR_8 _Slave_2_Addr movlw movwf wait2: I2C_TEST_DEVICE call IsSlaveActive TEMP ???? Assembler Error with this MACRO _10BitAddr (0xAC 0xff) SlaveAddr Address Mode
btfss _SlaveActive slave responding goto wait2 stuck forever, recover from WDT, other schemes clrwdt I2C_READ_SUB DataBegin+1, 0x60 call call movlw movwf call _Slave_RW write operation TxmtStartBit send START Txmt_Slave_Addr successful, then _Txmt_Success 0x60 DataByte SendData
START address EEPROM(slave write address
AN554
send STOP after this, REPEATED START condition I2C_READ DataBegin+1
DS00554C-page 1997 Microchip Technology Inc.
AN554
012E 012F 0130 0131
3007 0096 3021 0084
0132 2039
0133 0008
0134
0134 1011 0135 30D6 0136 008C 0137
0137 2011 0138 1F11 0139 2937 013A 0064
013B 1091 013C 2057 013D 206B 013E 3000 013F 008E 0140 2095
00136 00137 00138 00139 00140 00141 00142 00143 00144 00145 00146 00147 00148 00149 00150
movlw movwf movlw movwf call
tempCount DataBegin+1 _i2c_block_read
because, last byte used loop FIFO destination address pointer
return ReadSlave3: LOAD_ADDR_8 movlw movwf wait3: I2C_TEST_DEVICE call IsSlaveActive TEMP ???? Assembler Error with this MACRO _Slave_3_Addr Address Mode
_10BitAddr (0xD6 0xff) SlaveAddr
btfss _SlaveActive slave responding goto wait3 stuck forever, recover from WDT, other schemes clrwdt I2C_READ_SUB DataBegin, call call movlw movwf call _Slave_RW write operation TxmtStartBit send START Txmt_Slave_Addr successful, then _Txmt_Success DataByte SendData
START address EEPROM(slave write address
send STOP after this, REPEATED START condition I2C_READ DataBegin
1997 Microchip Technology Inc. DS00554C-page
0141 0142 0143 0144
3007 0096 3020 0084
0145 2039
0146 0008
0147 0147 0148 0149 014A 014B 014C 014D 014E 014F 014F 0150 0151 0152 0153 0154 0155 3000 00A0 3021 0084 3008 009A 3055 009B 099B 081B 0080 0A84 0B9A 294F 0008
0156
00151 00152 00153 00154 00155 00156 00157 00158 00159 00160 00161 00162 00163 00164 00165 00166 00167 00168 00169 00170 00171 00172 00173 00174 00175 00176 00177 00178 00179 00180 00181 00182 00183 00184 00185 00186 00187 00188
movlw movwf movlw movwf call
tempCount DataBegin _i2c_block_read
because, last byte used loop FIFO destination address pointer
return Fill Data Buffer With Test Data bytes 0x55, 0xAA pattern) FillDataBuf: movlw movwf movlw movwf movlw movwf movlw movwf comf movf movwf incf decfsz goto return HoldData, HoldData,W INDF FSR, byteCount, 0x00 DataBegin DataBegin+1 byteCount 0x55 HoldData start address location EEPROM array byte data sent start address data starts following address (RAM Pointer) fill with bytes this data written EEPROM (slave) pattern fill with 0x55 0xAA
point next location
Main Routine (Test Program) SINGLE MASTER, MULTIPLE SLAVES Start:
AN554
DS00554C-page 1997 Microchip Technology Inc.
AN554
0156 204D 0157 178B
0158 2147
0159 1810 015A 2959
015B 1011 015C 30A0 015D 008C
015E 015F 0160 0161
3009 0096 3020 0084
0162 2019 0163 205F
0164 1810 0165 2964
0166 1011 0167 30AC 0168 008C
0169 3009 016A 0096
00189 00190 00191 00192 00193 00194 00195 00196 00197 00198 00199 00200 00201 00202 00203 00204 00205 00206 00207 00208 00209 00210 00211 00212 00213
call
InitI2CBus_Master INTCON,GIE
initialize enable global interrupts
call FillDataBuf fill data buffer with bytes data (0x55, 0xAA) high level Macro send bytes Slave 24C04) Addr Write bytes Slave starting addr pointer DataBegin btfsc _Bus_Busy Free, ie.has start stop been detected (only multi master system) goto very simple test, unused LOAD_ADDR_8 movlw movwf I2C_WR _Slave_1_Addr _10BitAddr (0xA0 0xff) SlaveAddr Address Mode
0x09, DataBegin movlw movwf movlw movwf call call 0x09 tempCount DataBegin _i2c_block_write TxmtStopBit Issue stop slave transmission
Write bytes Data slave starting slaves memory address 0x30 btfsc goto _Bus_Busy Free, start stop been detected (only multi master system) very simple test, unused
LOAD_ADDR_8
_Slave_2_Addr movlw movwf _10BitAddr (0xAC 0xff) SlaveAddr Address Mode
I2C_WR_SUB movlw movwf
0x08, DataBegin+1, 0x30 (0x08 tempCount
1997 Microchip Technology Inc. DS00554C-page
016B 3020 016C 0084 016D 016E 016F 0170 0800 0097 3030 0080
0171 2019 0172 0817 0173 00A0 0174 205F
0175 210F
0176 1011 0177 30D6 0178 008C 0179 30CC 017A 00A0
017B 3002 017C 0096 017D 301F 017E 0084 017F 0180 0181 0182 0800 0097 3033 0080
0183 2019 0184 0817 0185 009F 0186 205F
00214 00215 00216 00217 00218 00219 00220
movlw movwf movf movwf movlw movwf call movf movwf call
(DataBegin+1 INDF,W StoreTemp_1 0x30 INDF _i2c_block_write StoreTemp_1,W (DataBegin+1 TxmtStopBit
temporarily store contents (_SourcePointer_ store temporarily sub-address (_SourcePointer_ write _BYTES_+1 block data
restore contents (_SourcePointer_ Issue stop slave transmission
call LOAD_ADDR_8 movlw movwf movlw movwf I2C_WR_SUB movlw movwf movlw movwf movf movwf movlw movwf call movf movwf call
ReadSlave1 _Slave_3_Addr _10BitAddr (0xD6 0xff) SlaveAddr 0xCC DataBegin 0x01,DataBegin, 0x33 (0x01 tempCount (DataBegin INDF,W StoreTemp_1 0x33 INDF _i2c_block_write StoreTemp_1,W (DataBegin TxmtStopBit
read byte from slave from current address
Address Mode
temporarily store contents (_SourcePointer_ store temporarily sub-address (_SourcePointer_
AN554
write _BYTES_+1 block data
restore contents (_SourcePointer_ Issue stop slave transmission
DS00554C-page 1997 Microchip Technology Inc.
AN554
0187 2134
0188 0064 0189 2988
00221 00222 00223 00224 00225 00226 00227 00228 00229 00230
call self clrwdt goto ReadSlave3 Read From Slave
self
MEMORY USAGE (`X' Used, 0000 0040 0080 00C0 0100 0140 0180 X-XXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXX-
Unused) XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX -XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
other memory blocks unused. Program Memory Words Used: Program Memory Words Free:
Errors Warnings Messages
reported, reported,
suppressed suppressed
Note following details code protection feature PICmicro® MCUs. PICmicro family meets specifications contained Microchip Data Sheet. Microchip believes that family PICmicro microcontrollers most secure products kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using PICmicro microcontroller manner outside operating specifications contained data sheet. person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable". Code protection constantly evolving. Microchip committed continuously improving code protection features product.
have further questions about this matter, please contact local sales office nearest you.
Information contained this publication regarding device applications like intended through suggestion only superseded updates. your responsibility ensure that your application meets with your specifications. representation warranty given liability assumed Microchip Technology Incorporated with respect accuracy such information, infringement patents other intellectual property rights arising from such otherwise. Microchip's products critical components life support systems authorized except with express written approval Microchip. licenses conveyed, implicitly otherwise, under intellectual property rights.
Trademarks Microchip name logo, Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, MATE, SEEVAL Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode Total Endurance trademarks Microchip Technology Incorporated U.S.A. Serialized Quick Turn Programming (SQTP) service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2002, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved.
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Microchip received QS-9000 quality system certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona July 1999. Company's quality system processes procedures QS-9000 compliant PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs microperipheral products. addition, Microchip's quality system design manufacture development systems 9001 certified.
2002 Microchip Technology Inc.
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2002 Microchip Technology Inc.

most systems microcontroller master external peripheral devices slaves

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