Math Utility Routines Author: Amar Palacherla Microchip Technolog
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AN544
Math Utility Routines
Author: Amar Palacherla Microchip Technology Inc.
more routines available, they will added library. latest routines obtained either through Microchip's bulletin board contacting your nearest Microchip sales office copy MS-DOS® floppy. These routines have been optimized wherever possible with compromise between speed, utilization, code size. Some routines (multiplication division) provided forms, optimized speed other optimized code size. routines have been implemented callable subroutines usage each routine explained below. application note, listing files above programs given.
INTRODUCTION
PLEASE NOTE: This application note uses Microchip Math Routine format. intended reference purposes only being provided those still implementing Binary Coded Decimal(BCD) routines. designs, please refer application notes contained Microchip's Embedded Control Handbook Volume Math Library This application note provides some utility math routines Microchip's second generation high performance 8-bit microcontroller, PIC17C42. Three assembly language modules provided, namely ARITH.ASM, BCD.ASM FXP-DIV.ASM. Currently each file following subroutines implemented:
SINGLE PRECISION UNSIGNED MULTIPLICATION
This routine computes product unsigned 8-bit numbers produces 16-bit result. routines provided: routine optimized speed straight line code) other been optimized code size looped code version). These subroutines located ARITH.ASM printed listing file ARITH.LST. performance specs shown Table
ARITH.ASM
Single precision unsigned multiply double precision multiply (signed unsigned) double precision divide (signed unsigned) double precision addition double precision subtraction double precision square root double precision numerical differentiation double precision numerical integration Pseudo Random number generation Gaussian distributed random number generation
DOUBLE PRECISION MULTIPLICATION
This routine computes product numbers produces 32-bit result. Both signed unsigned arithmetic provided (2's complement arithmetic). Whether signed unsigned decided assembly time depending whether "SIGNED" true false (refer source code). These routines extremely useful high precision computation used extensively other programs provided this application note (for example, square root, integrator, differentiator call these routines). routines provided. routine optimized speed straight line code) other been optimized code size looped code version). These subroutines located ARITH.ASM printed listing file ARITH.LST. performance specs shown Table
BCD.ASM
8-bit binary digit conversion 16-bit binary digit conversion 5-bit 16-bit binary conversion digit addition
FXP-DIV.ASM.
routines that implementing this source file shown Table
TABLE
Name mpy8x8_F MPY8X8_s
SINGLE PRECISION MULTIPLICATION
Comments speed efficient code efficient Program Memory Instruction Cycles Scratch Register used used
MS-DOS registered trademark Microsoft Corporation.
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listing file shown assembled with "SIGNED TRUE". unsigned arithmetic needed, source code should changed "SIGNED FALSE". Conditional assembly advanced macro features assembler used. data memory organization explained comment section code. Faster execution code space saving achieved setting "MODE_FAST TRUE". However, setting MODE_FAST variable TRUE restricts that operands 32-bit result data locations 0x18 0x1F this mode, MOVFP MOVPF instructions used transfer data to/from location addresses less than 0x1F). MODE_FAST FALSE, there will restriction location data values used this subroutine. However, code will slightly slower occupies more program memory. listing file shown assembled with "SIGNED TRUE". unsigned arithmetic needed, source code should changed "SIGNED FALSE". Conditional assembly advanced macro features assembler used.
DOUBLE PRECISION DIVISION
This routine performs complement division 16-bit numbers produces 16-bit quotient with 16-bit remainder. Both signed unsigned arithmetic provided (2's complement arithmetic). Whether signed unsigned decided assembly time depending whether "SIGNED" true false (refer source code). These routines extremely useful high precision computation used extensively other programs provided this application note (for example, square root, integrator, differentiator call these routines). routines provided. routine optimized speed straight line code) other been optimized code size looped code version). These subroutines located Appendix performance specs shown Table
TABLE
Name D_myfF D_mpyF D_mpyS D_mpyS
DOUBLE PRECISION MULTIPLICATION
Comments Speed Efficient, Signed Arithmetic Speed Efficient, Unsigned Arithmetic Code Efficient, Signed Arithmetic Code Efficient, Unsigned Arithmetic Program Memory Instruction Cycles Scratch Register used used used used
TABLE
Routine Signed Unsigned Unsigned Unsigned Unsigned Unsigned Unsigned Unsigned Unsigned Unsigned Unsigned Unsigned
FIXED POINT DIVIDE PERFORMANCE DATA
Max. Cycles Min. Cycles Program Memory Data Memory
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DOUBLE PRECISION ADDITION SUBTRACTION
routines provided. performs complement addition other performs complement subtraction 16-bit binary numbers. These subroutines located ARITH.ASM printed listing file ARITH.LST. performance specs shown Table
EQUATION
)2ff
root f(Y), then f(X) Therefore,
NEGATE DOUBLE PRECISION NUMBER
These routines negate double precision number (16-bit 32-bit). routines macros provided negate 16-bit number. subroutines indirect addressing mode macros direct addressing scheme. macro provided negate number.
approximate root f(Y), then higher order terms above equation negligible. Therefore, i.e.,
Thus better approximation From previous equation, sequence {Xn} generated:
DOUBLE PRECISION SQUARE ROOT
Often many applications, needs find square root number. many numerical methods available compute square root number, Newton-Raphson method most attractive because fast convergence rate. this method, square root number, obtained approximate solution function f(Y) expanded about using first order Taylor polynomial expansion
EQUATION
case, equation reduces
EQUATION
routine "Sqrt" ARITH.ASM implements above equation. Equation requires that first initial approximation root known. better initial approximation, faster convergence rate would "Sqrt" routine, initial approximation root N/2. This routine calls double precision division routine (D_divS). code size, Division routine (Ddiv_S) size included.
TABLE
Name Dadd Dsub
DOUBLE PRECISION ADDITION SUBTRACTION
Program Memory Instruction Cycles Scratch Register used used
TABLE
Name Negate NegateAlt NegMac AltNegMac
NEGATE DOUBLE ADDITION SUBTRACTION
Program Memory Instruction Cycles Scratch Register unused used used unused used
NegMac32 bit)
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ROUTINES
Three routines provided general purpose arithmetic: binary conversion Binary conversion addition where point which numerical derivative desired step size. smaller value step size (h), better approximation. case say, motor control, step size proportional time intervals which sample value position speed) obtained. Using above equation compute differential, three samples necessary (present value last past values). subroutine "Diff" implemented that 1/2h factor stored already location (location DiffK) 1/2h because more efficient multiply than divide. After computation, routine does move present value past value. user must update past values before calling this routine again. This way, necessary, differentiation performed without disturbing present past values. Also, when this routine called first time, user's responsibility initial values past data points (may zero). This routine called "Diff" located "ARITH.ASM". code size, double precision multiplication routine (Dmpy_S) used included.
EQUATION
3-POINT FORMULA:
binary conversion routine converts 5-digit code 16-bit binary number. addition routine adds digits directly without converting them first binary. Note usage "DAW" instruction. other routines convert binary number code. performance specs routines given Table below.
NUMERICAL DIFFERENTIATION
This routine performs numerical differentiation sequence data input sequence assumed piecewise linear with discontinuances (this case most real world signals). Although this routine provided tool implement algorithm motor control, used general purpose subroutine. This routine uses called 3-Point formula compute differential sequence numbers. Given equation f(t), derivative given above equation approximated using 3-Point formula given below:
TABLE
Name Sqrt
DOUBLE PRECISION SQUARE ROOT
Program Memory Instruction Cycles 3300 (Approx.) Scratch Register used
TABLE
Name BCDtoB B2_BCD_Loope
ROUTINES
Comments Binary Binary bit) looped code Program Memory Instruction Cycles Scratch Register used used used unused used
B2_BCD_Straig Binary bit) straight line code BinBCD BCDAdd Binary bit) addition
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NUMERICAL INTEGRATION
This routine performs numerical integration using Simpson's Three-Eighths Rule. This third order approximation function, whose integral computed given point. Although this routine provided tool implement algorithm motor control, used general purpose subroutine. Given function f(t), integral over range represented f(t)dt. This function approximated follows: Simpson's Three-Eighths Rule:
PSEUDO RANDOM NUMBER GENERATOR
This routine (subroutine "Random provided ARITH.ASM) generates pseudo random number sequence. random points generated using 16-bit register left shifting contents with shown following schematic. test, random points generated calling subroutine from infinite loop, data points continuously captured into real time trace buffer using PICMASTER (the Universal In-Circuit Emulator PICmicroseries). autocorrelation captured data computed using stand alone program shown Figure From this figure, seen that data strong autocorrelation only origin sharply approaches zero within points. This demonstrates randomness data captured.
(t0)
FIGURE
constant 3h/8 computed before hand stored location location IntgKLo IntgKHi 16-bit number). After computation, routine does move present value past value. user must update past values before calling this routine again. This way, necessary, integration performed without disturbing present past values. Also, when this routine called first time, user's responsibility initial values past data points (may zero). This routine called "Integrate" located "ARITH.ASM". code size, double precision multiplication routine (Dmpy_S) used included.
TABLE
Name Diff
DIFFERENTIATION
Comments Numerical Differentiation Program Memory Instruction Cycles Scratch Register used
TABLE
Name Integrate
INTEGRATION
Comments Numerical Integration Program Memory Instruction Cycles Scratch Register used
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FIGURE AUTOCORRELATION DATA POINTS GENERATED RANDOM NUMBER GENERATOR
Autocorrelation Data from Random Number Generator 1.20 -1.00 -0.80 -Magnitude 0.60 -0.40 -0.20 -0.00
Sample Number
TABLE
Name Random16 Gauss
RANDOM DOUBLE GENERATOR
Comments Pseudo Random Number Generator Gaussian Random Number Generator Program Memory Instruction Cycles Scratch Register used used
(pseudo noise) sequences widely used digital communication systems synchronization. These code words also used data scrambling because their good correlation properties. interesting application these sequences system integrity. example, these sequences regularly transmitted processor whose watchdog timer will time say, consecutive sequences match.
GAUSSIAN DISTRIBUTED RANDOM NUMBER GENERATOR
This routine (subroutine "Gauss" provided ARITH.ASM) generates sequence random numbers with characteristic normal distribution (Gaussian distributed points). This routine calls pseudo random number generator ("random16") obtain near uniformly distributed random points from these points, Gaussian distributed points generated. method generating Gaussian points based "Central Limit Theorem", which states that ensemble average weighted sequence uncorrelated samples tends have Gaussian distribution. test, Gaussian points generated calling subroutine from infinite loop, data points continuously captured into real time trace buffer using PICMASTER (the Universal In-Circuit Emulator PICmicro series). plot points captured shown Figure which shows that random points generated have characteristics Gaussian distribution.
FIGURE
HISTOGRAM DATA GENERATED GAUSSIAN GENERATOR
Gaussian Distributed Samples Generated PIC17C42
-Relative -Amplitude
-113
Samples
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Please check Microchip latest version source code. Microchip's Worldwide Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership required).
APPENDIX
GENERAL PURPOSE MATH ROUTINES LISTING FILE ARITH.LST
ARITH.ASM 1-16-1997 15:10:04 PAGE
MPASM 01.40 Released
OBJECT CODE VALUE 00001 00002 00003 00004 00005 00006 00001 00002 00264 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029 00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 00040 00041 00042 00043 00044 00045 00046 00047 00048 00049 00050
LINE SOURCE TEXT
TITLE LIST
"General Purpose Math Routines PIC17C42 1.0" 17C42, columns=120, WRAP, L=0,
include <p17c42.inc> LIST P17C42.INC Standard Header File, Version 1.03 Microchip Technology, Inc. LIST #define TRUE #define FALSE _INC _NO_INC _LOW _HIGH
00000001 00000000 00000000 00000001
00000001 00000000
Define Locations necessary "ARITH.ASM" locations should defined before calling library math routines Program: ARITH.ASM Revision Date: 1-13-97 Compatibility with MPASMWIN 1.40 MODE_FAST TRUE SIGNED FALSE MODE_FAST CBLOCK 0x18 ACCaLO, ACCaHI, ACCbLO, ACCbHI ACCcLO, ACCcHI, ACCdLO, ACCdHI ENDC #else CBLOCK 0x20 ACCaLO, ACCaHI, ACCbLO, ACCbHI ACCcLO, ACCcHI, ACCdLO, ACCdHI ENDC #endif CBLOCK
00000018 0000001C
Locations Arithmetic Routines
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00000020 00051 00052 00053 00054 00055 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 00095 00096 00097 00098 00099 00100 00101 00102 00103 00104 00105 00106 00107 00108 00109 00110 00111 00112 00113 00114 00115 00116 tempLo, tempHi, count, sign ENDC CBLOCK NumLo, NumHi iterCnt ENDC CBLOCK locations "Diff" routine XnLo, XnHi, Xn_1_Lo Xn_1_Hi, Xn_2_Lo, Xn_2_Hi DiffKLo, DiffKHi DiffK Step Size DiffLo, DiffHi
00000024 00000026
00000027 0000002A 0000002D 0000002F
ENDC CBLOCK X0Lo, X0Hi, X1Lo, X1Hi X2Lo, X2Hi, X3Lo, X3Hi IntgKLo, IntgKHi IntgLo, IntgHi Locations "Integrate" Routine INTEGRATE CONST 3*h/8
00000031 00000035 00000039 0000003B
00000018 00000019 0000001A 0000001B 0000000A 0000001E 0000001F
00000018 00000019 0000001B 0000001A 00000020
ENDC mulcnd ACCaLO mulplr ACCaHI L_byte ACCbLO H_byte ACCbHI _LUPCNT Desired Number iterations SqrtLo ACCdLO Square Root Routine(NEWTON Iterations) SqrtHi ACCdHI Define locations Random Number Generators RandLo ACCaLO RandHi ACCaHI Pseudo Random Number GaussHi ACCbHI GaussLo ACCbLO Gaussian distributed number GaussTmp tempLo PAGE 0x0000 Math Routines Test Program Load constant values ACCa ACCb testing main call loadAB result adding ACCb+ACCa->ACCb call D_add Here Accb 81FE call loadAB result subtracting ACCb ACCa->ACCb call D_sub Here Accb 7E00 call loadAB result multiplying ACCb*ACCa->(ACCd,ACCc) call D_mpyS Here (ACCd,ACCc) 00FF 7E01 call loadAB result multiplying ACCb*ACCa->(ACCd,ACCc) call D_mpyF Here (ACCd,ACCc) 00FF 7E01 call loadAB result multiplying ACCb/ACCa->(ACCd,ACCc) call D_divS Here (ACCd,ACCc) 0040 003f
0000
0000 0000 E02D 0001 E036 0002 E02D 0003 E03B 0004 E02D 0005 E050 0006 E02D 0007 E065 0008 E02D 0009 E119
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000A E02D 000B E138 000C 000D 000E 000F 0010 B0F3 0125 B0F6 0124 E27D 00117 00118 00119 00120 00121 00122 00123 00124 00125 00126 00127 00128 00129 00130 00131 00132 00133 00134 00135 00136 00137 00138 00139 00140 00141 00142 00143 00144 00145 00146 00147 00148 00149 00150 00151 00152 00153 00154 00155 00156 00157 00158 00159 00160 00161 00162 00163 00164 00165 00166 00167 00168 00169 00170 00171 00172 00173 00174 00175 00176 00177 00178 00179 00180 00181 00182 call call movlw movwf movlw movwf call movlw movwf movlw movwf call movlw movwf movlw movwf call 0xff mulplr 0xff mulcnd mpy8x8_S 0xff mulplr 0xff mulcnd mpy8x8_F NumHi NumLo Sqrt loadAB D_divF result multiplying ACCb/ACCa->(ACCd,ACCc) Here (ACCd,ACCc) 0040 003f
input test number 62454 F3F6h result 00F9h SqrtLo) exact sqrt(62454) 249.9
0011 0012 0013 0014 0015 0016 0017 0018 0019 001A
B0FF 0119 B0FF 0118 E293 B0FF 0119 B0FF 0118 E2B8
multiplier mulplr) multiplicand(W result 0FF*0FF FE01 locations H_byte L_byte multiplier mulplr) multiplicand(W
001B 001C 001D 001E 001F 0020 0021 0022
B0FF 010D B05F 010E B030 0119 B045 0118
0023 C028 0024 0024 0025 0026 0027 0028 0028 0029 002A 002B
E311 A418 AE19 C024
E31E A41A AE1B C028
002C C02C 002D 002D 002E 002F 0030 0031 0032 0033 0034 0035
B001 0119 B0FF 0118 B07F 011B B0FF 011A 0002
result 0FF*0FF FE01 locations H_byte L_byte Test Random Number Generators Capture data into trace buffer TABLE WRITES dummy Program Memory location movlw 0xff movwf TBLPTRL movlw 0x5f movwf TBLPTRH movlw 0x30 movwf RandHi movlw 0x45 movwf RandLo goto GaussPoint RandPoint call Random16 tlwt _LOW,RandLo only data capture tablwt _HIGH,0,RandHi using PICMASTER goto RandPoint GaussPoint call Gauss tlwt _LOW,GaussLo only data capture tablwt _HIGH,0,GaussHi using PICMASTER goto GaussPoint self goto self Test Routines loadAB movlw 0x01 movwf ACCaHI movlw 0xff loads ACCa 01FF movwf ACCaLO movlw 0x7f movwf ACCbHI movlw 0xFF loads ACCb 7FFF movwf ACCbLO return PAGE
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00183 00184 00185 00186 00187 00188 00189 00190 00191 00192 00193 00194 00195 00196 00197 00198 00199 00200 00201 00202 00203 00204 00205 00206 00207 00208 00209 00210 00211 00212 00213 00214 00215 00216 00217 00218 00219 00220 00221 00222 00223 00224 00225 00226 00227 00228 00229 00230 00231 00232 00233 00234 00235 00236 00237 00238 00239 00240 00241 00242 00243 00244 00245 00246 00247 00248 Double Precision Arithmetic Routines Routines Addition, Subtraction, Multiplication ,Division Square Root NOTE MODE_FAST must first either TRUE FALSE MODE_FAST determines address locations ACCa thru ACCd MODE_FAST TRUE, data transfers done efficiently using "MOVFP" "MOVPF" instructions instead indirectly moving first then desired locations speed increase using this locating ACCa ACCd will result saving about Cycles/filter stage this case stage filter), faster Cycles other constraints, ACCa thru ACCd cannot address 0x18 0x1f, then user required MODE_FAST FALSE PAGE Double Precision Addition Addition ACCb(16 bits) ACCa(16 bits) ACCb(16 bits) Load operand location ACCaLO ACCaHI bits Load operand location ACCbLO ACCbHI bits CALL D_add result location ACCbLO ACCbHI bits Performance Program Memory (excluding call return) Clock Cycles (excluding call return) Register Used Scratch D_add movfp ACCaLO,WREG addwf ACCbLO, ;addwf movfp ACCaHI,WREG addwfc ACCbHI, ;addwf with carry return PAGE Double Precision Subtraction Subtraction ACCb(16 bits) ACCa(16 bits) ACCb(16 bits) Load operand location ACCaLO ACCaHI bits Load operand location ACCbLO ACCbHI bits CALL D_sub result location ACCbLO ACCbHI bits Performance Program Memory (excluding call return Clock Cycles (excluding call return Register Used scratch D_sub movfp ACCaLO,WREG
0036 0036 0037 0038 0039 003A
6A18 0F1A 6A19 111B 0002
003B 003B 6A18
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003C 003D 003E 003F 051A 6A19 031B 0002 00249 00250 00251 00252 00253 00254 00255 00256 00257 00258 00259 00260 00261 00262 00263 00264 00265 00266 00267 00268 00269 00270 00271 00272 00273 00274 00275 00276 00277 00278 00279 00280 00281 00282 00283 00284 00285 00286 00287 00288 00289 00290 00291 00292 00293 00294 00295 00296 00297 00298 00299 00300 00301 00302 00303 00304 00305 00306 00307 00308 00309 00310 00311 00312 00313 00314 subwf movfp subwfb return PAGE Function negate integer integers assumed consecutive locations. Before calling this routine, FSR0 should loaded with address lower byte. Assume that ALUSTA register autoincrement FSR0. negateAlt movfp INDF0,WREG ALUSTA,FS1 negw INDF0, ALUSTA,FS1 movfp INDF0,WREG clrf INDF0, subwfb INDF0, return negate comf INDF0, ALUSTA,FS1 incf INDF0, ALUSTA,FS1 btfsc ALUSTA,Z decf INDF0, comf INDF0, return PAGE Double Precision Multiplication Optimized Code Looped Code Multiplication ACCb(16 bits) ACCa(16 bits) ACCd,ACCc bits Load operand location ACCaLO ACCaHI bits Load operand location ACCbLO ACCbHI bits CALL D_mpyS result location ACCdHI,ACCdLO,ACCdHI,ACCdLO Performance Program Memory (UNSIGNED) (SIGNED) Clock Cycles (UNSIGNED :excluding CALL RETURN) (SIGNED :excluding CALL RETURN) Scratch (used only SIGNED arithmetic) Note above timing worst case timing, when register ACCb FFFF. speed improved register ACCb contains number numbers with less number Double Precision Multiply 16x16 ACCb*ACCa ACCb,ACCc output with high word ACCd ACCdHI,ACCdLO word ACCc ACCcHI,ACCcLO D_mpyS ;results ACCd(16 msb's) ACCc(16 lsb's) ACCbLO, ACCaHI,WREG ACCbHI,
0040 0040 0041 0042 0043 0044 0045 0046 0047 0048 0048 0049 004A 004B 004C 004D 004E 004F
6A00 8D04 2D00 8504 6A00 2900 0300 0002
1300 8D04 1500 8504 9A04 0700 1300 0002
0050
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00315 00316 00317 00318 00319 00320 00321 00322 00323 00324 00325 00326 00327 00328 00329 00330 00331 00332 00333 00334 00335 00336 00337 00338 00339 00340 00341 00342 00343 00344 00345 00346 00347 00348 00349 00350 00351 00352 00353 00354 00355 00356 00357 00358 00359 00360 00361 00362 00363 00364 00365 00366 00367 00368 00369 00370 00371 00372 00373 00374 00375 00376 00377 00378 00379 00380 SIGNED CALL S_SIGN #endif clrf MODE_FAST movpf movpf #else movfp movwf movfp movwf #endif clrf clrf ACCbLO,tempLo ACCbHI,tempHi ACCbLO,WREG tempLo ACCbHI,WREG empHi ACCdHI, ACCdLO, count, count,4 count
0050 2922 0051 8422
0052 5A20 0053 5B21
0054 291F 0055 291E
0056 0056 0057 0058 0059 005A 005B 005C 005D 005E 005E 005F 0060 0061 0062 0063
1921 1920 9004 C05E 6A18 0F1E 6A19 111F 191F 191E 191D 191C 1722 C056
0064 0002
shift right addwf times mpyLoop rrcf tempHi, rrcf tempLo, btfss ALUSTA,C goto NoAdd need addwf movfp ACCaLO,WREG addwf ACCdLO, ;addwf movfp ACCaHI,WREG addwfc ACCdHI, ;addwf NoAdd rrcf ACCdHI, rrcf ACCdLO, rrcf ACCcHI, rrcf ACCcLO, decfsz count, goto mpyLoop SIGNED btfss sign,MSB return comf ACCcLO, incf ACCcLO, btfsc ALUSTA,Z decf ACCcHI, comf ACCcHI, btfsc ALUSTA,Z decf ACCdLO, comf ACCdLO, btfsc ALUSTA,Z decf ACCdHI, comf ACCdHI, return #else return #endif Assemble this section only Signed Arithmetic Needed SIGNED S_SIGN movfp ACCaHI,WREG xorwf ACCbHI,W movwf sign sign determines whether signed
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00381 00382 00383 00384 00385 00386 00387 00388 00389 00390 00391 00392 00393 00394 00395 00396 00397 00398 00399 00400 00401 00402 00403 00404 00405 00406 00407 00408 00409 00410 00411 00412 00413 00414 00415 00416 00417 00418 00419 00420 00421 00422 00423 00424 00425 00426 00427 00428 00429 00430 00431 00432 00433 00434 00435 00436 00437 00438 00439 00440 00441 00442 00443 00444 00445 00446 btfss goto comf incf btfsc decf comf chek_A btfss return comf incf btfsc decf comf return #endif PAGE Double Precision Multiplication Optimized Speed straight Line Code Multiplication ACCb(16 bits) ACCa(16 bits) ACCd,ACCc bits Load operand location ACCaLO ACCaHI bits Load operand location ACCbLO ACCbHI bits CALL D_mpy result location ACCdHI,ACCdLO,ACCdHI,ACCdLO Performance Program Memory (UNSIGNED) (SIGNED) Clock Cycles (UNSIGNED :excluding CALL RETURN) (SIGNED :excluding CALL RETURN) Note above timing worst case timing, when register ACCb FFFF. speed improved register ACCb contains number numbers with less number performance specs Unsigned arithmetic i.e, with "SIGNED FALSE Upon return from subroutine, input registers Multiplication Macro mulMac MACRO variable variable SIGNED variable MUL_LP_CNT #else variable MUL_LP_CNT #endif .while MUL_LP_CNT ACCaHI,MSB ACCaLO, ACCaLO, ALUSTA,Z ACCaHI, ACCaHI, negate ACCa ACCbHI,MSB chek_A ACCbLO, ACCbLO, ALUSTA,Z ACCbHI, ACCbHI, negate ACCb
negate ACCb
negate ACCa
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00447 00448 00449 00450 00451 00452 00453 00454 00455 00456 00457 00458 00459 00460 00461 00462 00463 00464 00465 00466 00467 00468 00469 00470 00471 00472 00473 00474 00475 00476 00477 00478 00479 00480 00481 00482 00483 00484 00485 00486 00487 00488 00489 00490 00491 00492 00493 00494 00495 00496 00497 00498 00499 00500 00501 00502 00503 00504 00505 00506 00507 00508 00509 00510 00511 00512 btfss .else btfss goto movfp addwf movfp addwfc NoAdd#v(i) rrcf rrcf rrcf rrcf variable .endw SIGNED rrcf rrcf rrcf rrcf #endif ENDM PAGE Double Precision Negate Macros AltNegMac MACRO fileRegLo,fileRegHi movfp fileRegLo,WREG negw fileRegLo, movfp fileRegHi,WREG clrf fileRegHi, subwfb fileRegHi, ENDM negMac ACCdHI, ACCdLO, ACCcHI, ACCcLO, ALUSTA,C ACCbLO,i ACCbHI,i-8 NoAdd#v(i) ACCaLO,WREG ACCdLO, ACCaHI,WREG ACCdHI, test byte test high byte need addwf ;addwf ;addwf
ACCdHI, ACCdLO, ACCcHI, ACCcLO, ALUSTA,C
MACRO comf incf btfsc decf comf ENDM
fileRegLo, fileRegLo, fileRegLo, ALUSTA,Z fileRegHi, fileRegHi,
fileRegHi negate FileReg -FileReg FileReg
NegMac32 movfp negw movfp clrf subwfb movfp clrf subwfb movfp clrf subwfb
MACRO x3,x2,x1,x0 x3,WREG x2,WREG x1,WREG x0,WREG ENDM
PAGE Double Precision Multiply 16x16 ACCb*ACCa ACCb,ACCc output with high word
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0065 00513 00514 00515 00516 00517 00518 00519 00520 00521 00522 00523 00524 00525 00526 00527 00528 00529 00530 00531 00532 00533 00534 00535 00536 00537 00538 00539 00540 00541 00542 ACCd ACCdHI,ACCdLO word ACCc ACCcHI,ACCcLO D_mpyF ;results ACCd(16 msb's) ACCc(16 lsb's) SIGNED movfp ACCaHI,WREG xorwf ACCbHI,W movwf sign btfss ACCbHI,MSB negate ACCb goto chek_A_MSB_MPY negMac ACCbLO,ACCbHI chek_A_MSB_MPY btfss ACCaHI,MSB negate ACCa goto continue_MPY negMac ACCaLO,ACCaHI #endif continue_MPY clrf ACCdHI, clrf ACCdLO, ALUSTA,C mulMac macro times mulMac variable variable SIGNED variable MUL_LP_CNT #else variable MUL_LP_CNT #endif .while MUL_LP_CNT btfss .else btfss goto movfp addwf movfp addwfc NoAdd0 rrcf rrcf rrcf rrcf variable btfss .else btfss goto movfp ACCbLO,i ACCbHI,i-8 NoAdd1 ACCaLO,WREG test byte test high byte need addwf ACCdHI, ACCdLO, ACCcHI, ACCcLO, ALUSTA,C ACCbLO,i ACCbHI,i-8 NoAdd0 ACCaLO,WREG ACCdLO, ACCaHI,WREG ACCdHI, test byte test high byte need addwf addwf addwf
0065 0065 291F 0066 291E 0067 8804
0000 0000
0010
0068 901A
0069 C06E 006A 6A18 006B 0F1E 006C 6A19 006D 111F 006E 006E 191F 006F 191E 0070 191D 0071 191C 0072 8804 0001
0073 911A
0074 C079 0075 6A18
1997 Microchip Technology Inc.
DS00544D-page 4-15
AN544
0076 0F1E 0077 6A19 0078 111F 0079 0079 191F 007A 191E 007B 191D 007C 191C 007D 8804 0002 addwf movfp addwfc NoAdd1 rrcf rrcf rrcf rrcf variable btfss .else btfss goto movfp addwf movfp addwfc NoAdd2 rrcf rrcf rrcf rrcf variable btfss .else btfss goto movfp addwf movfp addwfc NoAdd3 rrcf rrcf rrcf rrcf variable btfss .else btfss goto movfp addwf movfp addwfc NoAdd4 rrcf rrcf rrcf rrcf variable ACCdHI, ACCdLO, ACCcHI, ACCcLO, ALUSTA,C ACCbLO,i ACCbHI,i-8 NoAdd4 ACCaLO,WREG ACCdLO, ACCaHI,WREG ACCdHI, test byte test high byte need addwf addwf addwf ACCdHI, ACCdLO, ACCcHI, ACCcLO, ALUSTA,C ACCbLO,i ACCbHI,i-8 NoAdd3 ACCaLO,WREG ACCdLO, ACCaHI,WREG ACCdHI, test byte test high byte need addwf addwf addwf ACCdHI, ACCdLO, ACCcHI, ACCcLO, ALUSTA,C ACCbLO,i ACCbHI,i-8 NoAdd2 ACCaLO,WREG ACCdLO, ACCaHI,WREG ACCdHI, test byte test high byte need addwf addwf addwf ACCdHI, ACCdLO, ACCcHI, ACCcLO, ALUSTA,C ACCdLO, ACCaHI,WREG ACCdHI, ;addwf ;addwf
007E 921A
007F C084 0080 6A18 0081 0F1E 0082 6A19 0083 111F 0084 0084 191F 0085 191E 0086 191D 0087 191C 0088 8804 0003
0089 931A
008A C08F 008B 6A18 008C 0F1E 008D 6A19 008E 111F 008F 008F 191F 0090 191E 0091 191D 0092 191C 0093 8804 0004
0094 941A
0095 C09A 0096 6A18 0097 0F1E 0098 6A19 0099 111F 009A 009A 191F 009B 191E 009C 191D 009D 191C 009E 8804 0005
DS00544D-page 4-16
1997 Microchip Technology Inc.
AN544
009F 951A btfss .else btfss goto movfp addwf movfp addwfc NoAdd5 rrcf rrcf rrcf rrcf variable btfss .else btfss goto movfp addwf movfp addwfc NoAdd6 rrcf rrcf rrcf rrcf variable btfss .else btfss goto movfp addwf movfp addwfc NoAdd7 rrcf rrcf rrcf rrcf variable btfss .else btfss goto movfp addwf movfp addwfc NoAdd8 rrcf rrcf ACCdHI, ACCdLO, ACCbLO,i ACCbHI,i-8 NoAdd8 ACCaLO,WREG ACCdLO, ACCaHI,WREG ACCdHI, test byte test high byte need addwf addwf addwf ACCdHI, ACCdLO, ACCcHI, ACCcLO, ALUSTA,C ACCbLO,i ACCbHI,i-8 NoAdd7 ACCaLO,WREG ACCdLO, ACCaHI,WREG ACCdHI, test byte test high byte need addwf addwf addwf ACCdHI, ACCdLO, ACCcHI, ACCcLO, ALUSTA,C ACCbLO,i ACCbHI,i-8 NoAdd6 ACCaLO,WREG ACCdLO, ACCaHI,WREG ACCdHI, test byte test high byte need addwf addwf addwf ACCdHI, ACCdLO, ACCcHI, ACCcLO, ALUSTA,C ACCbLO,i ACCbHI,i-8 NoAdd5 ACCaLO,WREG ACCdLO, ACCaHI,WREG ACCdHI, test byte test high byte need addwf addwf addwf
00A0 C0A5 00A1 6A18 00A2 0F1E 00A3 6A19 00A4 111F 00A5 00A5 191F 00A6 191E 00A7 191D 00A8 191C 00A9 8804 0006
00AA 961A
00AB C0B0 00AC 6A18 00AD 0F1E 00AE 6A19 00AF 111F 00B0 00B0 191F 00B1 191E 00B2 191D 00B3 191C 00B4 8804 0007
00B5 971A
00B6 C0BB 00B7 6A18 00B8 0F1E 00B9 6A19 00BA 111F 00BB 00BB 191F 00BC 191E 00BD 191D 00BE 191C 00BF 8804 0008
00C0 901B 00C1 00C2 00C3 00C4 00C5 00C6 00C6 00C7 C0C6 6A18 0F1E 6A19 111F 191F 191E
1997 Microchip Technology Inc.
DS00544D-page 4-17
AN544
00C8 191D 00C9 191C 00CA 8804 0009 rrcf rrcf variable btfss .else btfss goto movfp addwf movfp addwfc NoAdd9 rrcf rrcf rrcf rrcf variable btfss .else btfss goto movfp addwf movfp addwfc NoAdd10 rrcf rrcf rrcf rrcf variable btfss .else btfss goto movfp addwf movfp addwfc NoAdd11 rrcf rrcf rrcf rrcf variable btfss .else btfss goto movfp ACCbLO,i ACCbHI,i-8 NoAdd12 ACCaLO,WREG test byte test high byte need addwf ACCdHI, ACCdLO, ACCcHI, ACCcLO, ALUSTA,C ACCbLO,i ACCbHI,i-8 NoAdd11 ACCaLO,WREG ACCdLO, ACCaHI,WREG ACCdHI, test byte test high byte need addwf addwf addwf ACCdHI, ACCdLO, ACCcHI, ACCcLO, ALUSTA,C ACCbLO,i ACCbHI,i-8 NoAdd10 ACCaLO,WREG ACCdLO, ACCaHI,WREG ACCdHI, test byte test high byte need addwf addwf addwf ACCdHI, ACCdLO, ACCcHI, ACCcLO, ALUSTA,C ACCbLO,i ACCbHI,i-8 NoAdd9 ACCaLO,WREG ACCdLO, ACCaHI,WREG ACCdHI, test byte test high byte need addwf addwf addwf ACCcHI, ACCcLO, ALUSTA,C
00CB 911B 00CC C0D1 00CD 6A18 00CE 0F1E 00CF 6A19 00D0 111F 00D1 00D1 191F 00D2 191E 00D3 191D 00D4 191C 00D5 8804 000A
00D6 921B 00D7 C0DC 00D8 6A18 00D9 0F1E 00DA 6A19 00DB 111F 00DC 00DC 191F 00DD 191E 00DE 191D 00DF 191C 00E0 8804 000B
00E1 931B 00E2 C0E7 00E3 6A18 00E4 0F1E 00E5 6A19 00E6 111F 00E7 00E7 191F 00E8 191E 00E9 191D 00EA 191C 00EB 8804 000C
00EC 941B 00ED C0F2 00EE 6A18
DS00544D-page 4-18
1997 Microchip Technology Inc.
AN544
00EF 0F1E 00F0 6A19 00F1 111F 00F2 00F2 191F 00F3 191E 00F4 191D 00F5 191C 00F6 8804 000D addwf movfp addwfc NoAdd12 rrcf rrcf rrcf rrcf variable btfss .else btfss goto movfp addwf movfp addwfc NoAdd13 rrcf rrcf rrcf rrcf variable btfss .else btfss goto movfp addwf movfp addwfc NoAdd14 rrcf rrcf rrcf rrcf variable btfss .else btfss goto movfp addwf movfp addwfc NoAdd15 rrcf rrcf rrcf rrcf variable .endw SIGNED ACCdHI, ACCdLO, ACCcHI, ACCcLO, ALUSTA,C ACCbLO,i ACCbHI,i-8 NoAdd15 ACCaLO,WREG ACCdLO, ACCaHI,WREG ACCdHI, test byte test high byte need addwf addwf addwf ACCdHI, ACCdLO, ACCcHI, ACCcLO, ALUSTA,C ACCbLO,i ACCbHI,i-8 NoAdd14 ACCaLO,WREG ACCdLO, ACCaHI,WREG ACCdHI, test byte test high byte need addwf addwf addwf ACCdHI, ACCdLO, ACCcHI, ACCcLO, ALUSTA,C ACCbLO,i ACCbHI,i-8 NoAdd13 ACCaLO,WREG ACCdLO, ACCaHI,WREG ACCdHI, test byte test high byte need addwf addwf addwf ACCdHI, ACCdLO, ACCcHI, ACCcLO, ALUSTA,C ACCdLO, ACCaHI,WREG ACCdHI, ;addwf ;addwf
00F7 951B 00F8 C0FD 00F9 6A18 00FA 0F1E 00FB 6A19 00FC 111F 00FD 00FD 191F 00FE 191E 00FF 191D 0100 191C 0101 8804 000E
0102 961B 0103 C108 0104 6A18 0105 0F1E 0106 6A19 0107 111F 0108 0108 191F 0109 191E 010A 191D 010B 191C 010C 8804 000F
010D 971B 010E C113 010F 6A18 0110 0F1E 0111 6A19 0112 111F 0113 0113 191F 0114 191E 0115 191D 0116 191C 0117 8804 0010
1997 Microchip Technology Inc.
DS00544D-page 4-19
AN544
00543 00544 00545 00546 00547 00548 00549 00550 00551 00552 00553 00554 00555 00556 00557 00558 00559 00560 00561 00562 00563 00564 00565 00566 00567 00568 00569 00570 00571 00572 00573 00574 00575 00576 00577 00578 00579 00580 00581 00582 00583 00584 00585 00586 00587 00588 00589 00590 00591 00592 00593 00594 00595 00596 00597 00598 00599 00600 00601 rrcf rrcf rrcf rrcf #endif SIGNED btfss sign,MSB negate (ACCc,ACCd) return NegMac32 ACCcHI,ACCcLO,ACCdHI, ACCdLO return #else return #endif PAGE Double Precision Division Optimized Code Looped Code Division ACCb(16 bits) ACCa(16 bits) ACCb(16 bits) with Remainder ACCc bits) Load Denominator location ACCaHI ACCaLO bits Load Numerator location ACCbHI ACCbLO bits CALL D_div result location ACCbHI ACCbLO Remainder locations ACCcHI ACCcLO Performance Program Memory (UNSIGNED) (SIGNED) Clock Cycles (UNSIGNED excluding CALL RETURN) (SIGNED excluding CALL RETURN) NOTE performance specs Unsigned arithmetic i.e, with "SIGNED FALSE Double Precision Divide 16/16 ACCb/ACCa ACCb with remainder ACCc output with Quotiont ACCb (ACCbHI,ACCbLO) Remainder ACCc (ACCcHI,ACCcLO). (R)/A where Numerator Denominator Quotiont (Integer Result) Remainder Note Check ZERO Denominator Numerator performed ZERO Denominator will produce incorrect results SIGNED Arithmetic case signed arithmetic, either numerator denominator negative, then both represented negative numbers -(B/A) -(Q) (-R)/A (-Q)*A (-R) ACCdHI, ACCdLO, ACCcHI, ACCcLO, ALUSTA,C
0118 0002
DS00544D-page 4-20
1997 Microchip Technology Inc.
AN544
0119 0119 8404 011A 8504 00602 00603 00604 00605 00606 00607 00608 00609 00610 00611 00612 00613 00614 00615 00616 00617 00618 00619 00620 00621 00622 00623 00624 00625 00626 00627 00628 00629 00630 00631 00632 00633 00634 00635 00636 00637 00638 00639 00640 00641 00642 00643 00644 00645 00646 00647 00648 00649 00650 00651 00652 00653 00654 00655 00656 00657 00658 00659 00660 00661 00662 00663 00664 00665 00666 00667 D_divS ALUSTA,FS0 ALUSTA,FS1 auto-incrment fsr0 CALL #endif clrf clrf clrf clrf clrf Looped code divLoop rlcf rlcf rlcf rlcf movfp subwf btfss goto movfp subwf notz btfss goto subca movfp subwf movfp subwfb nosub rlcf rlcf decfsz goto SIGNED btfss return movlw movwf call movlw movwf call return #else return #endif PAGE Double Precision Division sign,MSB ACCcLO fsr0 negate ACCdLO fsr0 negate count, count,4 ACCcHI, ACCcLO, ACCdLO, ACCdHI, count SIGNED S_SIGN
011B 011C 011D 011E 011F 0120
2922 8422 291D 291C 291E 291F
0121 0121 0122 0123 0124 0125 0126 0127 0128 0129 012A 012B 012C 012C 012D 012E 012E 012F 0130 0131 0132 0133 0133 0134 0135 0136
8804 1B1A 1B1B 1B1C 1B1D 6A19 041D 9204 C12C 6A18 041C 9004 C133 6A18 051C 6A19 031D 8004 1B1E 1B1F 1722 C121
ALUSTA,C ACCbLO, ACCbHI, ACCcLO, ACCcHI, ACCaHI,WREG ACCcHI,W ALUSTA,Z notz ACCaLO,WREG ACCcLO,W ALUSTA,C nosub ACCaLO,WREG ACCcLO, ACCaHI,WREG ACCcHI, ALUSTA,C ACCdLO, ACCdHI, count, divLoop
check
equal then check carry into
shift into (result)
0137 0002
1997 Microchip Technology Inc.
DS00544D-page 4-21
AN544
00668 00669 00670 00671 00672 00673 00674 00675 00676 00677 00678 00679 00680 00681 00682 00683 00684 00685 00686 00687 00688 00689 00690 00691 00692 00693 00694 00695 00696 00697 00698 00699 00700 00701 00702 00703 00704 00705 00706 00707 00708 00709 00710 00711 00712 00713 00714 00715 00716 00717 00718 00719 00720 00721 00722 00723 00724 00725 00726 00727 00728 00729 00730 00731 00732 00733 Optimized Speed straight Line Code Division ACCb(16 bits) ACCa(16 bits) ACCb(16 bits) with Remainder ACCc bits) Load Denominator location ACCaHI ACCaLO bits Load Numerator location ACCbHI ACCbLO bits CALL D_div result location ACCbHI ACCbLO Remainder locations ACCcHI ACCcLO (R)/A where Numerator Denominator Quotiont (Integer Result) Remainder Note Check ZERO Denominator Numerator performed ZERO Denominator will produce incorrect results SIGNED Arithmetic case signed arithmetic, either numerator denominator negative, then both represented negative numbers -(B/A) -(Q) (-R)/A (-Q)*A (-R) Performance Program Memory (UNSIGNED) (SIGNED) Clock Cycles (UNSIGNED excluding CALL RETURN) (SIGNED excluding CALL RETURN) division macro divMac MACRO variable variable .while rlcf rlcf rlcf rlcf movfp subwf btfss goto movfp subwf notz#v(i) btfss goto subca#v(i) movfp subwf movfp subwfb nosub#v(i) rlcf rlcf variable i=i+1 ALUSTA,C ACCbLO, ACCbHI, ACCcLO, ACCcHI, ACCaHI,WREG ACCcHI,W ALUSTA,Z notz#v(i) ACCaLO,WREG ACCcLO,W ALUSTA,C nosub#v(i) ACCaLO,WREG ACCcLO, ACCaHI,WREG ACCcHI, ALUSTA,C ACCdLO, ACCdHI,
check
equal then check carry into
shift into (result)
DS00544D-page 4-22
1997 Microchip Technology Inc.
AN544
00734 00735 00736 00737 00738 00739 00740 00741 00742 00743 00744 00745 00746 00747 00748 00749 00750 00751 00752 00753 00754 00755 00756 00757 00758 00759 00760 00761 00762 00763 00764 00765 00766 00767 00768 00769 00770 00771 00772 00773 00774 00775 00776 00777 00778 00779 00780 00781 .endw ENDM PAGE Double Precision Divide 16/16 ACCb/ACCa ACCb with remainder ACCc output with Quotiont ACCb (ACCbHI,ACCbLO) Remainder ACCc (ACCcHI,ACCcLO). NOTE Before calling this routine, user should make sure that Numerator(ACCb) greater than Denominator(ACCa). case true, user should scale either Numerator Denominator both such that Numerator greater than Denominator. D_divF SIGNED movfp ACCaHI,WREG xorwf ACCbHI,W movwf sign btfss ACCbHI,MSB negate ACCb goto chek_A_MSB_DIV negMac ACCbLO,ACCbHI chek_A_MSB_DIV btfss ACCaHI,MSB negate ACCa goto continue_DIV negMac ACCaLO,ACCaHI #endif continue_DIV clrf clrf clrf clrf
0138
0138 0138 0139 013A 013B
291D 291C 291E 291F
ACCcHI, ACCcLO, ACCdLO, ACCdHI,
0000 0000
straight line code using macro divMac divMac variable variable .while rlcf rlcf rlcf rlcf movfp subwf btfss goto movfp subwf btfss goto ALUSTA,C ACCbLO, ACCbHI, ACCcLO, ACCcHI, ACCaHI,WREG ACCcHI,W ALUSTA,Z notz0 ACCaLO,WREG ACCcLO,W ALUSTA,C nosub0
013C 013D 013E 013F 0140 0141 0142 0143 0144 0145 0146 0147 0148
8804 1B1A 1B1B 1B1C 1B1D 6A19 041D 9204 C147 6A18 041C 9004 C14E
check
notz0
equal then check carry
1997 Microchip Technology Inc.
DS00544D-page 4-23
AN544
0149 6A18 014A 051C 014B 6A19 014C 031D 014D 8004 014E 1B1E 014F 1B1F 0001 0150 8804 0151 1B1A 0152 1B1B 0153 1B1C 0154 1B1D 0155 6A19 0156 041D 0157 9204 0158 C15B 0159 6A18 015A 041C 015B 9004 015C C162 015D 6A18 015E 051C 015F 6A19 0160 031D 0161 8004 0162 1B1E 0163 1B1F 0002 0164 8804 0165 1B1A 0166 1B1B 0167 1B1C 0168 1B1D 0169 6A19 016A 041D 016B 9204 016C C16F 016D 6A18 016E 041C 016F 9004 0170 C176 0171 6A18 0172 051C 0173 6A19 0174 031D 0175 8004 0176 1B1E 0177 1B1F 0003 0178 0179 017A 017B 017C 017D 017E 017F 0180 0181 0182 0183 0184 8804 1B1A 1B1B 1B1C 1B1D 6A19 041D 9204 C183 6A18 041C 9004 C18A subca0 movfp subwf movfp subwfb nosub0 rlcf rlcf variable i=i+1 rlcf rlcf rlcf rlcf movfp subwf btfss goto movfp subwf notz1 btfss goto subca1 movfp subwf movfp subwfb nosub1 rlcf rlcf variable i=i+1 rlcf rlcf rlcf rlcf movfp subwf btfss goto movfp subwf notz2 btfss goto subca2 movfp subwf movfp subwfb nosub2 rlcf rlcf variable i=i+1 rlcf rlcf rlcf rlcf movfp subwf btfss goto movfp subwf notz3 btfss goto ACCaLO,WREG ACCcLO, ACCaHI,WREG ACCcHI, ALUSTA,C ACCdLO, ACCdHI, into
shift into (result)
ALUSTA,C ACCbLO, ACCbHI, ACCcLO, ACCcHI, ACCaHI,WREG ACCcHI,W ALUSTA,Z notz1 ACCaLO,WREG ACCcLO,W ALUSTA,C nosub1 ACCaLO,WREG ACCcLO, ACCaHI,WREG ACCcHI, ALUSTA,C ACCdLO, ACCdHI,
check
equal then check carry into
shift into (result)
ALUSTA,C ACCbLO, ACCbHI, ACCcLO, ACCcHI, ACCaHI,WREG ACCcHI,W ALUSTA,Z notz2 ACCaLO,WREG ACCcLO,W ALUSTA,C nosub2 ACCaLO,WREG ACCcLO, ACCaHI,WREG ACCcHI, ALUSTA,C ACCdLO, ACCdHI,
check
equal then check carry into
shift into (result)
ALUSTA,C ACCbLO, ACCbHI, ACCcLO, ACCcHI, ACCaHI,WREG ACCcHI,W ALUSTA,Z notz3 ACCaLO,WREG ACCcLO,W ALUSTA,C nosub3
check
equal then check carry
DS00544D-page 4-24
1997 Microchip Technology Inc.
AN544
0185 6A18 0186 051C 0187 6A19 0188 031D 0189 8004 018A 1B1E 018B 1B1F 0004 018C 8804 018D 1B1A 018E 1B1B 018F 1B1C 0190 1B1D 0191 6A19 0192 041D 0193 9204 0194 C197 0195 6A18 0196 041C 0197 9004 0198 C19E 0199 6A18 019A 051C 019B 6A19 019C 031D 019D 8004 019E 1B1E 019F 1B1F 0005 01A0 8804 01A1 1B1A 01A2 1B1B 01A3 1B1C 01A4 1B1D 01A5 6A19 01A6 041D 01A7 9204 01A8 C1AB 01A9 6A18 01AA 041C 01AB 9004 01AC C1B2 01AD 6A18 01AE 051C 01AF 6A19 01B0 031D 01B1 8004 01B2 1B1E 01B3 1B1F 0006 01B4 01B5 01B6 01B7 01B8 01B9 01BA 01BB 01BC 01BD 01BE 01BF 01C0 8804 1B1A 1B1B 1B1C 1B1D 6A19 041D 9204 C1BF 6A18 041C 9004 C1C6 subca3 movfp subwf movfp subwfb nosub3 rlcf rlcf variable i=i+1 rlcf rlcf rlcf rlcf movfp subwf btfss goto movfp subwf notz4 btfss goto subca4 movfp subwf movfp subwfb nosub4 rlcf rlcf variable i=i+1 rlcf rlcf rlcf rlcf movfp subwf btfss goto movfp subwf notz5 btfss goto subca5 movfp subwf movfp subwfb nosub5 rlcf rlcf variable i=i+1 rlcf rlcf rlcf rlcf movfp subwf btfss goto movfp subwf notz6 btfss goto ACCaLO,WREG ACCcLO, ACCaHI,WREG ACCcHI, ALUSTA,C ACCdLO, ACCdHI, into
shift into (result)
ALUSTA,C ACCbLO, ACCbHI, ACCcLO, ACCcHI, ACCaHI,WREG ACCcHI,W ALUSTA,Z notz4 ACCaLO,WREG ACCcLO,W ALUSTA,C nosub4 ACCaLO,WREG ACCcLO, ACCaHI,WREG ACCcHI, ALUSTA,C ACCdLO, ACCdHI,
check
equal then check carry into
shift into (result)
ALUSTA,C ACCbLO, ACCbHI, ACCcLO, ACCcHI, ACCaHI,WREG ACCcHI,W ALUSTA,Z notz5 ACCaLO,WREG ACCcLO,W ALUSTA,C nosub5 ACCaLO,WREG ACCcLO, ACCaHI,WREG ACCcHI, ALUSTA,C ACCdLO, ACCdHI,
check
equal then check carry into
shift into (result)
ALUSTA,C ACCbLO, ACCbHI, ACCcLO, ACCcHI, ACCaHI,WREG ACCcHI,W ALUSTA,Z notz6 ACCaLO,WREG ACCcLO,W ALUSTA,C nosub6
check
equal then check carry
1997 Microchip Technology Inc.
DS00544D-page 4-25
AN544
01C1 6A18 01C2 051C 01C3 6A19 01C4 031D 01C5 8004 01C6 1B1E 01C7 1B1F 0007 01C8 8804 01C9 1B1A 01CA 1B1B 01CB 1B1C 01CC 1B1D 01CD 6A19 01CE 041D 01CF 9204 01D0 C1D3 01D1 6A18 01D2 041C 01D3 9004 01D4 C1DA 01D5 6A18 01D6 051C 01D7 6A19 01D8 031D 01D9 8004 01DA 1B1E 01DB 1B1F 0008 01DC 8804 01DD 1B1A 01DE 1B1B 01DF 1B1C 01E0 1B1D 01E1 6A19 01E2 041D 01E3 9204 01E4 C1E7 01E5 6A18 01E6 041C 01E7 9004 01E8 C1EE 01E9 6A18 01EA 051C 01EB 6A19 01EC 031D 01ED 8004 01EE 1B1E 01EF 1B1F 0009 01F0 01F1 01F2 01F3 01F4 01F5 01F6 01F7 01F8 01F9 01FA 01FB 01FC 8804 1B1A 1B1B 1B1C 1B1D 6A19 041D 9204 C1FB 6A18 041C 9004 C202 subca6 movfp subwf movfp subwfb nosub6 rlcf rlcf variable i=i+1 rlcf rlcf rlcf rlcf movfp subwf btfss goto movfp subwf notz7 btfss goto subca7 movfp subwf movfp subwfb nosub7 rlcf rlcf variable i=i+1 rlcf rlcf rlcf rlcf movfp subwf btfss goto movfp subwf notz8 btfss goto subca8 movfp subwf movfp subwfb nosub8 rlcf rlcf variable i=i+1 rlcf rlcf rlcf rlcf movfp subwf btfss goto movfp subwf notz9 btfss goto ACCaLO,WREG ACCcLO, ACCaHI,WREG ACCcHI, ALUSTA,C ACCdLO, ACCdHI, into
shift into (result)
ALUSTA,C ACCbLO, ACCbHI, ACCcLO, ACCcHI, ACCaHI,WREG ACCcHI,W ALUSTA,Z notz7 ACCaLO,WREG ACCcLO,W ALUSTA,C nosub7 ACCaLO,WREG ACCcLO, ACCaHI,WREG ACCcHI, ALUSTA,C ACCdLO, ACCdHI,
check
equal then check carry into
shift into (result)
ALUSTA,C ACCbLO, ACCbHI, ACCcLO, ACCcHI, ACCaHI,WREG ACCcHI,W ALUSTA,Z notz8 ACCaLO,WREG ACCcLO,W ALUSTA,C nosub8 ACCaLO,WREG ACCcLO, ACCaHI,WREG ACCcHI, ALUSTA,C ACCdLO, ACCdHI,
check
equal then check carry into
shift into (result)
ALUSTA,C ACCbLO, ACCbHI, ACCcLO, ACCcHI, ACCaHI,WREG ACCcHI,W ALUSTA,Z notz9 ACCaLO,WREG ACCcLO,W ALUSTA,C nosub9
check
equal then check carry
DS00544D-page 4-26
1997 Microchip Technology Inc.
AN544
01FD 6A18 01FE 051C 01FF 6A19 0200 031D 0201 8004 0202 1B1E 0203 1B1F 000A 0204 8804 0205 1B1A 0206 1B1B 0207 1B1C 0208 1B1D 0209 6A19 020A 041D 020B 9204 020C C20F 020D 6A18 020E 041C 020F 9004 0210 C216 0211 6A18 0212 051C 0213 6A19 0214 031D 0215 8004 0216 1B1E 0217 1B1F 000B 0218 8804 0219 1B1A 021A 1B1B 021B 1B1C 021C 1B1D 021D 6A19 021E 041D 021F 9204 0220 C223 0221 6A18 0222 041C 0223 9004 0224 C22A 0225 6A18 0226 051C 0227 6A19 0228 031D 0229 8004 022A 1B1E 022B 1B1F 000C 022C 022D 022E 022F 0230 0231 0232 0233 0234 0235 0236 0237 0238 8804 1B1A 1B1B 1B1C 1B1D 6A19 041D 9204 C237 6A18 041C 9004 C23E subca9 movfp subwf movfp subwfb nosub9 rlcf rlcf variable i=i+1 rlcf rlcf rlcf rlcf movfp subwf btfss goto movfp subwf notz10 btfss goto subca10 movfp subwf movfp subwfb nosub10 rlcf rlcf variable i=i+1 rlcf rlcf rlcf rlcf movfp subwf btfss goto movfp subwf notz11 btfss goto subca11 movfp subwf movfp subwfb nosub11 rlcf rlcf variable i=i+1 rlcf rlcf rlcf rlcf movfp subwf btfss goto movfp subwf notz12 btfss goto ACCaLO,WREG ACCcLO, ACCaHI,WREG ACCcHI, ALUSTA,C ACCdLO, ACCdHI, into
shift into (result)
ALUSTA,C ACCbLO, ACCbHI, ACCcLO, ACCcHI, ACCaHI,WREG ACCcHI,W ALUSTA,Z notz10 ACCaLO,WREG ACCcLO,W ALUSTA,C nosub10 ACCaLO,WREG ACCcLO, ACCaHI,WREG ACCcHI, ALUSTA,C ACCdLO, ACCdHI,
check
equal then check carry into
shift into (result)
ALUSTA,C ACCbLO, ACCbHI, ACCcLO, ACCcHI, ACCaHI,WREG ACCcHI,W ALUSTA,Z notz11 ACCaLO,WREG ACCcLO,W ALUSTA,C nosub11 ACCaLO,WREG ACCcLO, ACCaHI,WREG ACCcHI, ALUSTA,C ACCdLO, ACCdHI,
check
equal then check carry into
shift into (result)
ALUSTA,C ACCbLO, ACCbHI, ACCcLO, ACCcHI, ACCaHI,WREG ACCcHI,W ALUSTA,Z notz12 ACCaLO,WREG ACCcLO,W ALUSTA,C nosub12
check
equal then check carry
1997 Microchip Technology Inc.
DS00544D-page 4-27
AN544
0239 6A18 023A 051C 023B 6A19 023C 031D 023D 8004 023E 1B1E 023F 1B1F 000D 0240 8804 0241 1B1A 0242 1B1B 0243 1B1C 0244 1B1D 0245 6A19 0246 041D 0247 9204 0248 C24B 0249 6A18 024A 041C 024B 9004 024C C252 024D 6A18 024E 051C 024F 6A19 0250 031D 0251 8004 0252 1B1E 0253 1B1F 000E 0254 8804 0255 1B1A 0256 1B1B 0257 1B1C 0258 1B1D 0259 6A19 025A 041D 025B 9204 025C C25F 025D 6A18 025E 041C 025F 9004 0260 C266 0261 6A18 0262 051C 0263 6A19 0264 031D 0265 8004 0266 1B1E 0267 1B1F 000F 0268 0269 026A 026B 026C 026D 026E 026F 0270 0271 0272 0273 0274 8804 1B1A 1B1B 1B1C 1B1D 6A19 041D 9204 C273 6A18 041C 9004 C27A subca12 movfp subwf movfp subwfb nosub12 rlcf rlcf variable i=i+1 rlcf rlcf rlcf rlcf movfp subwf btfss goto movfp subwf notz13 btfss goto subca13 movfp subwf movfp subwfb nosub13 rlcf rlcf variable i=i+1 rlcf rlcf rlcf rlcf movfp subwf btfss goto movfp subwf notz14 btfss goto subca14 movfp subwf movfp subwfb nosub14 rlcf rlcf variable i=i+1 rlcf rlcf rlcf rlcf movfp subwf btfss goto movfp subwf notz15 btfss goto ACCaLO,WREG ACCcLO, ACCaHI,WREG ACCcHI, ALUSTA,C ACCdLO, ACCdHI, into
shift into (result)
ALUSTA,C ACCbLO, ACCbHI, ACCcLO, ACCcHI, ACCaHI,WREG ACCcHI,W ALUSTA,Z notz13 ACCaLO,WREG ACCcLO,W ALUSTA,C nosub13 ACCaLO,WREG ACCcLO, ACCaHI,WREG ACCcHI, ALUSTA,C ACCdLO, ACCdHI,
check
equal then check carry into
shift into (result)
ALUSTA,C ACCbLO, ACCbHI, ACCcLO, ACCcHI, ACCaHI,WREG ACCcHI,W ALUSTA,Z notz14 ACCaLO,WREG ACCcLO,W ALUSTA,C nosub14 ACCaLO,WREG ACCcLO, ACCaHI,WREG ACCcHI, ALUSTA,C ACCdLO, ACCdHI,
check
equal then check carry into
shift into (result)
ALUSTA,C ACCbLO, ACCbHI, ACCcLO, ACCcHI, ACCaHI,WREG ACCcHI,W ALUSTA,Z notz15 ACCaLO,WREG ACCcLO,W ALUSTA,C nosub15
check
equal then check carry
DS00544D-page 4-28
1997 Microchip Technology Inc.
AN544
0275 6A18 0276 051C 0277 6A19 0278 031D 0279 8004 027A 1B1E 027B 1B1F 0010 00782 00783 00784 00785 00786 00787 00788 00789 00790 00791 00792 00793 00794 00795 00796 00797 00798 00799 00800 00801 00802 00803 00804 00805 00806 00807 00808 00809 00810 00811 00812 00813 00814 00815 00816 00817 00818 00819 00820 00821 00822 00823 00824 00825 00826 00827 00828 00829 00830 00831 00832 00833 00834 00835 00836 00837 subca15 movfp ACCaLO,WREG into subwf ACCcLO, movfp ACCaHI,WREG subwfb ACCcHI, ALUSTA,C shift into (result) nosub15 rlcf ACCdLO, rlcf ACCdHI, variable i=i+1 .endw SIGNED btfss sign,MSB negate (ACCc,ACCd) return negMac ACCcLO,ACCcHI negMac ACCdLO,ACCdHI return #else return #endif PAGE Square Root Newton Raphson Method This routine computes square root number(with byte NumLo high byte NumHi After loading NumLo NumHi with desired number whose square root computed, branch location Sqrt "GOTO Sqrt" CALL Sqrt" cannot issued because Sqrt function makes calls Math routines stack completely used result sqrt(NumHi,NumLo) returned location SqrtLo. total number iterations ten. more iterations desired, change "LupCnt .10" desired value. Also, initial guess value square root given input/2 subroutine "init" user modify this scheme better initial approximation value known. good initial guess will help algorithm converge faster rate thus less number iterations required. utility math routines used this program D_divS D_add. These routines listed seperate routines under double precision Division double precision addition respectively. Note square root number desired, probably better have table look scheme rather than using numerical methods. This method computationally quite intensive slow, very accurate convergence rate high Performance Program Memory (excluding D_divS subroutine) Clock Cycles 3000 (approximately,with iterations) cycles depends Number Iterations Selected. cases less iterations sufficient Newton-Raphson Method Sqrt call nextIter SqrtInit compute initial sqrt Num/2
027C 0002
027D 027D E28B 027E
1997 Microchip Technology Inc.
DS00544D-page 4-29
AN544
027E 7A24 027F 7B25 00838 00839 00840 00841 00842 00843 00844 00845 00846 00847 00848 00849 00850 00851 00852 00853 00854 00855 00856 00857 00858 00859 00860 00861 00862 00863 00864 00865 00866 00867 00868 00869 00870 00871 00872 00873 00874 00875 00876 00877 00878 00879 00880 00881 00882 00883 00884 00885 00886 00887 00888 00889 00890 00891 00892 00893 00894 00895 00896 00897 00898 00899 00900 00901 00902 00903 MODE_FAST movfp movfp #else movfp movwf movfp movwf #endif call movfp addwf movfp addwfc rrcf rrcf decfsz goto return SqrtInit movlw movwf MODE_FAST movfp movfp #else movfp movwf movfp movwf #endif rrcf rrcf return PAGE Software Multiplier Fast Version Straight Line Code result stored bytes Before calling subroutine multiplier should loaded location mulplr multiplicand mulcnd result stored locations H_byte L_byte. Performance Program Memory words cycles (excluding call return) Scratch locations Register Used This routine optimized speed efficiency straight line code code efficiency, refer "mult8x8S.asm" looped code Define macro adding right shifting multiply MACRO _LUPCNT iterCnt NumHi,ACCaHI NumLo,ACCaLO NumHi,WREG ACCaHI NumLo,WREG ACCaLO ALUSTA,C ACCaHI, ACCaLO, number iterations iterCnt, nextIter Sqrt D_divS ACCdLO,WREG ACCaLO, ACCdHI,WREG ACCaHI, ALUSTA,C ACCaHI, ACCaLO, double precision division double precision addition ACCd ACCa ACCd addwf NumLo,ACCbLO NumHi,ACCbHI NumLo,WREG ACCbLO NumHi,WREG ACCbHI
0280 E119 0281 0282 0283 0284 6A1E 0F18 6A1F 1119
addwf divide
0285 8804 0286 1919 0287 1918 0288 1726 0289 C27E 028A 0002 028B 028B B00A 028C 0126 028D 7925 028E 7824
initial guess root NUM/2
028F 0290 0291 0292
8804 1919 1918 0002
initial sqrt Num/2
DS00544D-page 4-30
1997 Microchip Technology Inc.
AN544
00904 00905 00906 00907 00908 00909 00910 00911 00912 00913 00914 00915 00916 00917 00918 00919 00920 00921 00922 00923 00924 00925 variable variable .while btfsc mulplr,i addwf H_byte, rrcf H_byte, rrcf L_byte, variable .endw ENDM macro mpy8x8_F clrf clrf movfp multiply variable variable .while btfsc addwf rrcf rrcf variable btfsc addwf rrcf rrcf variable btfsc addwf rrcf rrcf variable btfsc addwf rrcf rrcf variable btfsc addwf rrcf rrcf variable btfsc addwf rrcf rrcf variable btfsc addwf rrcf rrcf variable btfsc addwf rrcf rrcf variable .endw return H_byte, L_byte, mulcnd,WREG ALUSTA,C
0293 0293 0294 0295 0296
291B 291A 6A18 8804
move multiplicand reg. Clear carry status Reg.
0000 0000 0297 9819 0298 0F1B 0299 191B 029A 191A 0001 029B 9919 029C 0F1B 029D 191B 029E 191A 0002 029F 9A19 02A0 0F1B 02A1 191B 02A2 191A 0003 02A3 9B19 02A4 0F1B 02A5 191B 02A6 191A 0004 02A7 9C19 02A8 0F1B 02A9 191B 02AA 191A 0005 02AB 9D19 02AC 0F1B 02AD 191B 02AE 191A 0006 02AF 9E19 02B0 0F1B 02B1 191B 02B2 191A 0007 02B3 9F19 02B4 0F1B 02B5 191B 02B6 191A 0008
mulplr,i H_byte, H_byte, L_byte, mulplr,i H_byte, H_byte, L_byte, mulplr,i H_byte, H_byte, L_byte, mulplr,i H_byte, H_byte, L_byte, mulplr,i H_byte, H_byte, L_byte, mulplr,i H_byte, H_byte, L_byte, mulplr,i H_byte, H_byte, L_byte, mulplr,i H_byte, H_byte, L_byte,
02B7 0002
1997 Microchip Technology Inc.
DS00544D-page 4-31
AN544
00926 00927 00928 00929 00930 00931 00932 00933 00934 00935 00936 00937 00938 00939 00940 00941 00942 00943 00944 00945 00946 00947 00948 00949 00950 00951 00952 00953 00954 00955 00956 00957 00958 00959 00960 00961 00962 00963 00964 00965 00966 00967 00968 00969 00970 00971 00972 00973 00974 00975 00976 00977 00978 00979 00980 00981 00982 00983 00984 00985 00986 00987 00988 00989 00990 00991 PAGE Software Multiplier Code Efficient Looped Code result stored bytes Before calling subroutine multiplier should loaded location mulplr multiplicand mulcnd result stored locations H_byte L_byte. Performance Program Memory words (excluding call return) cycles (excluding call return) Scratch byte Register Used This routine optimized code efficiency looped code time efficiency code refer "mult8x8F.asm" straight line code mpy8x8_S clrf H_byte, clrf L_byte, clrf count, count,3 count movfp mulcnd,WREG ALUSTA,C Clear carry status Reg. loop btfsc mulplr,0 addwf H_byte, rrcf H_byte, rrcf L_byte, rrncf mulplr, decfsz count, goto loop return PAGE Numerical Differenciation called "Three-Point Formula" implemented differenciate sequence points (uniformly sampled). implemented f'(Xn) f(Xn 4*f(Xn 3*f(Xn)]*0.5/h where present sample step size. above formula rewritten f'(Xn) 0.5*f(Xn 2*f(Xn 0.5*3*f(Xn)]*1/DiffK where DiffK Step Size This differenciation routine used very effectively computation differential component part Loop calculation Motor Control Applications Double precision arithmetic used throught present sample value assumed locations (XnHi, XnLo). past values assumed locations (Xn_1_Hi, Xn_1_Lo) (Xn_2_Hi, Xn_2_Lo). output value located DiffHi DiffLo. overflow checking mechanism implemented. values limited bits, then user need worry about overflows
02B8 02B8 02B9 02BA 02BB 02BC 02BD 02BE 02BE 02BF 02C0 02C1 02C2 02C3 02C4
291B 291A 2922 8322 6A18 8804 9819 0F1B 191B 191A 2119 1722 C2BE
02C5 0002
DS00544D-page 4-32
1997 Microchip Technology Inc.
AN544
00992 00993 00994 00995 00996 00997 00998 00999 01000 01001 01002 01003 01004 01005 01006 01007 01008 01009 01010 01011 01012 01013 01014 01015 01016 01017 01018 01019 01020 01021 01022 01023 01024 01025 01026 01027 01028 01029 01030 01031 01032 01033 01034 01035 01036 01037 01038 01039 01040 01041 01042 01043 01044 01045 01046 01047 01048 01049 01050 01051 01052 01053 01054 01055 01056 01057 user's responsibility update past values with present values before calling this routine. After computation, present value moved Xn_1 because user want these values intact other computations numerical integration) Also user's responsibility past values (Xn_1 Xn_2) values zero initialization. Diff movfp Xn_2_Lo,WREG addwf XnLo,W movwf ACCbLO movfp Xn_2_Hi,WREG addwfc XnHi,W movwf ACCbHI f(Xn-2) f(Xn) movfp XnLo,WREG addwf ACCbLO, movfp XnHi,WREG addwfc ACCbHI, movfp XnLo,WREG addwf ACCbLO, movfp XnHi,WREG addwfc ACCbHI, f(Xn-2) 3*f(Xn) ALUSTA,C rrcf ACCbHI, rrcf ACCbLO, 0.5*[ f(Xn-2) 3*f(Xn) movfp subwf movfp subwfb movfp subwf movfp subwfb movfp movwf movfp movwf call movfp movwf movfp movwf return PAGE Numerical Integration Simpson's Three-Eighths Rule implemented Y(n) f(X0) 3*f(X1) 3*f(X2) f(X3)]*3*h/8 where step size integral over D_divS ACCbLO,WREG DiffLo ACCbHI,WREG DiffHi DiffKLo,WREG ACCaLO DiffKHi,WREG ACCaHI Xn_1_Lo,WREG ACCbLO, Xn_1_Hi,WREG ACCbHI, Xn_1_Lo,WREG ACCbLO, Xn_1_Hi,WREG ACCbHI,
02C6 02C6 02C7 02C8 02C9 02CA 02CB 02CC 02CD 02CE 02CF 02D0 02D1 02D2 02D3
6A2B 0E27 011A 6A2C 1028 011B 6A27 0F1A 6A28 111B 6A27 0F1A 6A28 111B
02D4 8804 02D5 191B 02D6 191A
02D7 02D8 02D9 02DA 02DB 02DC 02DD 02DE 02DF 02E0 02E1 02E2 02E3 02E4 02E5 02E6 02E7
6A29 051A 6A2A 031B 6A29 051A 6A2A 031B 6A2D 0118 6A2E 0119 E119 6A1A 012F 6A1B 0130
0.5*[f(Xn-2) 3*f(Xn)] 2*f(Xn-1)
result
02E8 0002
1997 Microchip Technology Inc.
DS00544D-page 4-33
AN544
01058 01059 01060 01061 01062 01063 01064 01065 01066 01067 01068 01069 01070 01071 01072 01073 01074 01075 01076 01077 01078 01079 01080 01081 01082 01083 01084 01085 01086 01087 01088 01089 01090 01091 01092 01093 01094 01095 01096 01097 01098 01099 01100 01101 01102 01103 01104 01105 01106 01107 01108 01109 01110 01111 01112 01113 01114 01115 01116 01117 01118 01119 01120 01121 01122 01123 range above equation rewritten Y(n) f(X0) 3*f(X1) 3*f(X2) f(X3)]*IntgK where IntgK 3*h/8 locations (IntgKHi, IntgKHi) This Integration routine used very effectively computation integral component part Loop calculation Motor Control Applications Double precision arithmetic used throught three input values over which integral computed assumed locations (X0Lo,X0Hi), (X1Lo,X1Hi) (X2Lo,X2Hi) (X3Lo,X3Hi) output value located IntgHi IntgLo. overflow checking mechanism implemented. values limited bits, then user need worry about overflows user's responsibility update past values with present values before calling this routine. After computation, present value moved Xn_1 because user want these values intact other computations numerical integration) Also user's responsibility past values (Xn_1 Xn_2) values zero initialization. Integrate movfp X0Lo,WREG addwf X3Lo,W movwf ACCbLO movfp X0Hi,WREG addwfc X3Hi,W movwf ACCbHI Intg f(X0) f(X3) movfp X1Lo,WREG addwf ACCbLO, movfp X1Hi,WREG addwfc ACCbHI, Intg f(X0) f(X3) movfp X1Lo,WREG addwf ACCbLO, movfp X1Hi,WREG addwfc ACCbHI, Intg f(X0) f(X3) +2*X1 movfp X1Lo,WREG addwf ACCbLO, movfp X1Hi,WREG addwfc ACCbHI, Intg f(X0) f(X3) +3*X1 movfp X2Lo,WREG addwf ACCbLO, movfp X2Hi,WREG addwfc ACCbHI, Intg f(X0) f(X3) +3*X1 movfp X2Lo,WREG addwf ACCbLO, movfp X2Hi,WREG addwfc ACCbHI, Intg f(X0) f(X3) +3*X1 2*X2 movfp X2Lo,WREG addwf ACCbLO, movfp X2Hi,WREG addwfc ACCbHI, Intg f(X0) f(X3) +3*X1 3*X2 movfp IntgKLo,WREG movwf ACCaLO
02E9 02E9 02EA 02EB 02EC 02ED 02EE 02EF 02F0 02F1 02F2 02F3 02F4 02F5 02F6 02F7 02F8 02F9 02FA 02FB 02FC 02FD 02FE 02FF 0300 0301 0302 0303 0304 0305 0306
6A31 0E37 011A 6A32 1038 011B 6A33 0F1A 6A34 111B 6A33 0F1A 6A34 111B 6A33 0F1A 6A34 111B 6A35 0F1A 6A36 111B 6A35 0F1A 6A36 111B 6A35 0F1A 6A36 111B
0307 6A39 0308 0118
DS00544D-page 4-34
1997 Microchip Technology Inc.
AN544
0309 6A3A 030A 0119 030B 030C 030D 030E 030F E050 6A1E 013B 6A1F 013C 01124 01125 01126 01127 01128 01129 01130 01131 01132 01133 01134 01135 01136 01137 01138 01139 01140 01141 01142 01143 01144 01145 01146 01147 01148 01149 01150 01151 01152 01153 01154 01155 01156 01157 01158 01159 01160 01161 01162 01163 01164 01165 01166 01167 01168 01169 01170 01171 01172 01173 01174 01175 01176 01177 01178 01179 01180 01181 01182 01183 01184 01185 01186 01187 01188 01189 movfp movwf call movfp movwf movfp movwf return PAGE Random Number Generator This routine generates Pseudo Sequence Random Generator based Linear shift register feedback. sequence generated (Q15 xorwf xorwf xorwf random number location RandHi(high byte) RandLo (low byte) Before calling this routine, make sure initial values RandHi RandLo ZERO good chiose initial random number 0x3045 Random16 rlcf RandHi,W xorwf RandHi,W rlcf WREG, carry xorwf(Q15,14) swapf RandHi, swapf RandLo,W rlncf WREG, xorwf RandHi,W xorwf(Q12,Q3) swapf RandHi, andlw 0x01 rlcf RandLo, xorwf RandLo, rlcf RandHi, return PAGE Gaussian Noise Generator This routine generates Gaussian distributed random points. This routine calls routine "Random16", which generates psuedo random noise sequence. Gaussian noise computed using CENTRAL LIMIT THEOREM. Central Limit Theorem states that average weighted uncorelated samples tends have Gaussian distribution practical purposes, could over sample size Random numbers. Better results could result larger sample size desired. faster results, over samples would also adequate say, applications like Speech synthesis, channel simulations, etc). Gaussian distributed point locations GaussHi GaussLo Before calling this routine, initial seed Random number should ZERO refer notes "Random16" routine D_mpyS make sure either SIGNED UNSIGNED ACCdLO,WREG IntgLo result ACCd ACCc ACCdHI,WREG IntgHi upper bits result IntgKHi,WREG ACCaHI ACCa IntgK (prepare multiplication)
0310 0002
0311 0311 1A19 0312 0C19 0313 1B0A 0314 0315 0316 0317 0318 0319 031A 031B 031C 031D 1D19 1C18 230A 0C19 1D19 B501 1B18 0D18 1B19 0002
1997 Microchip Technology Inc.
DS00544D-page 4-35
AN544
031E 031E 031F 0320 0321 0322 0323 0323 0324 0325 0326 0327 0328 0329 032A 032B 032C 032D 032D 032E 032F 0330 0331 0332 01190 01191 01192 Gauss 2922 01193 clrf count, 8522 01194 count,5 Sample size 291A 01195 clrf GaussLo, 291B 01196 clrf GaussHi, 2920 01197 clrf GaussTmp, 01198 01199 NextGauss E311 01200 call Random16 random value 6A18 01201 movfp RandLo,WREG 0F1A 01202 addwf GaussLo, 6A19 01203 movfp RandHi,WREG 111B 01204 addwfc GaussHi, 290A 01205 clrf WREG, 1120 01206 addwfc GaussTmp, 1722 01207 decfsz count, C323 01208 goto NextGauss random numbers 01209 B005 01210 movlw 01211 GaussDiv16 1920 01212 rrcf GaussTmp, 191B 01213 rrcf GaussHi, 191A 01214 rrcf GaussLo, weghted average 170A 01215 decfsz WREG, divide C32D 01216 goto GaussDiv16 01217 0002 01218 return 01219 01220 01221 arith.asm XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXX-
0000 0040 0080 00C0 0100 0140 0180 01C0 0200 0240 0280 02C0 0300
other memory blocks unused. Program Memory Words Used:
Errors Warnings Messages
reported, reported,
suppressed suppressed
DS00544D-page 4-36
1997 Microchip Technology Inc.
AN544
Please check Microchip latest version source code. Microchip's Worldwide Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership required).
APPENDIX
ARITHMETIC ROUTINES LISTING FILE BCD.ASM
BCD.ASM 1-16-1997 15:11:16 PAGE
MPASM 01.40 Released
OBJECT CODE VALUE 00001 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00001 00002 00264 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029 00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 00040 00041 00042 00043 00044 00045 00046 00047 00048 00049 00050 00051
LINE SOURCE TEXT
TITLE
"BCD Arithmetic Routines 1.0"
Arithmetic Routines Program: BCD.ASM Revision Date: 1-13-97 Compatibility with MPASMWIN 1.40 LIST 17C42, columns=120, WRAP,
include "P17C42.INC" LIST P17C42.INC Standard Header File, Version 1.03 LIST
Microchip Technology, Inc.
#define TRUE #define FALSE _INC _NO_INC _LOW _HIGH
00000001 00000000 00000000 00000001
CBLOCK
00000020 00000022 00000025 00000026
0x20 Lbyte, Hbyte count Num1, Num2
must maintain sequence
ENDC Htemp Ltemp PAGE 0x0000 Arithmetic Test Program main setf Hbyte, setf Lbyte, binary 0xffff call B2_BCD_Looped after conversion Decimal 06,55,35 setf Hbyte, Num1 Num1 Num2
00000026 00000026 00000027
0000
0000 0000 2B21 0001 2B20 0002 E01F 0003 2B21
1997 Microchip Technology Inc.
DS00544D-page 4-37
AN544
0004 2B20 0005 E03F 0006 0007 0008 0009 000A 000B B006 0124 B055 0123 B035 0122 00052 00053 00054 00055 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 00095 00096 00097 00098 00099 00100 00101 00102 00103 00104 00105 00106 00107 00108 00109 00110 00111 00112 00113 00114 00115 00116 00117 setf call movlw movwf movlw movwf movlw movwf call movlw movwf movlw movwf call movlw call self 0x63 BinBCD BCDAdd after addition, Num2 Num1 99+99 198) setf Wreg after conversion, decimal. 0x99 Num1 0x99 Num2 BCDtoB after conversion Hbyte 0xff Lbyte 0xff 0x06 0x55 0x35 Lbyte, B2_BCD_Straight same above, straight line code
setf R0R1R2 65535
000C E082 000D 000E 000F 0010 B099 0126 B099 0127
setf Num1 Num2 0x99 (max BCD)
0011 E093
0012 B063 0013 E015
0014 C014
goto
self
0015 0015 0016 0016 0017 0018 0019 001A 001B 001B 001C 001D 001E
2926 B1F0 9004 C01B 1526 C016 B110 1D26 0926 0002
PAGE Binary Conversion Routine bit) This routine converts binary number digit number location BCD( compacted Code) least significant digit returned location most significant digit returned location MSD. Performance Program Memory Clock Cycles (worst case when Decimal number BinBCD clrf BCD, again addlw btfss ALUSTA,C goto swapBCD incf BCD, goto again swapBCD addlw swapf BCD, iorwf BCD, return PAGE Binary Conversion Routine Bit) (LOOPED Version) This routine converts binary Number Digit Number. binary number input locations Hbyte Lbyte with high byte Hbyte. digit number returned with
DS00544D-page 4-38
1997 Microchip Technology Inc.
AN544
00118 00119 00120 00121 00122 00123 00124 00125 00126 00127 00128 00129 00130 00131 00132 00133 00134 00135 00136 00137 00138 00139 00140 00141 00142 00143 00144 00145 00146 00147 00148 00149 00150 00151 00152 00153 00154 00155 00156 00157 00158 00159 00160 00161 00162 00163 00164 00165 00166 00167 00168 00169 00170 00171 00172 00173 00174 00175 00176 00177 00178 00179 00180 00181 00182 00183 containing right most nibble. Performance Program Memory Clock Cycles B2_BCD_Looped ALUSTA,FS0 ALUSTA,FS1 FSR0 auto increment ALUSTA,C clrf count, count,4 count clrf clrf clrf loop16a rlcf Lbyte, rlcf Hbyte, rlcf rlcf rlcf dcfsnz count, return adjDEC movlw load indirect address movwf FSR0 call adjBCD incf FSR0, call adjBCD incf FSR0, call adjBCD goto loop16a adjBCD movfp INDF0,WREG addlw 0x03 btfsc WREG,3 test result movwf INDF0 movfp INDF0,WREG addlw 0x30 btfsc WREG,7 test result movwf INDF0 save return Binary Conversion Routine Bit) (Partial Straight Line Version) This routine converts binary Number Digit Number. binary number input locations Hbyte Lbyte with high byte Hbyte. digit number returned with containing right most nibble. Performance Program Memory Clock Cycles
001F 001F 8404 0020 8504 0021 0022 0023 0024 0025 0026 0027 0027 0028 0029 002A 002B 002C 002D 002E 002E 002F 0030 8804 2925 8425 2924 2923 2922 1B20 1B21 1B22 1B23 1B24 2725 0002 B022 0101 E036
0031 1501 0032 E036 0033 1501 0034 E036 0035 C027 0036 0036 0037 0038 0039 003A 003B 003C 003D 003E
6A00 B103 9B0A 0100 6A00 B130 9F0A 0100 0002
1997 Microchip Technology Inc.
DS00544D-page 4-39
AN544
00184 00185 00186 00187 00188 00189 00190 00191 00192 00193 00194 00195 00196 00197 00198 00199 00200 00201 00202 00203 00204 00205 00206 00207 00208 00209 00210 00211 00212 00213 00214 00215 00216 00217 00218 00219 00220 00221 00222 00223 00224 00225 00226 00227 00228 00229 00230 00231 00232 00233 00234 00235 00236 00237 00238 00239 00240 00241 00242 00243 00244 00245 00246 00247 00248 00249 B2_BCD_Straight ALUSTA,FS0 ALUSTA,FS1 FSR0 auto increment ALUSTA,C clrf count, count,4 count clrf clrf clrf loop16b rlcf Lbyte, rlcf Hbyte, rlcf rlcf rlcf dcfsnz count, return DONE movlw load indirect address movwf FSR0 adjustBCD movfp INDF0,WREG addlw 0x03 btfsc WREG,3 test result movwf INDF0 movfp INDF0,WREG addlw 0x30 btfsc WREG,7 test result movwf INDF0 save incf FSR0, adjustBCD movfp INDF0,WREG addlw 0x03 btfsc WREG,3 test result movwf INDF0 movfp INDF0,WREG addlw 0x30 btfsc WREG,7 test result movwf INDF0 save incf FSR0, adjustBCD movfp INDF0,WREG addlw 0x03 btfsc WREG,3 test result movwf INDF0 movfp INDF0,WREG addlw 0x30 btfsc WREG,7 test result movwf INDF0 save goto loop16b PAGE Binary Conversion This routine converts digit number binary number. input digit numbers asumed locations with containing right most nibble.
003F 003F 8404 0040 8504 0041 0042 0043 0044 0045 0046 0047 0047 0048 0049 004A 004B 004C 004D 004E 004F 0050 0051 0052 0053 0054 0055 0056 0057 8804 2925 8425 2924 2923 2922 1B20 1B21 1B22 1B23 1B24 2725 0002 B022 0101 6A00 B103 9B0A 0100 6A00 B130 9F0A 0100
0058 1501 0059 005A 005B 005C 005D 005E 005F 0060 6A00 B103 9B0A 0100 6A00 B130 9F0A 0100
0061 1501 0062 0063 0064 0065 0066 0067 0068 0069 6A00 B103 9B0A 0100 6A00 B130 9F0A 0100
006A C047
DS00544D-page 4-40
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AN544
00250 00251 00252 00253 00254 00255 00256 00257 00258 00259 00260 00261 00262 00263 00264 00265 00266 00267 00268 00269 00270 00271 00272 00273 00274 00275 00276 00277 00278 00279 00280 00281 00282 00283 00284 00285 00286 00287 00288 00289 00290 00291 00292 00293 00294 00295 00296 00297 00298 00299 00300 00301 00302 00303 00304 00305 00306 00307 00308 00309 00310 00311 00312 00313 00314 00315 binary number output registers Hbyte Lbyte high byte byte repectively method used conversion input number abcde digit number (R0,R1,R2) abcde 10[10[10[10a+b]+c]+d]+e Performance Program Memory Clock Cycles mpy10b andlw 0x0f addwf Lbyte, btfsc ALUSTA,C incf Hbyte, mpy10a ALUSTA,C multiply rlcf Lbyte,W movwf Ltemp rlcf Hbyte,W (Htemp,Ltemp) movwf Htemp ALUSTA,C multiply rlcf Lbyte, rlcf Hbyte, ALUSTA,C multiply rlcf Lbyte, rlcf Hbyte, ALUSTA,C multiply rlcf Lbyte, rlcf Hbyte, (Hbyte,Lbyte) movfp Ltemp,WREG addwf Lbyte, movfp Htemp,WREG addwfc Hbyte, return (Hbyte,Lbyte) 10*N BCDtoB clrf Hbyte, movfp R0,WREG andlw 0x0f movwf Lbyte call mpy10a result 10a+b swapf R1,W call mpy10b result 10[10a+b] movfp R1,WREG call mpy10b result 10[10[10a+b]+c] swapf R2,W call mpy10b result 10[10[10[10a+b]+c]+d] movfp R2,WREG andlw 0x0f addwf Lbyte, btfsc ALUSTA,C incf Hbyte, result 10[10[10[10a+b]+c]+d]+e return binary conversion done
006B 006B 006C 006D 006E 006F 006F 0070 0071 0072 0073 0074 0075 0076 0077 0078 0079 007A 007B 007C 007D 007E 007F 0080 0081
B50F 0F20 9804 1521 8804 1A20 0127 1A21 0126 8804 1B20 1B21 8804 1B20 1B21 8804 1B20 1B21 6A27 0F20 6A26 1121 0002
0082 0082 0083 0084 0085 0086
2921 6A24 B50F 0120 E06F
0087 1C23 0088 E06B 0089 6A23 008A E06B 008B 1C22 008C E06B 008D 008E 008F 0090 0091 0092 6A22 B50F 0F20 9804 1521 0002
1997 Microchip Technology Inc.
DS00544D-page 4-41
AN544
00316 PAGE 00317 00318 00319 Unsigned Addition 00320 00321 This routine performs Digit Unsigned Addition 00322 assumed that numbers added 00323 locations Num1 Num2. result Num1+Num2 00324 stored location Num2 overflow carry returned 00325 location Num1 00326 00327 Performance 00328 Program Memory 00329 Clock Cycles 00330 00331 00332 0093 00333 BCDAdd 0093 6A26 00334 movfp Num1,WREG 0094 0E27 00335 addwf Num2,W perform binary addition 0095 2F27 00336 Num2, adjust addition 0096 2926 00337 clrf Num1, 0097 1B26 00338 rlcf Num1, Num1 carry 0098 0002 00339 return 00340 00341 00342 00343 Arithmetic Routines MEMORY USAGE (`X' Used, Unused) 0000 XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX 0040 XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX 0080 XXXXXXXXXXXXXXXX XXXXXXXXX- -All other memory blocks unused. Program Memory Words Used:
Errors Warnings Messages
reported, reported,
suppressed suppressed
DS00544D-page 4-42
1997 Microchip Technology Inc.
AN544
Please check Microchip latest version source code. Microchip's Worldwide Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership required).
APPENDIX
FXP_DIV.ASM
FLOAT.ASM 1-16-1997 15:11:46 PAGE
MPASM 01.40 Released
OBJECT CODE VALUE 00001 00002 00003 00004 00005 00006 00001 00002 00264 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029 00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 00040 00041 00042 00043 00044 00045 00046 00047 00048 00049 00050 00051
LINE SOURCE TEXT
TITLE LIST
"Binary Floating Arithmetic Routines PIC17C42 1.0" 17C42, columns=120, WRAP,
include "p17c42.inc" LIST P17C42.INC Standard Header File, Version 1.03 LIST #define TRUE #define FALSE #define #define
Microchip Technology, Inc.
00000020 00000023 00000026 00000028 0000002A
00000001
Binary Floating Point Addition, Subtraction Multiplication Routines Mantissa bits Exponent bits exponent binary decimal) number ABCD EXP(X) 0xABCD (2**X) Before calling following floating point routines, required Indirect Register FSR0 No-Autoincrement i.e. bits ALUSTA Program: FLOAT.ASM Revision Date: 1-13-97 Compatibility with MPASMWIN 1.40 CBLOCK 0x20 ACCaLO, ACCaHI, EXPa ACCbLO, ACCbHI, EXPb ACCcLO, ACCcHI ACCdLO, ACCdHI temp, sign ENDC Mode16 TRUE Change this FALSE product PAGE 0x0000 Floating Point Routines Test Program main
0000
0000
1997 Microchip Technology Inc.
DS00544D-page 4-43
AN544
00052 00053 ALUSTA,FS0 FSR0 autoincrement 00054 ALUSTA,FS1 00055 0002 E009 00056 call loadAB result adding 0003 E019 00057 call F_add Here Accb 403F, EXPb 00058 0004 E009 00059 call loadAB result subtracting 0005 E016 00060 call F_sub Here Accb 7F7F, EXPb 00061 0006 E009 00062 call loadAB result multiplying ACCb(EXPb) ACCa(EXPa)->ACCb(EXPb) 0007 E03B 00063 call F_mpy Here ACCb FF7E, EXPb 00064 0008 C008 00065 self goto self 00066 00067 Load constant values (ACCa, EXPa) (ACCb, EXPb) testing 00068 0009 00069 loadAB 0009 B001 00070 movlw 0x01 000A 0121 00071 movwf ACCaHI 000B B0FF 00072 movlw 0xff loads ACCa 01FF EXP(4) 000C 0120 00073 movwf ACCaLO 000D B004 00074 movlw 0x04 000E 0122 00075 movwf EXPa 00076 000F B07F 00077 movlw 0x7f 0010 0124 00078 movwf ACCbHI 0011 B0FF 00079 movlw 0xff loads ACCb 7fff EXP(6) 0012 0123 00080 movwf ACCbLO 0013 B006 00081 movlw 0x06 0014 0125 00082 movwf EXPb 0015 0002 00083 return 00084 00085 PAGE 00086 00087 Floating Point Subtraction ACCb ACCa ACCb 00088 00089 Subtraction ACCb(16 bits) ACCa(16 bits) ACCb(16 bits) 00090 Load operand location ACCaLO ACCaHI bits 00091 exponent EXPa 00092 Load operand location ACCbLO ACCbHI bits 00093 exponent EXPb 00094 CALL F_sub 00095 result location ACCbLO ACCbHI bits with 00096 exponent EXPb. 00097 00098 00099 0016 00100 F_sub 0016 B020 00101 movlw ACCaLO 0017 0101 00102 movwf FSR0 0018 E075 00103 call negate first negate ACCa; Then addwf 00104 00105 00106 Floating Point Addition ACCb ACCa ACCb 00107 00108 Addition ACCb(16 bits) ACCa(16 bits) ACCb(16 bits) 00109 Load operand location ACCaLO ACCaHI bits 00110 exponent EXPa. 00111 Load operand location ACCbLO ACCbHI bits 00112 exponent EXPb. 00113 CALL F_add 00114 result location ACCbLO ACCbHI bits with 0000 8404 0001 8504
with with
with with
DS00544D-page 4-44
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00115 00116 00117 00118 00119 00120 00121 00122 00123 00124 00125 00126 00127 00128 00129 00130 00131 00132 00133 00134 00135 00136 00137 00138 00139 00140 00141 00142 00143 00144 00145 00146 00147 00148 00149 00150 00151 00152 00153 00154 00155 00156 00157 00158 00159 00160 00161 00162 00163 00164 00165 00166 00167 00168 00169 00170 00171 00172 00173 00174 00175 00176 00177 00178 00179 00180 exponent EXPb F_add movfp EXPa,WREG cpfseq EXPb goto Lbl1 goto noAddNorm exponents equal Lbl1 cpfslt EXPb call F_swap then swap A<->B movfp EXPa,WREG subwf EXPb, scloop call addNorm incfsz EXPb, goto scloop movfp EXPa,WREG movwf EXPb noAddNorm movfp ACCaHI,WREG iorwf ACCbHI,W movwf sign save sign states) call D_add compute double precision integer addwf btfss sign,MSB btfss ACCbHI,MSB return incf EXPb, ALUSTA,C goto shftR addNorm ALUSTA,C btfsc ACCbHI,MSB ALUSTA,C carry shftR rrcf ACCbHI, rrcf ACCbLO, return PAGE Double Precision Addition D_add movfp ACCaLO,WREG addwf ACCbLO, addwf movfp ACCaHI,WREG addwfc ACCbHI, addwf with carry return PAGE Binary Floating Point Multiplication Multiplication ACCb(16 bits)EXP(b) ACCa(16 bits)EXPa ACCb(16 bits)EXPb where, EXP(x) represents exponent. Load operand location ACCaLO ACCaHI bits with exponent location EXPa Load operand location ACCbLO ACCbHI bits with exponent location EXPb CALL F_mpy result overwrites ACCb(ACCbLO ACCbHI). exponent stored EXPb results normalized.
0019 0019 001A 001B 001C 001D 001D 001E 001F 0020 0021 0021 0022 0023 0024 0025 0026 0026 0027 0028 0029 002A 002B 002C 002D 002E 002F 0030 0030 0031 0032 0033 0033 0034 0035
6A22 3125 C01D C026 3025 E09E 6A22 0525 E030 1F25 C021 6A22 0125 6A21 0824 012B E036 972B 9724 0002 1525 8804 C033
8804 9F24 8004 1924 1923 0002
0036 0036 0037 0038 0039 003A
6A20 0F23 6A21 1124 0002
1997 Microchip Technology Inc.
DS00544D-page 4-45
AN544
00181 00182 00183 00184 00185 00186 00187 00188 00189 00190 00191 00192 00193 00194 00195 00196 00197 00198 00199 00200 00201 00202 00203 00204 00205 00206 00207 00208 00209 00210 00211 00212 00213 00214 00215 00216 00217 00218 00219 00220 00221 00222 00223 00224 00225 00226 00227 00228 00229 00230 00231 00232 00233 00234 00235 00236 00237 00238 00239 00240 00241 00242 00243 00244 00245 00246 NOTE needs product( exponent assemble program after changing line Mode16 TRUE" Mode16 FALSE this option chosen, then result returned ACCbHI, ACCbLO, ACCcHI, ACCcLO exponent EXPb. This method with Mode16 FALSE Recommended. mantissa desired, MODE16 FALSE F_mpy call S_SIGN call setup mloop ALUSTA,C rrcf ACCdHI, rotate right rrcf ACCdLO, btfsc ALUSTA,C call D_add rrcf ACCbHI, rrcf ACCbLO, rrcf ACCcHI, rrcf ACCcLO, decfsz temp, loop until bits checked goto mloop movfp EXPa,WREG addwf EXPb, Mode16 tstfsz ACCbHI goto finup ACCbHI tstfsz ACCbLO goto Shft08 ACCbLO ACCbHI movfp ACCcHI,WREG movwf ACCbHI ACCb then move ACCc ACCb movfp ACCcLO,WREG movwf ACCbLO movlw addwf EXPb, goto finup Shft08 movfp ACCbLO,WREG movwf ACCbHI movfp ACCcHI,WREG movwf ACCbLO movlw addwf EXPb, #endif matching endif Mode16 finup btfss sign,MSB goto F_norm movlw ACCcLO movwf FSR0 call negate movlw ACCbLO movwf FSR0 call negate goto F_norm normalize floating point
003B 003B 003C 003D 003D 003E 003F 0040 0041 0042 0043 0044 0045 0046 0047
E07D E064 8804 1929 1928 9804 E036 1924 1923 1927 1926 172A C03D
0048 6A22 0049 0F25
004A 004B 004C 004D 004E 004F 0050 0051 0052 0053 0054 0055 0055 0056 0057 0058 0059 005A
3324 C05B 3323 C055 6A27 0124 6A26 0123 B016 0F25 C05B
6A23 0124 6A27 0123 B008 0F25
005B 005B 972B 005C C08B 005D 005E 005F 0060 0061 0062 0063 B026 0101 E075 B023 0101 E075 C08B
DS00544D-page 4-46
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AN544
0064 0064 0065 0066 0067 0068 0069 006A 006B 006C 00247 00248 00249 00250 00251 00252 00253 00254 00255 00256 00257 00258 00259 00260 00261 00262 00263 00264 00265 00266 00267 00268 00269 00270 00271 00272 00273 00274 00275 00276 00277 00278 00279 00280 00281 00282 00283 00284 00285 00286 00287 00288 00289 00290 00291 00292 00293 00294 00295 00296 00297 00298 00299 00300 00301 00302 00303 00304 00305 00306 00307 00308 00309 00310 00311 00312 setup clrf temp, temp,4 temp movfp ACCbHI,WREG move ACCb ACCd movwf ACCdHI movfp ACCbLO,WREG movwf ACCdLO clrf ACCbHI, clrf ACCbLO, clear ACCb ACCbLO ACCbHI return PAGE Double Precision Negate Routines negateAlt movfp INDF0,WREG ALUSTA,FS1 negw INDF0, ALUSTA,FS1 movfp INDF0,WREG clrf INDF0, subwfb INDF0, return negate comf INDF0, ALUSTA,FS1 incf INDF0, ALUSTA,FS1 btfsc ALUSTA,Z decf INDF0, comf INDF0, return PAGE Check Sign Number, negate SIGN flag S_SIGN movfp ACCaHI,WREG xorwf ACCbHI,W movwf sign btfss ACCbHI,MSB negate ACCb goto chek_A movlw ACCbLO movwf FSR0 call negate chek_A btfss ACCaHI,MSB negate ACCa return movlw ACCaLO movwf FSR0 call negate return PAGE Normalize Routine Normalizes ACCb floating point calculations. Call this routine often possible minimize loss precission. This routine normalizes ACCb that
292A 842A 6A24 0129 6A23 0128 2924 2923 0002
006D 006D 006E 006F 0070 0071 0072 0073 0074 0075 0075 0076 0077 0078 0079 007A 007B 007C
6A00 8D04 2D00 8504 6A00 2900 0300 0002
1300 8D04 1500 8504 9A04 0700 1300 0002
007D 007D 007E 007F 0080 0081
6A21 0C24 012B 9724 C085
0082 B023 0083 0101 0084 E075 0085 0085 0086 0087 0088 0089 008A
9721 0002 B020 0101 E075 0002
1997 Microchip Technology Inc.
DS00544D-page 4-47
AN544
00313 00314 00315 00316 00317 00318 00319 00320 00321 00322 00323 00324 00325 00326 00327 00328 00329 00330 00331 00332 00333 00334 00335 00336 00337 00338 00339 00340 00341 00342 00343 00344 00345 00346 00347 00348 00349 00350 00351 00352 00353 00354 00355 00356 00357 00358 00359 00360 00361 00362 00363 00364 00365 00366 00367 00368 00369 00370 00371 00372 00373 00374 00375 00376 00377 00378 mantissa maximized exponent minimized. F_norm normalize ACCb tstfsz ACCbHI goto C_norm tstfsz ACCbLO goto C_norm return C_norm btfsc ACCbHI,MSB-1 return call shftSL decf EXPb, goto C_norm shftSL ALUSTA,C Mode16 rlcf ACCcLO, rlcf ACCcHI, #endif rlcf ACCbLO, rlcf ACCbHI, ACCbHI,MSB btfsc ALUSTA,C ACCbHI,MSB return Swap ACCa ACCb (ACCa,EXPa) (ACCb,EXPb) F_swap movfp ACCaHI,WREG movwf temp movfp ACCbHI,WREG ACCaHI ACCbHI movwf ACCaHI movfp temp,WREG movwf ACCbHI movfp ACCaLO,WREG movwf temp movfp ACCbLO,WREG ACCaLO ACCbLO movwf ACCaLO movfp temp,WREG movwf ACCbLO movfp EXPb,WREG movwf temp movfp EXPa,WREG EXPa EXPb movwf EXPb movfp temp,WREG movwf EXPa return Normalizes Floating Point Number number assumed (LowByte, HighByte, Exp) consecutive locations. Before calling this routine, address LowByte should loaded into FSR0 (indirect register ptr)
008B 008B 008C 008D 008E 008F 0090 0090 0091 0092 0093 0094
3324 C090 3323 C090 0002
9E24 0002 E095 0725 C090
0095 0095 8804
0096 1B26 0097 1B27
0098 0099 009A 009B 009C 009D
1B23 1B24 8F24 9804 8724 0002
009E 009E 009F 00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AA 00AB 00AC 00AD 00AE 00AF 00B0
6A21 012A 6A24 0121 6A2A 0124 6A20 012A 6A23 0120 6A2A 0123 6A25 012A 6A22 0125 6A2A 0122 0002
DS00544D-page 4-48
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AN544
00379 Normalize 00380 incf 00381 tstfsz 00382 goto 00383 decf 00384 tstfsz 00385 goto 00386 return 00387 NextNorm2 1501 00388 incf 00389 NextNorm1 9E00 00390 btfsc 0002 00391 return E0C0 00392 call 1501 00393 incf 0700 00394 decf 0701 00395 decf C0B9 00396 goto 00397 00C0 00398 shiftNorm 00C0 8804 00399 00C1 1501 00400 incf 00C2 1B00 00401 rlcf 00C3 1501 00402 incf 00C4 1B00 00403 rlcf 00C5 0701 00404 decf 00C6 0701 00405 decf 00C7 0701 00406 decf 00C8 1B00 00407 rlcf 00C9 1501 00408 incf 00CA 1B00 00409 rlcf 00CB 8F00 00410 00CC 9804 00411 btfsc 00CD 8700 00412 00CE 0002 00413 return 00414 00415 00416 MEMORY USAGE (`X' Used, 1501 3300 C0B9 0701 3300 C0B8 0002 0000 0040 0080 00C0 XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXX00B1 00B1 00B2 00B3 00B4 00B5 00B6 00B7 00B8 00B8 00B9 00B9 00BA 00BB 00BC 00BD 00BE 00BF FSR0, INDF0 NextNorm1 FSR0, INDF0 NextNorm2
FSR0, INDF0,MSB-1 shiftNorm FSR0, INDF0, FSR0, NextNorm1
ALUSTA,C FSR0, INDF0, FSR0, INDF0, FSR0, FSR0, FSR0, INDF0, FSR0, INDF0, INDF0,MSB ALUSTA,C INDF0,MSB
Unused) XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX -XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
other memory blocks unused. Program Memory Words Used:
Errors Warnings Messages
reported, reported,
suppressed suppressed
1997 Microchip Technology Inc.
DS00544D-page 4-49
Note following details code protection feature PICmicro® MCUs. PICmicro family meets specifications contained Microchip Data Sheet. Microchip believes that family PICmicro microcontrollers most secure products kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using PICmicro microcontroller manner outside operating specifications contained data sheet. person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable". Code protection constantly evolving. Microchip committed continuously improving code protection features product.
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2002 Microchip Technology Inc.
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Drive, Suite Westford, 01886 Tel: 978-692-3848 Fax: 978-692-3821
China Chengdu
Microchip Technology Consulting (Shanghai) Co., Ltd., Chengdu Liaison Office 2401, 24th Floor, Ming Xing Financial Tower TIDU Street Chengdu 610016, China Tel: 86-28-6766200 Fax: 86-28-6766599
Taiwan
Microchip Technology Taiwan 11F-3, Tung North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Chicago
Pierce Road, Suite Itasca, 60143 Tel: 630-285-0071 Fax: 630-285-0075
Dallas
4570 Westgrove Drive, Suite Addison, 75001 Tel: 972-818-7423 Fax: 972-818-2924
China Fuzhou
Microchip Technology Consulting (Shanghai) Co., Ltd., Fuzhou Liaison Office Unit 28F, World Trade Plaza Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521
EUROPE
Denmark
Microchip Technology Nordic Regus Business Centre Lautrup Ballerup DK-2750 Denmark Tel: 4420 9895 Fax: 4420 9910
Detroit
Tri-Atria Office Building 32255 Northwestern Highway, Suite Farmington Hills, 48334 Tel: 248-538-2250 Fax: 248-538-2260
China Shanghai
Microchip Technology Consulting (Shanghai) Co., Ltd. Room 701, Bldg. East International Plaza Xian Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Kokomo
2767 Albright Road Kokomo, Indiana 46902 Tel: 765-864-8360 Fax: 765-864-8387
France
Microchip Technology SARL Parc d'Activite Moulin Massy Saule Trapu Batiment Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Angeles
18201 Karman, Suite 1090 Irvine, 92612 Tel: 949-263-1888 Fax: 949-263-1338
China Shenzhen
Microchip Technology Consulting (Shanghai) Co., Ltd., Shenzhen Liaison Office 1315, 13/F, Shenzhen Kerry Centre, Renminnan Shenzhen 518001, China Tel: 86-755-2350361 Fax: 86-755-2366086
York
Motor Parkway, Suite Hauppauge, 11788 Tel: 631-273-5305 Fax: 631-273-5335
Germany
Microchip Technology GmbH Gustav-Heinemann Ring D-81739 Munich, Germany Tel: 49-89-627-144 Fax: 49-89-627-144-44
Jose
Microchip Technology Inc. 2107 North First Street, Suite Jose, 95131 Tel: 408-436-7950 Fax: 408-436-7955
Hong Kong
Microchip Technology Hongkong Ltd. Unit 901-6, Tower Metroplaza Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431
Italy
Microchip Technology Centro Direzionale Colleoni Palazzo Taurus Colleoni 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883
Toronto
6285 Northam Drive, Suite Mississauga, Ontario 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509
India
Microchip Technology Inc. India Liaison Office Divyasree Chambers Floor, Wing (A3/A4) O'Shaugnessey Road Bangalore, 025, India Tel: 91-80-2290061 Fax: 91-80-2290062
United Kingdom
Arizona Microchip Technology Ltd. Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 Tel: 5869 Fax: 44-118 921-5820
03/01/02
2002 Microchip Technology Inc.
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