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VT8371
REVISION HISTORY
Document Release Date 4/12/99 6/14/99 Revision Initial internal release Updated feature bullets, overview descriptions Added ballout engineering document revision Added registers from 694X data sheet 0.61 (bank ending addresses fixed) Updated package mechanical Fixed formatting problems electrical specs page Updated feature bullets, overview, block diagram Updated pinouts (changed interface some DRAM data pins) Updated package mechanical BGA512 Updated register specs reflect register (rev copy 694X) Fixed pinout errors center VCC/GND changed areas Fixed strap options Fixed device registers Rx58-59, 61-63, Updated mechanical specs Fixed typographical error feature bullets regarding package count Fixed formatting errors page footer revision numbers document date Updated pinouts engineering ballout 0.6: swapped PWROK WSC# Updated pinouts engineering ballout 0.7: swapped D37# Changed Device Device Device values Fixed Device Rx10[27-20] typographical error, Rx88[2] function, RxA0 RxA4 default values (typographical errors) Fixed Device Rx54[0] definition Device Device Added Device RxC0-C7 Power Management registers Fixed GCKRUN# direction Added strap register cross references MAA/MAB descriptions Device Fixed Rx3-2 (Device ID), 52[3], 68[0], 76[3-0], 7B[1], F0-F7 Fixed RxB4[3-2] strapping RxB5[7,3] polarity; added RxB4-5 defaults Device Fixed Rx3-2 (Device ID), 1F-1E, Rx40[3], 42[4, 44[4-1], 82[5], 83[2-1] Changed "K7" Athlon" reworded document title Changed feature bullets DRAM controller section Removed "NDA Required" disclaimer (product announced) Fixed minor typo pinout table (pin lists descriptions were correct) Added Device Rx55[1], moved Device registers RxB4-B6 B3-B5 Removed "Socket-462" from description (chip optimized Slot-A) Updated Logo "Delivering Value" format Fixed typos DRAM controller feature bullets Device RxB2[0] Initials
0.21
6/17/99 7/2/99
0.41
7/13/99
7/20/99
0.51
7/22/99 8/26/99
11/1/99
1.01 1.02
1/7/00 1/17/00
Preliminary Revision 1.02, January 2000
Revision History
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VT8371
TABLE CONTENTS
REVISION HISTORY.I TABLE CONTENTS. LIST FIGURES.III LIST TABLES KX133 ATHLONNORTH BRIDGE. OVERVIEW PINOUTS DESCRIPTIONS REGISTERS REGISTER OVERVIEW MISCELLANEOUS I/O. CONFIGURATION SPACE REGISTER DESCRIPTIONS. Device Header Registers Host Bridge. Device Configuration Registers Host Bridge
Host Control DRAM Control Control. GART Graphics Aperture Control Control
Device Header Registers PCI-to-PCI Bridge Device Configuration Registers PCI-to-PCI Bridge.
Control
ELECTRICAL SPECIFICATIONS. ABSOLUTE MAXIMUM RATINGS CHARACTERISTICS. TIMING SPECIFICATIONS MECHANICAL SPECIFICATIONS
Preliminary Revision 1.02, January 2000
-ii-
Table Contents
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VT8371
LIST FIGURES
FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE KX133 SYSTEM BLOCK DIAGRAM USING VT82C686A SOUTH BRIDGE VT8371 BALL DIAGRAM (TOP VIEW) VT8371 LIST (NUMERICAL ORDER) VT8371 LIST (ALPHABETICAL ORDER) SDRAM CLOCK CONNECTIONS GRAPHICS APERTURE ADDRESS TRANSLATION MECHANICAL SPECIFICATIONS 516-PIN BALL GRID ARRAY PACKAGE
Preliminary Revision 1.02, January 2000
-iii-
List Figures
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VT8371
LIST TABLES
TABLE TABLE TABLE TABLE TABLE TABLE VT8371 DESCRIPTIONS VT8371 REGISTERS SYSTEM MEMORY MAP. MEMORY ADDRESS MAPPING TABLE VGA/MDA MEMORY/IO REDIRECTION. TIMING CONDITIONS.
Preliminary Revision 1.02, January 2000
-iv-
List Tables
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VT8371
VT8371 KX133 ATHLONNORTH BRIDGE
Single-Chip North Bridge Slot-A Based Athlon CPUs with Front Side Desktop Systems with plus Advanced Memory Controller supporting PC133 PC100 SDRAM
High Performance High Integration Athlon PC133 Chipset with Advanced System Power Management KX133 Chipset: VT8371 system controller VT82C686A bridge Single chip Athlon system controller with 64-bit Slot-A Athlon CPU, 64-bit system memory, 32-bit 32-bit PCI-to-ISA bridge chip includes UltraDMA-33/66 EIDE, Ports, Integrated Super-I/O, AC97 MC97 link (for
Audio Modem support), Hardware Monitoring, Power Management, Keyboard PS2-Mouse Interfaces plus CMOS chip Supports separately powered 3.3V tolerant) interface system memory, AGP, Modular power management clock control advanced system power management interfaces
High Performance Athlon Interface Supports Slot-A (AMD Athlon) processors HSTL-like 1.5V high-speed transceiver logic signal levels Support independent address, data, snoop interfaces (Double Data Rate) transfer Athlon address data buses Built-in (Phase Lock Loop) circuitry optimal skew control within between clocking regions Four-entry command queue accommodate maximum throughput Four-entry probe queue stores probes from system processor Twenty four-entry processor system data control queue store system data control commands separate Supports (Write Combining) cycles Sleep mode support System management interrupt, memory remap STPCLK mechanism
read write buffers data movement processor interface
Preliminary Revision 1.02, January 2000
Features
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VT8371
Full Featured Accelerated Graphics Port (AGP) Controller Synchronous pseudo-synchronous with host with optimal skew control
Mode synchronous v2.0 compliant Supports SideBand Addressing (SBA) mode (non-multiplexed address data) Supports modes signaling Pipelined split-transaction long-burst transfers 1GB/sec Thirty-two level read request queue Four level posted-write request queue Thirty-two level (quadwords) read data FIFO (256 bytes) Sixteen level (quadwords) write data FIFO (128 bytes) Intelligent request reordering maximum utilization Supports Flush/Fence commands Graphics Address Relocation Table (GART)
Windows OSR-2 integrated Windows Windows 2000 miniport driver support Concurrent Controller buses synchronous pseudo-synchronous host operation primary operation PCI-to-PCI bridge configuration 66MHz Supports five masters Peer concurrency Concurrent multiple master transactions; i.e., allow masters from both buses active same time Zero wait state master slave burst transfer rate system memory data streaming 132Mbyte/sec lines double-words) posted write buffers Byte merging write buffers reduce number cycles create further bursting possibilities Enhanced command optimization (MRL, MRM, MWI, etc.) Thirty-two levels (double-words) post write buffers from masters DRAM
(two cache lines double-words bus, cache lines double-words Athlon processor interface) Sixteen levels (double-words) prefetch buffers from DRAM access masters Delay transaction from master accessing DRAM Read caching master reading DRAM Transaction timer fair arbitration between masters (granularity clocks) Symmetric arbitration between Host/PCI optimized system performance Complete steerable interrupts PCI-2.2 compliant, 3.3V interface with tolerant inputs
level structure Sixteen entry fully associative page table replacement scheme
Preliminary Revision 1.02, January 2000
Features
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VT8371
Advanced High-Performance DRAM Controller Supports PC133 PC100 SDRAM Virtual Channel Memory (VCM) SDRAM DIMMs Concurrent CPU, AGP, access Different DRAM types used mixed combinations Different DRAM timing each bank Dynamic Clock Enable (CKE) control SDRAM power reduction high speed systems Mixed 32MxN DRAMs Support memory space (256Mb DRAM technology) Flexible column addresses 64-bit data width 3.3V DRAM interface Programmable drive capability command, signals Dual copies signals improved drive Optional bank-by-bank (single-bit error correction multi-bit error detection)
(error checking only) DRAM integrity Two-bank interleaving 16Mbit SDRAM support Two-bank four bank interleaving 64Mbit SDRAM support Supports maximum 16-bank interleave (i.e., pages open simultaneously); banks allocated based Independent SDRAM control each bank Seamless DRAM command scheduling maximum DRAM utilization (e.g., precharge other banks while accessing current bank) Four cache lines quadwords) DRAM write buffers Four cache lines quadwords) DRAM read prefetch buffers Read around write capability non-stalled read Burst read write operation BIOS shadow 16KB increment Decoupled burst DRAM refresh before self refresh
Advanced System Power Management Support Dynamic power down SDRAM (CKE) clock clock generator control suspend power plane preserves memory data Suspend-to-DRAM Self-Refresh operation SDRAM self-refresh power down bytes BIOS scratch registers Low-leakage pads Built-in NAND-tree scan test capability 3.3V, 0.35um, high speed power CMOS process Package
Preliminary Revision 1.02, January 2000
Features
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VT8371
OVERVIEW
KX133 VT8371 VT82C686A chipset high performance, cost-effective energy efficient system controller implementation desktop personal computer systems based 64-bit Slot-A (AMD Athlon) processors. Athlon Host
Address Data SYSCLK, SYSCLK# INTR, NMI, SMI#, STPCLK#, IGNNE#, FERR#, A20M#, PWROK, INIT#, RESET#
PROCRDY CONNECT CFWDRST
Graphics Controller
GCLK
KX133 VT8371
North Bridge
SUSCLK, SUSST1#
Memory
MCLK HCLK PCLK
SDRAM Clock Buffer
GCKRUN# PCKRUN#
PCLK
BIOS Ports AC97 Audio Codec AC97 Link MC97 Modem Codec Crystal
Super South
CPUSTP# PCISTP#
VT82C686A
South Bridge
SMBus Power Plane Peripheral Control GPIO ACPI Events Hardware Monitoring Inputs Keyboard Mouse Serial Ports Parallel Port Floppy Drive Interface MIDI Game Ports
Clock Generator
Figure KX133 System Block Diagram Using VT82C686A South Bridge
KX133 chip consists VT8371 system controller (516 BGA) VT82C686A bridge (352 BGA). system controller provides superior performance between CPU, DRAM, bus, with pipelined, burst, concurrent operation. VT8371 supports eight banks DRAMs DRAM controller supports standard Synchronous DRAM (SDRAM) Virtual Channel SDRAM SDRAM), flexible match manner. Synchronous DRAM interface allows zero wait state bursting between DRAM data buffers 66/100/133 MHz. eight banks DRAM composed arbitrary mixture 32MxN DRAMs. DRAM controller also supports optional (single-bit error correction multi-bit detection) (error checking) capability separately selectable bank-by-bank basis. VT8371 system controller also supports full v2.0 capability maximum utilization including mode transfers, (SideBand Addressing), Flush/Fence commands, pipelined grants. eight level request queue plus four level post-write request queue with thirty-two sixteen quadwords read write data FIFO's respectively included deep pipelined split transactions. single-level GART with full associative entries flexible remapping control also provided operation under protected mode operating environments. Both Windows-95 Windows-98 Windows 2000 miniport drivers supported interoperability with major AGP-based DVD-capable multimedia accelerators. VT8371 supports 32-bit system buses (one PCI) that synchronous pseudo-synchronous bus. chip also contains built-in bus-to-bus bridge allow simultaneous concurrent operations each bus. Five levels (doublewords) post write buffers included allow concurrent operation. master operation, fortyeight levels (doublewords) post write buffers sixteen levels (doublewords) prefetch buffers included concurrent Preliminary Revision 1.02, January 2000 -4Overview
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VT8371
DRAM/cache accesses. chip also supports enhanced commands such Memory-Read-Line, MemoryRead-Multiple Memory-Write-Invalid commands minimize snoop overhead. addition, advanced features supported such snoop ahead, snoop filtering, L1/L2 write-back forward master, L1/L2 write-back merged with post write buffers minimize master read latency DRAM utilization. Delay transaction read caching mechanisms also implemented further improvement overall system performance. 352-pin Ball Grid Array VT82C686A bridge supports four levels (doublewords) line buffers, type transfers delay transaction allow efficient utilization (PCI-2.1 compliant). VT82C686A also includes integrated keyboard controller with mouse support, integrated DS12885 style real time clock with extended byte CMOS RAM, integrated master mode enhanced controller with full scatter gather capability extension UltraDMA-33/66 33/66 MB/sec transfer rate, integrated interface with root four function ports with built-in physical layer transceivers, Distributed support, OnNow ACPI compliant advanced configuration power management interface. VT82C686A also includes AC97 MC97 link interface external audio modem codecs, "Super-I/O" functions (serial ports, parallel port, floppy drive interface game port). sophisticated power management, KX133 provides independent clock stop control SDRAM, PCI, buses Dynamic control powering down SDRAM. separate suspend-well plane implemented SDRAM control signals Suspend-to-DRAM operation. VT82C686A also includes complete hardware monitoring subsystem monitoring control internal external (motherboard system) conditions including voltages, temperatures, speeds, switch open/close states, etc. Coupled with VT82C686A south bridge chip, complete power conscious main board implemented with external TTLs. KX133 chipset ideal high performance, high quality, high energy efficient high integration desktop computer systems.
Preliminary Revision 1.02, January 2000
Overview

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