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KT133 VT8363
VT8363 KT133 ATHLONNORTH BRIDGE
Single-Chip North Bridge Socket-A (Socket-462) Based Athlon CPUs with Front Side Desktop Systems with plus Advanced Memory Controller supporting PC133 PC100 SDRAM
High Performance High Integration Athlon PC133 Chipset with Advanced System Power Management KT133 Chipset: VT8363 system controller VT82C686A bridge Single chip Athlon system controller with 64-bit Socket-A Athlon CPU, 64-bit system memory, 32-bit PCI-to-ISA bridge chip includes UltraDMA-33/66 EIDE, Ports, Integrated Super-I/O, AC97 MC97 link (for
Audio Modem support), Hardware Monitoring, Power Management, Keyboard PS2-Mouse Interfaces plus CMOS chip Supports separately powered 3.3V tolerant) interface system memory, AGP, Modular power management clock control advanced system power management interfaces
High Performance Athlon Interface Supports Socket-A (Socket-462) Athlon processors HSTL-like 1.5V high-speed transceiver logic signal levels Support independent address, data, snoop interfaces (Double Data Rate) transfer Athlon address data buses Built-in (Phase Lock Loop) circuitry optimal skew control within between clocking regions Four-entry command queue accommodate maximum throughput Four-entry probe queue stores probes from system processor Twenty four-entry processor system data control queue store system data control commands separate Supports (Write Combining) cycles Sleep mode support System management interrupt, memory remap STPCLK mechanism
read write buffers data movement processor interface
Preliminary Revision 1.0, 2000
Features
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KT133 VT8363
Full Featured Accelerated Graphics Port (AGP) Controller Synchronous pseudo-synchronous with host with optimal skew control
Mode synchronous v2.0 compliant Supports SideBand Addressing (SBA) mode (non-multiplexed address data) Supports modes signaling Pipelined split-transaction long-burst transfers 1GB/sec Thirty-two level read request queue Four level posted-write request queue Thirty-two level (quadwords) read data FIFO (256 bytes) Sixteen level (quadwords) write data FIFO (128 bytes) Intelligent request reordering maximum utilization Supports Flush/Fence commands Graphics Address Relocation Table (GART)
Windows OSR-2 integrated Windows Windows 2000 miniport driver support Concurrent Controller buses synchronous pseudo-synchronous host operation primary operation PCI-to-PCI bridge configuration 66MHz Supports five masters Peer concurrency Concurrent multiple master transactions; i.e., allow masters from both buses active same time Zero wait state master slave burst transfer rate system memory data streaming 132Mbyte/sec lines double-words) posted write buffers Byte merging write buffers reduce number cycles create further bursting possibilities Enhanced command optimization (MRL, MRM, MWI, etc.) Thirty-two levels (double-words) post write buffers from masters DRAM
(two cache lines double-words bus, cache lines double-words Athlon processor interface) Sixteen levels (double-words) prefetch buffers from DRAM access masters Delay transaction from master accessing DRAM Read caching master reading DRAM Transaction timer fair arbitration between masters (granularity clocks) Symmetric arbitration between Host/PCI optimized system performance Complete steerable interrupts PCI-2.2 compliant, 3.3V interface with tolerant inputs
level structure Sixteen entry fully associative page table replacement scheme
Preliminary Revision 1.0, 2000
Features
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KT133 VT8363
Advanced High-Performance DRAM Controller Supports PC133 PC100 SDRAM Virtual Channel Memory (VCM) SDRAM DIMMs Concurrent CPU, AGP, access Different DRAM types used mixed combinations Different DRAM timing each bank Dynamic Clock Enable (CKE) control SDRAM power reduction high speed systems Mixed 32MxN DRAMs Support memory space (256Mb DRAM technology) Flexible column addresses 64-bit data width 3.3V DRAM interface Programmable drive capability command, signals Two-bank interleaving 16Mbit SDRAM support Two-bank four bank interleaving 64Mbit SDRAM support Supports maximum 16-bank interleave (i.e., pages open simultaneously); banks allocated based Independent SDRAM control each bank Seamless DRAM command scheduling maximum DRAM utilization
(e.g., precharge other banks while accessing current bank) Four cache lines quadwords) DRAM write buffers Four cache lines quadwords) DRAM read prefetch buffers Read around write capability non-stalled read Burst read write operation BIOS shadow 16KB increment Decoupled burst DRAM refresh with staggered timing before self refresh
Advanced System Power Management Support Dynamic power down SDRAM (CKE) clock clock generator control suspend power plane preserves memory data Suspend-to-DRAM Self-Refresh operation SDRAM self-refresh power down bytes BIOS scratch registers Low-leakage pads Built-in NAND-tree scan test capability 3.3V, 0.35um, high speed power CMOS process Package
Preliminary Revision 1.0, 2000
Features
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KT133 VT8363
OVERVIEW
KT133 VT8363 VT82C686A chipset high performance, cost-effective energy efficient system controller implementation desktop personal computer systems based 64-bit Socket-A (AMD Athlon) processors. Athlon Host
Address Data SYSCLK, SYSCLK# INTR, NMI, SMI#, STPCLK#, IGNNE#, FERR#, A20M#, PWROK, INIT#, RESET#
PROCRDY CONNECT CFWDRST
Graphics Controller
GCLK
KT133 VT8363
North Bridge
SUSCLK, SUSST1#
Memory
MCLK HCLK PCLK
SDRAM Clock Buffer
GCKRUN# PCKRUN#
PCLK
BIOS Ports AC97 Audio Codec AC97 Link MC97 Modem Codec Crystal
Super South
CPUSTP# PCISTP#
VT82C686A
South Bridge
SMBus Power Plane Peripheral Control GPIO ACPI Events Hardware Monitoring Inputs Keyboard Mouse Serial Ports Parallel Port Floppy Drive Interface MIDI Game Ports
Clock Generator
Figure KT133 System Block Diagram Using VT82C686A South Bridge
KT133 chip consists VT8363 system controller (552 BGA) VT82C686A bridge (352 BGA). system controller provides superior performance between CPU, DRAM, bus, with pipelined, burst, concurrent operation. VT8363 supports eight banks DRAMs DRAM controller supports standard Synchronous DRAM (SDRAM) Virtual Channel SDRAM SDRAM), flexible match manner. Synchronous DRAM interface allows zero wait state bursting between DRAM data buffers 66/100/133 MHz. banks DRAM composed arbitrary mixture 32MxN DRAMs. VT8363 system controller also supports full v2.0 capability maximum utilization including mode transfers, (SideBand Addressing), Flush/Fence commands, pipelined grants. eight level request queue plus four level post-write request queue with thirty-two sixteen quadwords read write data FIFO's respectively included deep pipelined split transactions. single-level GART with full associative entries flexible remapping control also provided operation under protected mode operating environments. Both Windows-95 Windows-98 Windows 2000 miniport drivers supported interoperability with major AGP-based DVD-capable multimedia accelerators. VT8363 supports 32-bit system buses (one PCI) that synchronous pseudo-synchronous bus. chip also contains built-in bus-to-bus bridge allow simultaneous concurrent operations each bus. Five levels (doublewords) post write buffers included allow concurrent operation. master operation, fortyeight levels (doublewords) post write buffers sixteen levels (doublewords) prefetch buffers included concurrent DRAM/cache accesses. chip also supports enhanced commands such Memory-Read-Line, Memory-
Preliminary Revision 1.0, 2000
Overview
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KT133 VT8363
Read-Multiple Memory-Write-Invalid commands minimize snoop overhead. addition, advanced features supported such snoop ahead, snoop filtering, L1/L2 write-back forward master, L1/L2 write-back merged with post write buffers minimize master read latency DRAM utilization. Delay transaction read caching mechanisms also implemented further improvement overall system performance. 352-pin Ball Grid Array VT82C686A bridge supports four levels (doublewords) line buffers, type transfers delay transaction allow efficient utilization (PCI-2.1 compliant). VT82C686A also includes integrated keyboard controller with mouse support, integrated DS12885 style real time clock with extended byte CMOS RAM, integrated master mode enhanced controller with full scatter gather capability extension UltraDMA-33/66 33/66 MB/sec transfer rate, integrated interface with root four function ports with built-in physical layer transceivers, Distributed support, OnNow ACPI compliant advanced configuration power management interface. VT82C686A also includes AC97 MC97 link interface external audio modem codecs, "Super-I/O" functions (serial ports, parallel port, floppy drive interface game port). sophisticated power management, KT133 provides independent clock stop control SDRAM, PCI, buses Dynamic control powering down SDRAM. separate suspend-well plane implemented SDRAM control signals Suspend-to-DRAM operation. VT82C686A also includes complete hardware monitoring subsystem monitoring control internal external (motherboard system) conditions including voltages, temperatures, speeds, switch open/close states, etc. Coupled with VT82C686A south bridge chip, complete power conscious main board implemented with external TTLs. KT133 chipset ideal high performance, high quality, high energy efficient high integration desktop computer systems.
Preliminary Revision 1.0, 2000
Overview
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KT133 VT8363
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings Parameter
Ambient operating temperature Case operating temperature Storage temperature Input voltage Output voltage (VCC 3.6V)
-0.5 -0.5
Unit
Volts Volts
Note: Stress above conditions listed cause permanent damage device. Functional operation this device should restricted conditions described under operating conditions.
Characteristics
TA-0-55oC, VCC=5V+/-5%, GND=0V
Symbol
Parameter
Input voltage Input high voltage Output voltage Output high voltage Input leakage current Tristate leakage current Power supply current
-0.50
VCC+0.5 0.45 +/-10 +/-20
Unit
Condition
IOL=4.0mA IOH=-1.0mA 0<VIN<VCC 0.45<VOUT<VCC
Timing Specifications
timing specifications provided based external zero-pf capacitance load. Min/max cases based following table:
Table Timing Conditions
Parameter
3.3V Power (VCC, VCCI, VTT, AVCC, HVCC) Reference (5VREF) Temperature Drive strength each output programmable. Rx6D details.
3.135 4.75
3.465 5.25
Unit
Volts Volts
Preliminary Revision 1.0, 2000
-46-
Electrical Specifications
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KT133 VT8363
MECHANICAL SPECIFICATIONS
&251(5
Date Code Year Date Code Week Chip Revision Code
<<::55 7$,:$1 /////////
552-Pin
35x35x2.33 JEDEC Spec MO-151
6($7,1* 3/$1(
Figure Mechanical Specifications 552-Pin Ball Grid Array Package
Preliminary Revision 1.0, 2000
-47-
Mechanical Specifications

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