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VT82C596B
REVISION HISTORY
Document Release Revision Date 2/23/99 Revision Initial release based 82C596A Data Sheet revision Added UltraDMA-66 feature bullets overview Added integrated APIC (changed H18, K18, descriptions) Added note CMOS Register Summary Added changed function Rx42[6], Rx48[7-4], Rx5B[3], Rx5C[7-4, Rx74[29-24, Rx87-89 Added changed function Rx8, Rx4D[2-0], Rx54-55, Rx58-5B, Rx90-91, RxD2-D6 (80-88 renumbered), Offset 0[11], 20[14, 7-1], 22[14, 7-1], 24[14, 7-1], 28[15-11], 2A[15-11], 2C[11-10], 38[2-1], 44[10-1], 4C[30-0] Updated feature bullets, overview, descriptions Replaced function with registers from 686B reflect UltraDMA-66 Added changed function registers Rx42[7-6, Rx58-5B, Offset 0[8], 2C[2], 30[10-0], 34[10-0], 38[6, 4-3], (removed) Changed Function Rx42[2-0], 43[5-4], default, 55[3-0], 57[3-0], 58[3-0], 88[5], Function RxD, 42-43, 45[3-2], 54[4-3], 74-75, 7C-7D, Function Rx41[7-3], Function Rx4C-4F default value Initials
Revision
3/9/99
Revision
6/17/99
Revision June 1999
Revision History
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VT82C596B
TABLE CONTENTS
REVISION HISTORY.I TABLE CONTENTS. LIST FIGURES.IV LIST TABLES OVERVIEW PINOUTS REGISTERS REGISTER OVERVIEW CONFIGURATION SPACE REGISTER DESCRIPTIONS. Legacy Ports
Keyboard Controller Registers. Controller Registers Interrupt Controller Registers Timer Counter Registers CMOS Registers.
Function Registers Bridge.
Configuration Space Header Control. Plug Play Control Distributed Serial Control Miscellaneous General Purpose I/O.
Function Registers Enhanced Controller
Configuration Space Header IDE-Controller-Specific Confiiguration Registers Registers.
Function Registers Universal Serial Controller.
Configuration Space Header USB-Specific Configuration Registers. Registers.
Function Registers Power Management SMBus
Configuration Space Header Power Management-Specific Configuration Registers System Management Bus-Specific Configuration Registers System Management I/O-Space Registers. Power Management I/O-Space Registers
FUNCTIONAL DESCRIPTIONS POWER MANAGEMENT
Power Management Subsystem Overview Processor States System Suspend States Power Plane Control General Purpose Ports. Power Management Events System Processor Resume Events Legacy Power Management Timers System Primary Secondary Events Peripheral Events
ELECTRICAL SPECIFICATIONS.
Revision June 1999
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Table Contents
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VT82C596B
ABSOLUTE MAXIMUM RATINGS CHARACTERISTICS. TIMING SPECIFICATIONS PACKAGE MECHANICAL SPECIFICATIONS
Revision June 1999
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Table Contents
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VT82C596B
LIST FIGURES
FIGURE SYSTEM CONFIGURATION USING VT82C596B FIGURE VT82C596B BALL DIAGRAM (TOP VIEW). FIGURE VT82C596B LIST (NUMERICAL ORDER). FIGURE VT82C596B LIST (ALPHABETICAL ORDER). FIGURE STRAP OPTION CIRCUIT. FIGURE POWER MANAGEMENT SUBSYSTEM BLOCK DIAGRAM FIGURE ULTRADMA-33 TIMING DRIVE INITIATING BURST READ COMMAND. FIGURE ULTRADMA-33 TIMING DRIVE INITIATING BURST WRITE COMMAND. FIGURE ULTRADMA-33 TIMING PAUSING BURST FIGURE ULTRADMA-33 TIMING DRIVE TERMINATING BURST DURING READ COMMAND. FIGURE ULTRADMA-33 TIMING DRIVE TERMINATING BURST DURING WRITE COMMAND FIGURE ULTRADMA-33 TIMING HOST TERMINATING BURST DURING READ COMMAND. FIGURE ULTRADMA-33 TIMING HOST TERMINATING BURST DURING WRITE COMMAND FIGURE ULTRADMA-33 TIMING CYCLE FIGURE MECHANICAL SPECIFICATIONS 324-PIN BALL GRID ARRAY PACKAGE
LIST TABLES
TABLE TABLE TABLE TABLE TABLE TABLE TABLE DESCRIPTIONS. SYSTEM REGISTERS. KEYBOARD CONTROLLER COMMAND CODES CMOS REGISTER SUMMARY. CHARACTERISTICS CYCLE TIMING. CHARACTERISTICS ULTRADMA-33 INTERFACE TIMING.
Revision June 1999
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Table Contents
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VT82C596B
VT82C596B PIPC
INTEGRATED PERIPHERAL CONTROLLER PC98 COMPLIANT PCI-TO-ISA BRIDGE WITH ACPI, ENHANCED POWER MANAGEMENT, SMBUS, APIC, DISTRIBUTED DMA, SERIAL IRQ, PLUG PLAY, ULTRADMA-33/66 MASTER MODE PCI-EIDE CONTROLLER, CONTROLLER, KEYBOARD CONTROLLER,
Inter-operable with other Host-to-PCI Bridges Combine with VT82C598 (Apollo MVP3) complete 100MHz Socket-7 system Combine with VT82C693 (Apollo ProPlus) complete Socket-370 Slot-1 system Combine with VT82C693A (Apollo Pro133) complete Skt-370 Slot-1 system PC98 Compliant Bridge
Integrated Controller with integrated DMA, timer, interrupt controller Integrated Keyboard Controller with mouse support Integrated DS12885-style Real Time Clock with extended byte CMOS Day/Month Alarm ACPI Integrated Controller with root function ports Integrated UltraDMA-33/66 master mode EIDE controller with enhanced commands PCI-2.1 compliant with delay transaction Eight double-word line buffer between One-level post-write buffer Supports type transfers Distributed support legacy across Sideband signal support PC/PCI serial interrupt docking non-docking applications Serial Interrupt input Fast reset Gate operation Edge trigger level-sensitive interrupts Flash EPROM, EPROM combined BIOS support Supports positive subtractive decoding
Universal Serial Controller
v.1.1 Intel Universal v.1.1 compatible Eighteen level (doublewords) data FIFO with full scatter gather capabilities Root function ports Integrated physical layer transceivers with over-current detection status inputs Legacy keyboard PS/2 mouse support
Advanced Programmable Interrupt Controller (APIC)
Integrated on-chip Control pins provided support optional external APIC Used extend system interrupt capability PC98 compliant
Revision June 1999
Features
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VT82C596B
UltraDMA-33/66 Master Mode EIDE Controller
Dual channel master mode supporting four Enhanced devices Transfer rate 22MB/sec cover mode multi-word mode drives, beyond Extension UltraDMA-33 interface transfer rates 33MB/sec Extension UltraDMA-66 interface transfer rates 66MB/sec Thirty-two levels (doublewords) prefetch write buffers Dual engine concurrent dual channel operation master programming interface SFF-8038i rev.1.0 Windows-95 compliant Full scatter gather capability Support ATAPI compliant devices including devices Support native compatibility modes Complete software driver support Supports glue-less "Swap-Bay" option with full electrical isolation
System Management Interface Host interface processor communications Slave interface external SMBus masters
Sophisticated PC98-Compatible Mobile Power Management
Supports both ACPI (Advanced Configuration Power Interface) legacy (APM) power management ACPI v1.0 Compliant v1.2 Compliant clock throttling clock stop control complete ACPI state support clock PCI/CPU clock generator stop control Supports multiple system suspend types: power-on suspends with flexible CPU/PCI reset options, suspend DRAM, suspend disk (soft-off), with hardware automatic wake-up Multiple suspend power plane controls suspend status indicators idle timer, peripheral timer general purpose timer, plus 24/32-bit ACPI compliant timer Normal, doze, sleep, suspend conserve modes Global local device power control System event monitoring with event classes Primary secondary interrupt differentiation individual channels Dedicated input pins power sleep buttons, external modem ring indicator, notebook open/close system wake-up general purpose input ports output ports Multiple internal external sources flexible power management models programmable chip selects microcontroller chip select Enhanced integrated real time clock (RTC) with date alarm, month alarm, century field Thermal alarm support Cache SRAM power-down control docking support leakage control
Plug Play Controller interrupts steerable interrupt channel Dual interrupt signal steering on-board plug play devices Microsoft Windows 95and plug play BIOS compliant
Built-in NAND-tree scan test capability 0.5u, 3.3V, power CMOS process Single chip
Revision June 1999
Features
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VT82C596B
OVERVIEW
VT82C596B south bridge high integration, high performance, power-efficient, high compatibility device that supports bridge functionality make complete Microsoft PC98-compliant system. addition complete extension functionality, VT82C596B includes standard intelligent peripheral controllers: Master mode enhanced controller with dual channel engine interlaced dual channel commands. Dedicated FIFO coupled with scatter gather master mode operation allows high performance transfers between devices. addition standard mode operation, VT82C596B also supports UltraDMA-33 standard allow reliable data transfer rates 33MB/sec throughput UltraDMA-66 standard 66MB/sec data transfer. controller SFF-8038i v1.0 Microsoft Windows-95 compliant. Universal Serial controller that v1.1 Universal v1.1 compliant. VT82C596B includes root with function ports with integrated physical layer transceivers. controller allows plug play isochronous peripherals inserted into system with universal driver support. controller also implements legacy keyboard mouse support that legacy software transparently non-USB-aware operating system environment. Keyboard controller with mouse support. Real Time Clock with byte extended CMOS. addition standard functionality, integrated also includes date alarm, century field, other enhancements compatibility with ACPI standard. Notebook-class power management functionality compliant with ACPI legacy requirements. Multiple sleep states (power-on suspend, suspend-to-DRAM, suspend-to-Disk) supported with hardware automatic wake-up. Additional functionality includes event monitoring, clock throttling stop (Intel processor protocol), clock stop control, modular power, clock leakage control, hardware-based software-based event handling, general purpose I/O, chip select external SMI. Full System Management (SMBus) interface. Distributed capability support legacy over bus. PC/PCI Serial mechanisms also supported docking non-docking applications. Plug Play controller that allows complete steerability interrupts interrupt channel. Three additional steerable interrupt channels provided allow plug play reconfigurability on-board peripherals Windows compliance. Integrated APIC (see Win98 Hardware Design Guide) VT82C596B also enhances functionality standard peripherals. integrated interrupt controller supports both edge level triggered interrupts channel channel. integrated controller supports type addition standard modes. Compliant with PCI-2.1 specification, VT82C596B supports delayed transactions that slower peripherals block traffic bus. Special circuitry built allow concurrent operation without causing dead lock even PCI-to-PCI bridge environment. chip also includes eight levels (doublewords) line buffers from further enhance overall system performance.
Cache Sideband Signals: Init CPUreset StopClk FERR IGNNE Boot North Bridge MA/Command (Module VT82C596B Crystal Expansion Cards GPIO, Power Control, Reset System Memory
Figure System Configuration Using VT82C596B
Revision June 1999
Overview

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