Velio VC1003 8-lane Serializer Deserializer which operates from 3.125

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Velio VC1003 8-lane Serializer Deserializer which operates from 3.125

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3.125 Gbps Eight-Lane CMOS SerDes (Serializer Deserializer)
Velio VC1003 8-lane Serializer Deserializer which operates from 3.125 Gbps, (and half these rates). device designed flexibility; multiple configuration options, allowing operation tailored specific system environments.
Table VC1003 Features Benefits
transmitters accept parallel data several formats speeds, depending upon configuration. receivers accept serial data, recover clock data, then deserialize data into several formats, depending upon configuration.
FEATURES Eight 3.125 Gbps (and half-rate) SERDES Lanes Core Voltage Supply Typical Power High-Speed Serial with Programmable Output Voltage Swing SSTL_2 ASIC-side Adjustable Pre-Emphasis Serial Outputs Typical Receiver Sensitivity Compensated On-Chip Termination Resistors Serial Outputs Inputs 8b/10 encoder/decoder (and bypass mode) bit/Lane ASIC Interface (10-bit mode) bit/Lane ASIC Interface (8-bit/10-bit mode) Self-Test with PRBS Generation TBGA
BENEFITS Integration conserves board space, reduces power Voltage Core reduces power consumption Reduces overall system power requirements Serial Output Signal tailored specific system conditions Popular standard flexible ASIC design Reduces Inter-Symbol-Interference, enables serial transmission over longer distances Reduces noisy lossy signals Internal compensation ensures matched impedances, reducing transmission reflections Performs 8b/10b encode decode Multiple bit/Lane modes support 8b/10b SONET data streams Enables in-system testing diagnostics Space-saving, thermally enhanced package
APPLICATIONS
Gigabit Ethernet SONET Backplanes Infiniband Backplane applications Optical Transceiver Interface
Figure VC1003 Transmit Signal 3.125 Gbps
COPYRIGHT 2001 VELIO COMMUNICATIONS, INC. TASMAN DRIVE, MILPITAS, 95035 MAIN PHONE: (408) 474-0700 HTTP://WWW.VELIO.COM MARCH 2001 REVISION
FUNCTIONAL OVERVIEW
Configurable Serial Outputs Signal Integrity
FIFO 8b10b ASIC FIFO 8b10b ASIC FIFO 8b10b ASIC FIFO 8b10b ASIC FIFO 8b10b ASIC FIFO 8b10b FIFO 8b10b TXASIC ASIC 8b10b ASIC
VC1003 utilizes programmable SERializer DESerializer core high-speed serial signals. user-selectable features uniquely address Inter-Symbol Interference (ISI), help ensure signal integrity multi-gigabit speeds.
Programmable Pre-Emphasis
FIFO 10b8b Demux ASIC FIFO 10b8b Demux ASIC FIFO 10b8b Demux ASIC FIFO 10b8b Demux ASIC FIFO 10b8b Demux ASIC FIFO 10b8b Demux ASIC FIFO 10b8b Demux ASIC Demux 10b8b ASIC
counteract effects ISI, VC1003 serial output signal optional pre-emphasis component. This results detectable data signal over longer trace lengths.
Internal Termination Resistors
Clock Multiplier
Termination Reference
Figure VC1003 Block Diagram
Termination resistors provided serial input, well serial output. Input termination resistors common these speeds, internal output termination deserves special mention. absorbs reflections from impedance discontinuities, increasing available signal margin. value each internal termination resistors closely matched that single external resistor placed across RREF+ RREF- pins.
PRE-EMPHASIS EFFECTS SIGNAL INTEGRITY
Figure 3.125 Gbps Signal Sent Over One-Meter Backplane Plus Connectors (Pre-Emphasis Turned OFF)
Figure 3.125 Gbps Signal Sent Over One-Meter Backplane Plus Connectors (Pre-Emphasis Turned
Velio reserves right change products without notice. Velio advises customers obtain latest version information prior committing device application. Nothing herein grants license intellectual property rights Velio third party. Velio trademark Velio Communications, Incorporated. Copyright 2001 Velio Communications, Incorporated.
VELIO COMMUNICATIONS, INC. MARCH 2001 REVISION

Velio VC1003 8-lane Serializer Deserializer which operates from 3.125

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