SST45VF512 SST45VF010 SST45VF020 FEATURES: Single 2.7-3.6V Read W

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SST45VF512 SST45VF010 SST45VF020 FEATURES: Single 2.7-3.6V Read W

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Kbit Mbit Mbit Serial Flash
SST45VF512 SST45VF010 SST45VF020
FEATURES: Single 2.7-3.6V Read Write Operations Serial Interface Architecture Compatible: Mode Mode Byte Serial Read with Single Command Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption: Active Current: (typical) Standby Current: (typical) Sector Chip-Erase Capability Uniform KByte sectors Fast Erase Byte-Program: Chip-Erase Time: (typical) Sector-Erase Time: (typical) Byte-Program Time: (typical) Automatic Write Timing Internal Generation End-of-Write Detection Software Status Clock Frequency Hardware Reset (RESET#) Resets device Standby Mode CMOS Compatibility Hardware Data Protection Protects unprotects device from Write operation Packages Available 8-Pin SOIC (4.9mm 6mm)
PRODUCT DESCRIPTION SST45VF512, SST45VF010 SST45VF020 manufactured with SST's proprietary, high performance CMOS SuperFlash technology. Serial Flash organized sectors 4096 Bytes SST45VF512, sectors 4096 Bytes SST45VF010 sectors 4096 Bytes SST45VF020. memory accessed Read Erase/Program compatible serial protocol. signals are: serial data input (SI), serial data output (SO), serial clock (SCK), write protect (WP#), chip enable (CE#), hardware reset (RESET#). SST45VFxxx devices offered 8-pin SOIC package. Figure pinout. Device Operation SST45VFxxx uses cycles bits each commands, data, addresses execute operations. operation instructions listed Table instructions synchronized high transition CE#. first high transition will initiate instruction sequence. Inputs will accepted rising edge starting with most significant bit. high transition before input instruction completes will terminate instruction progress return device standby mode.
Read Read operation outputs data order from initial accessed address. While input, address will incremented automatically until (top) address space, then internal address pointer automatically increments beginning (bottom) address space (00000H), data stream will continue. read data stream continuous through addresses until terminated high transition CE#. Sector/Chip-Erase Operation Sector-Erase operation clears bits selected sector "FF". Chip-Erase instruction clears bits device "FF". Byte-Program Operation Byte-Program operation programs bits selected byte desired data. selected byte must erased state ("FF") when initiating Program operation. data input from order. Software Status Operation Status operation determines Erase Program operation progress. Erase Program operation progress, device busy. device ready valid operation. status read continuous with ongoing clock cycles until terminated high transition CE#.
2000 Silicon Storage Technology, Inc. logo SuperFlash registered trademarks Silicon Storage Technology, Inc. These specifications subject change without notice. 514-1 10/00 S71178
Kbit Mbit Mbit Serial Flash SST45VF512 SST45VF010 SST45VF020
Advance Information Reset Reset will terminate operation, e.g., Read, Erase Program, progress. activated high transition RESET# pin. device will remain reset condition long RESET# low. Minimum reset time 10µs. Figure reset timing diagram. RESET# internally pulled-up could remain unconnected during normal operation. After reset, device standby mode, high transition required start next operation. internal power-on reset circuit protects against accidental data writes. Applying logic level RESET# during power-on process then changing logic level high when reached correct voltage level will provide additional protection against accidental writes during power Read ID/Read Device Read Read Device operations read JEDEC assigned manufacturer identification manufacturer assigned device identification codes. These codes used determine actual device resident system. FUNCTIONAL BLOCK DIAGRAM TABLE PRODUCT IDENTIFICATION Manufacturer's Device SST45VF512 SST45VF010 SST45VF020 Byte 0000 0001 0001 0001 Data
T1.4
Write Protect provides inadvertent write protection. must held high Erase Program operation. "don't care" other operations. typical use, connected with standard pull-down resistor. then driven high whenever Erase Program operation required. tied with pull-up resistor, then operations occur write protection feature disabled. internal pull-up could remain unconnected when used.
Address Buffers Latches
Decoder
SuperFlash Cell Array
Decoder
Control Logic
Buffers Data Latches
Serial Interface
2000 Silicon Storage Technology, Inc.
RESET#
514ILL B1.0
S71178
514-1 10/00
Kbit Mbit Mbit Serial Flash SST45VF512 SST45VF010 SST45VF020
RESET#
Standard Pinout
View
F01.0
FIGURE ASSIGNMENTS 8-PIN SOIC
TABLE DESCRIPTION Symbol Name Serial Clock
Functions provide timing serial interface. Commands, addresses, input data latched rising edge clock input, while output data shifted falling edge clock input. transfer commands, addresses, data serially into device. Inputs latched rising edge serial clock. transfer data serially device. Data shifted falling edge serial clock. device enabled high transition CE#. protect device from unintentional Write (Erase Program) operations. When low, Erase Program commands ignored. When high, device erased programmed. This internal pull-up could remain unconnected when used. high transition RESET# will terminate operation progress reset internal logic standby mode. device will remain reset condition long RESET# low. Operations only occur when RESET# high. This internal pull-up could remain unconnected when used. provide power supply (2.7-3.6V).
T2.2
Serial Data Input Serial Data Output Chip Enable Write Protect
RESET#
Reset
Power Supply Ground
2000 Silicon Storage Technology, Inc.
S71178
514-1 10/00
Kbit Mbit Mbit Serial Flash SST45VF512 SST45VF010 SST45VF020
Advance Information TABLE DEVICE OPERATION INSTRUCTIONS Cycle Operation/Type Read Sector-Erase2 Chip-Erase Byte-Program Software-Status Read Read Device Command Address1 A23-A16 A23-A16 A23-A16 Dout Address A15-A8 A15-A8 A15-A8 Address A7-A0 A7-A0 A0=0 A0=1 Data Device
T3.3
Dummy
after Data Dout
Notes: A23-A16 "Don't Care" SST45VF512, A23-A17 "Don't Care" SST45VF010, A23-A18 "Don't Care" SST45VF020. A16-A12 used determine sector address, A11-A8 don't care. With A15-A1 SST45VF512 Device 41H, read with With A16-A1 SST45VF010 Device 45H, read with With A17-A1 SST45VF020 Device 43H, read with
TABLE DEVICE OPERATION TABLE Operation Read Sector-Erase Chip-Erase Byte-Program Software-Status Reset2 Read Read Device Dout Dout Dout Dout CE#1 High High High RESET# High High High High High High High
T4.1
Notes: high transition will required start device operation except Reset. RESET# will return device standby terminate Erase Program operation progress.
2000 Silicon Storage Technology, Inc.
S71178
514-1 10/00
Kbit Mbit Mbit Serial Flash SST45VF512 SST45VF010 SST45VF020
Advance Information Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V 0.5V Transient Voltage (<20 Ground Potential -1.0V 1.0V Package Power Dissipation Capability 25°C) 1.0W Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current1
OPERATING RANGE Range Ambient Temp Commercial
CONDITIONS TEST 2.7-3.6V Input Rise/Fall Time Output Load Figures
TABLE OPERATING CHARACTERISTICS 2.7-3.6V Limits Symbol Parameter Units VIHC Power Supply Current Read Program Erase Standby Current Input Leakage Current Output Leakage Current Input Current(2) Input Voltage Input High Voltage Input High Voltage (CMOS) VDD-0.3 Output Voltage Output High Voltage VDD-0.2
Test Conditions VIL, Max. VIL, Max. VIHC, Max. =GND VDD, Max. VOUT =GND VDD, Max. WP#, RESET# Min. Max. Max. Min. -100 Min.
T5.2
Note: Outputs shorted more than second. more than output shorted time. This parameter only applies RESET# pins.
2000 Silicon Storage Technology, Inc.
S71178
514-1 10/00
Kbit Mbit Mbit Serial Flash SST45VF512 SST45VF010 SST45VF020
Advance Information TABLE CAPACITANCE Mhz, other pins open) Parameter Description Test Condition COUT CIN1
Maximum
T6.0
Output Capacitance Input Capacitance
VOUT
TABLE RELIABILITY CHARACTERISTICS Symbol Parameter NEND TDR1 VZAP_HBM1 VZAP_MM1 ILTH1
Minimum Specification 10,000 2000
Units Cycles Years Volts Volts
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard
T7.0
Endurance Data Retention Susceptibility Human Body Model Susceptibility Machine Model Latch
Note: This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE OPERATING CHARACTERISTICS 2.7-3.6V Symbol FCLK TSCKH TSCKL TCES TCEH TCPH TCHZ TCLZ TRLZ TWPS TWPH TSCE TRST TREC TPURST Parameter Serial Clock Frequency Serial Clock High Time Serial Clock Time Setup Time Hold Time High Time High High-Z Output Low-Z Output RESET# High-Z Output Data Setup Time Data Hold Time Output Hold from Change Output Valid from Write Protect Setup Time Write Protect Hold Time Sector-Erase Chip-Erase Byte-Program Reset Pulse Width Reset Recovery Time Reset Time After Power-Up Limits Units
T8.2
2000 Silicon Storage Technology, Inc.
S71178
514-1 10/00
Kbit Mbit Mbit Serial Flash SST45VF512 SST45VF010 SST45VF020
VIHT
INPUT
REFERENCE POINTS
OUTPUT
F02.0
VILT
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.5 VDD) (0.5 VDD) Input rise fall times (10% 90%)
Note: VIT-VINPUT Test VOT-VOUTPUT Test VIHT-VINPUT HIGH Test VILT-VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TESTER
F03.0
FIGURE TEST LOAD EXAMPLE
2000 Silicon Storage Technology, Inc.
S71178
514-1 10/00
Kbit Mbit Mbit Serial Flash SST45VF512 SST45VF010 SST45VF020
TCPH TCES TSCKH TSCKL TCEH
DATA VALID HIGH-Z HIGH-Z
F04.0
FIGURE SERIAL INPUT TIMING DIAGRAM (INACTIVE SERIAL CLOCK MODE
TSCKH TSCKL TCLZ
F05.0
TCEH
DATA VALID
TCHZ
FIGURE SERIAL OUTPUT TIMING DIAGRAM (INACTIVE SERIAL CLOCK MODE
2000 Silicon Storage Technology, Inc.
S71178
514-1 10/00
Kbit Mbit Mbit Serial Flash SST45VF512 SST45VF010 SST45VF020
TCPH TCES TSCKL TSCKH TCEH
DATA VALID HIGH-Z HIGH-Z
F17.0
FIGURE SERIAL INPUT TIMING DIAGRAM (INACTIVE SERIAL CLOCK HIGH MODE
TSCKH TSCKL TCLZ
F18.0
TCEH
TCHZ
DATA VALID
FIGURE SERIAL OUTPUT TIMING DIAGRAM (INACTIVE SERIAL CLOCK HIGH MODE
2000 Silicon Storage Technology, Inc.
S71178
514-1 10/00
Kbit Mbit Mbit Serial Flash SST45VF512 SST45VF010 SST45VF020
TWPS
TWPH
SELF-TIMED SECTORERASE CYCLE
ADD.
ADD.
HIGH IMPEDANCE
F06.1
FIGURE SECTOR-ERASE TIMING DIAGRAM
TWPS
TWPH
TSCE
SELF-TIMED CHIPERASE CYCLE
HIGH IMPEDANCE
F07.1
FIGURE CHIP-ERASE TIMING DIAGRAM
2000 Silicon Storage Technology, Inc.
S71178
514-1 10/00
Kbit Mbit Mbit Serial Flash SST45VF512 SST45VF010 SST45VF020
TWPS TWPH
SELF-TIMED BYTEPROGRAM CYCLE
ADD.
ADD.
ADD.
HIGH IMPEDANCE
F08.1
FIGURE BYTE-PROGRAM TIMING DIAGRAM
ADD.
ADD.
ADD.
Dout Dout Dout
F10.1
HIGH IMPEDANCE
FIGURE READ TIMING DIAGRAM
2000 Silicon Storage Technology, Inc.
S71178
514-1 10/00
Kbit Mbit Mbit Serial Flash SST45VF512 SST45VF010 SST45VF020
ADD1
HIGH IMPEDANCE
Dout1
F19.5
Note: Manufacturer's read with A0=0 SST45VF512 Device read with A0=1 SST45VF010 Device read with A0=1 SST45VF020 Device read with A0=1
FIGURE READ-ID TIMING DIAGRAM
HIGH IMPEDANCE
DATA
DATA
DATA
F11.1
FIGURE SOFTWARE-STATUS TIMING DIAGRAM
2000 Silicon Storage Technology, Inc.
S71178
514-1 10/00
Kbit Mbit Mbit Serial Flash SST45VF512 SST45VF010 SST45VF020
TREC TCES
TRST
RESET#
HIGH IMPEDANCE
TRLZ
HIGH IMPEDANCE
F20.0
FIGURE RESET TIMING DIAGRAM (INACTIVE CLOCK POLARITY SHOWN)
TPURST
TREC
RESET#
F13.0
FIGURE POWER-ON RESET TIMING DIAGRAM
TWPS
TWPH
F14.0
TCPH TCES TCEH
FIGURE WRITE PROTECT TIMING DIAGRAM
2000 Silicon Storage Technology, Inc. S71178 514-1 10/00
Kbit Mbit Mbit Serial Flash SST45VF512 SST45VF010 SST45VF020
Device SST45VFxxx
Speed Suffix1
Suffix2 Package Modifier pins Package Type SOIC Temperature Range Commercial 70°C Minimum Endurance 10,000 cycles Operating Frequency Device Density Kilobit Megabit Megabit Voltage Range 2.7-3.6V
SST45VF512 Valid combinations SST45VF512-10-4C-SA SST45VF010 Valid combinations SST45VF010-10-4C-SA SST45VF020 Valid combinations SST45VF020-10-4C-SA
Example: Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
2000 Silicon Storage Technology, Inc.
S71178
514-1 10/00
Kbit Mbit Mbit Serial Flash SST45VF512 SST45VF010 SST45VF020
Advance Information PACKAGING DIAGRAMS
4.00 3.80 6.20 5.80
Identifier
1.75 1.35 places
Note:
places
1.27
0.25 0.10
0.25 0.19
1.27 0.40
8.soic-SA-ILL.3
Complies with JEDEC publication MS-012 dimensions, although some dimensions more stringent. linear dimensions millimeters (min/max). Coplanarity: (±.05)
8-PIN SMALL OUTLINE INTEGRATED CIRCUIT PACKAGE (SOIC) PACKAGE CODE:
2000 Silicon Storage Technology, Inc.
S71178
514-1 10/00
Kbit Mbit Mbit Serial Flash SST45VF512 SST45VF010 SST45VF020
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.ssti.com Literature FaxBack 888-221-1178, International 732-544-2873
2000 Silicon Storage Technology, Inc.
S71178
514-1 10/00

SST45VF512 SST45VF010 SST45VF020 FEATURES: Single 2.7-3.6V Read W

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